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TestSystem.vhd 3.6KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 12.07.2021 08:34:17
  6. -- Design Name:
  7. -- Module Name: TestSystem - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity TestSystem is
  30. -- Port ( );
  31. end TestSystem;
  32. architecture Behavioral of TestSystem is
  33. component System is
  34. Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
  35. vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
  36. vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
  37. Hsync : out STD_LOGIC;
  38. Vsync : out STD_LOGIC;
  39. PS2Clk : in STD_LOGIC;
  40. PS2Data : in STD_LOGIC;
  41. btnC : in STD_LOGIC;
  42. CLK : STD_LOGIC);
  43. end component;
  44. signal CLK : STD_LOGIC := '0';
  45. signal btnC : STD_LOGIC := '0';
  46. signal PS2Clk : STD_LOGIC := '0';
  47. signal PS2Data : STD_LOGIC := '0';
  48. signal vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
  49. signal vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
  50. signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
  51. signal Hsync : STD_LOGIC := '0';
  52. signal Vsync : STD_LOGIC := '0';
  53. constant CLK_period : time := 10 ns;
  54. begin
  55. instance : System
  56. port map (vgaRed => vgaRed,
  57. vgaBlue => vgaBlue,
  58. vgaGreen => vgaGreen,
  59. Hsync => Hsync,
  60. Vsync => Vsync,
  61. PS2Clk => PS2Clk,
  62. PS2Data => PS2Data,
  63. btnC => btnC,
  64. CLK => CLK);
  65. CLK_process :process
  66. begin
  67. CLK <= '1';
  68. wait for CLK_period/2;
  69. CLK <= '0';
  70. wait for CLK_period/2;
  71. end process;
  72. process
  73. begin
  74. PS2Clk <= '1' after 3200 us, '0' after 3250 us, '1' after 3300 us, '0' after 3350 us, '1' after 3400 us, '0' after 3450 us, '1' after 3500 us, '0' after 3550 us, '1' after 3600 us, '0' after 3650 us, '1' after 3700 us, '0' after 3750 us, '1' after 3800 us, '0' after 3850 us, '1' after 3900 us, '0' after 3950 us, '1' after 4000 us, '0' after 4050 us, '1' after 4100 us, '0' after 4150 us, '1' after 4200 us, '0' after 4250 us, '1' after 5000 us, '0' after 5050 us, '1' after 5100 us, '0' after 5150 us, '1' after 5200 us, '0' after 5250 us, '1' after 5300 us, '0' after 5350 us, '1' after 5400 us, '0' after 5450 us, '1' after 5500 us, '0' after 5550 us, '1' after 5600 us, '0' after 5650 us, '1' after 5700 us, '0' after 5750 us, '1' after 5800 us, '0' after 5850 us, '1' after 5900 us, '0' after 5950 us, '1' after 6000 us, '0' after 6050 us;
  75. PS2Data <= '0' after 3200 us, '1' after 3300 us, '0' after 3400 us, '1' after 3500 us, '0' after 3600 us, '1' after 3700 us, '1' after 3800 us, '1' after 3900 us, '0' after 4000 us, '0' after 4100 us, '1' after 4200 us, '0' after 4300 us, '0' after 5000 us, '0' after 5100 us, '1' after 5200 us, '0' after 5300 us, '1' after 5400 us, '1' after 5500 us, '0' after 5600 us, '1' after 5700 us, '0' after 5800 us, '1' after 5900 us, '1' after 6000 us, '0' after 6100 us;
  76. wait;
  77. end process;
  78. end Behavioral;