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TestScreenDriver.vhd 2.4KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 09.07.2021 11:39:21
  6. -- Design Name:
  7. -- Module Name: TestScreenDriver - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity TestScreenDriver is
  30. -- Port ( );
  31. end TestScreenDriver;
  32. architecture Behavioral of TestScreenDriver is
  33. component ScreenDriver
  34. Generic ( Nb_bits : Natural
  35. );
  36. Port ( CLK : in STD_LOGIC;
  37. Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  38. ValueAv : in STD_LOGIC;
  39. IsInt : in STD_LOGIC;
  40. OutData : out STD_LOGIC_VECTOR (0 to 6);
  41. OutDataAv : out STD_LOGIC);
  42. end component;
  43. signal CLK : STD_LOGIC := '0';
  44. signal Value : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  45. signal ValueAv : STD_LOGIC := '0';
  46. signal IsInt : STD_LOGIC := '0';
  47. signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
  48. signal OutDataAv : STD_LOGIC := '0';
  49. constant CLK_period : time := 10 ns;
  50. begin
  51. instance : ScreenDriver
  52. Generic map ( Nb_bits => 16)
  53. Port map ( CLK => CLK ,
  54. Value => Value ,
  55. ValueAv => ValueAv ,
  56. IsInt => IsInt ,
  57. OutData => OutData ,
  58. OutDataAv => OutDataAv );
  59. CLK_process : process
  60. begin
  61. CLK <= '1';
  62. wait for CLK_period/2;
  63. CLK <= '0';
  64. wait for CLK_period/2;
  65. end process;
  66. process
  67. begin
  68. Value <= "0000000001010101" after 10 ns, "11111111111111111" after 80 ns;
  69. ValueAv <= '1' after 10 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns;
  70. IsInt <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns;
  71. wait;
  72. end process;
  73. end Behavioral;