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- ----------------------------------------------------------------------------------
- -- Company: INSA-Toulouse
- -- Engineer: Paul Faure
- --
- -- Create Date: 19.04.2021 16:57:41
- -- Module Name: Pipeline_NS - Behavioral
- -- Project Name: Processeur sécurisé
- -- Target Devices: Basys 3 ARTIX7
- -- Tool Versions: Vivado 2016.4
- -- Description: Version non sécurisée du pipeline, connecte les étages et fait avancer les signaux sur le pipeline
- --
- -- Dependencies:
- -- - Etage1_LectureInstruction_NS
- -- - Etage2_5_Registres
- -- - Etage3_Calcul
- -- - Etage4_Memoire_NS
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- entity Pipeline_NS is
- Generic (Nb_bits : Natural := 8; -- Taille d'un mot binaire
- Instruction_En_Memoire_Size : Natural := 29; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
- Addr_Memoire_Instruction_Size : Natural := 3; -- Nombre de bits pour adresser la mémoire d'instruction
- Memoire_Instruction_Size : Natural := 8; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
- Instruction_Bus_Size : Natural := 5; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
- Nb_Instructions : Natural := 32; -- Nombre d'instructions dans le processeur
- Nb_Registres : Natural := 16; -- Nombre de registres du processeurs
- Addr_registres_size : Natural := 4; -- Nombre de bits pour adresser les registres
- Memoire_Size : Natural := 32; -- Taille de la mémoire de données
- Adresse_mem_size : Natural := 5); -- Nombre de bits pour adresser la mémoire
- Port (CLK : STD_LOGIC;
- RST : STD_LOGIC;
- STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- STD_IN_Av : in STD_LOGIC;
- STD_IN_Request : out STD_LOGIC;
- STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- STD_OUT_Av : out STD_LOGIC;
- STD_OUT_Int : out STD_LOGIC);
- end Pipeline_NS;
-
- architecture Behavioral of Pipeline_NS is
-
- component Etage1_LectureInstruction_NS is
- Generic (Instruction_size_in_memory : Natural;
- Addr_size_mem_instruction : Natural;
- Mem_instruction_size : Natural;
- Nb_bits : Natural;
- Instruction_bus_size : Natural;
- Nb_registres : Natural;
- Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
- Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
- Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
- Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
- Code_Instruction_JMP : STD_LOGIC_VECTOR;
- Code_Instruction_JMZ : STD_LOGIC_VECTOR;
- Code_Instruction_PRI : STD_LOGIC_VECTOR;
- Code_Instruction_PRIC : STD_LOGIC_VECTOR;
- Code_Instruction_CALL : STD_LOGIC_VECTOR;
- Code_Instruction_RET : STD_LOGIC_VECTOR;
- Code_Instruction_STOP : STD_LOGIC_VECTOR);
- Port ( CLK : in STD_LOGIC;
- RST : in STD_LOGIC;
- Z : in STD_LOGIC;
- STD_IN_Request : in STD_LOGIC;
- Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
- A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
- end component;
-
- component Etage2_5_Registres is
- Generic ( Nb_bits : Natural;
- Nb_registres : Natural;
- Addr_registres_size : Natural;
- Instruction_bus_size : Natural;
- Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
- Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
- Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
- Code_Instruction_PRI : STD_LOGIC_VECTOR;
- Code_Instruction_PRIC : STD_LOGIC_VECTOR;
- Code_Instruction_GET : STD_LOGIC_VECTOR);
- Port ( CLK : in STD_LOGIC;
- RST : in STD_LOGIC;
- STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur
- STD_IN_Av : in STD_LOGIC;
- STD_IN_Request : out STD_LOGIC;
- STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
- STD_OUT_Av : out STD_LOGIC;
- STD_OUT_Int : out STD_LOGIC;
- IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
- OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
- IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
- end component;
-
- component Etage3_Calcul is
- Generic ( Nb_bits : Natural;
- Instruction_bus_size : Natural;
- Bits_Controle_LC : STD_LOGIC_VECTOR;
- Bits_Controle_MUX : STD_LOGIC_VECTOR);
- Port ( RST : in STD_LOGIC;
- IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
- OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
- N : out STD_LOGIC;
- O : out STD_LOGIC;
- Z : out STD_LOGIC;
- C : out STD_LOGIC);
- end component;
-
- component Etage4_Memoire_NS is
- Generic ( Nb_bits : Natural;
- Mem_size : Natural;
- Adresse_mem_size : Natural;
- Instruction_bus_size : Natural;
- Bits_Controle_LC : STD_LOGIC_VECTOR;
- Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
- Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
- Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
- Code_Instruction_CALL : STD_LOGIC_VECTOR;
- Code_Instruction_RET : STD_LOGIC_VECTOR);
- Port ( CLK : in STD_LOGIC;
- RST : in STD_LOGIC;
- IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
- OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
- OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
- end component;
-
- -- Signaux reliant les étages
- signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
- signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
- -- Sorties de l'ALU
- signal N : STD_LOGIC := '0';
- signal Z : STD_LOGIC := '0';
- signal O : STD_LOGIC := '0';
- signal C : STD_LOGIC := '0';
- -- Sortie de l'adresse de retour de l'étage 4 vers le 1
- signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
-
- signal intern_STD_IN_Request : STD_LOGIC := '0';
-
- -- Constantes de contrôle des MUX et LC
- constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11110011101111111111111";
- constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111000011000000001";
- constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
- constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111111111100000001";
- constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111001011111111111";
- constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111110101111111111";
- constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "10011111011001111111111";
- constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000001010000000000";
- constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
- constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
- constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
- constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
- constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
- constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
- constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
- constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
- constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10110";
-
- -- Constantes de contrôle des bulles
- constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00001100010000000000000";
- constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000111100111111110";
- constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000000000011111110";
- constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
- begin
- instance_Etage1 : Etage1_LectureInstruction_NS
- generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
- Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
- Mem_instruction_size => Memoire_Instruction_Size,
- Nb_bits => Nb_bits,
- Instruction_bus_size => Instruction_Bus_Size,
- Nb_registres => Nb_Registres,
- Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
- Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
- Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
- Instructions_critiques_ecriture => Instructions_critiques_ecriture,
- Code_Instruction_JMP => Code_Instruction_JMP,
- Code_Instruction_JMZ => Code_Instruction_JMZ,
- Code_Instruction_PRI => Code_Instruction_PRI,
- Code_Instruction_PRIC => Code_Instruction_PRIC,
- Code_Instruction_CALL => Code_Instruction_CALL,
- Code_Instruction_RET => Code_Instruction_RET,
- Code_Instruction_STOP => Code_Instruction_STOP
- )
- port map (
- CLK => CLK,
- RST => RST,
- Z => Z,
- STD_IN_Request => intern_STD_IN_Request,
- Addr_Retour => AdresseRetour,
- A => A_from_1,
- B => B_from_1,
- C => C_from_1,
- Instruction => Instruction_from_1
- );
-
- instance_Etage2_5 : Etage2_5_Registres
- generic map( Nb_bits => Nb_bits,
- Nb_Registres => Nb_Registres,
- Addr_registres_size => Addr_registres_size,
- Instruction_bus_size => Instruction_Bus_Size,
- Bits_Controle_LC_5 => Bits_Controle_LC_5,
- Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
- Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
- Code_Instruction_PRI => Code_Instruction_PRI,
- Code_Instruction_PRIC => Code_Instruction_PRIC,
- Code_Instruction_GET => Code_Instruction_GET
- )
- port map( CLK => CLK,
- RST => RST,
- STD_IN => STD_IN,
- STD_IN_Av => STD_IN_Av,
- STD_IN_Request => intern_STD_IN_Request,
- STD_OUT => STD_OUT,
- STD_OUT_Av => STD_OUT_Av,
- STD_OUT_Int => STD_OUT_Int,
- IN_2_A => A_to_2,
- IN_2_B => B_to_2,
- IN_2_C => C_to_2,
- IN_2_Instruction => Instruction_to_2,
- OUT_2_A => A_from_2,
- OUT_2_B => B_from_2,
- OUT_2_C => C_from_2,
- OUT_2_Instruction => Instruction_from_2,
- IN_5_A => A_to_5,
- IN_5_B => B_to_5,
- IN_5_Instruction => Instruction_to_5
- );
-
- instance_Etage3 : Etage3_Calcul
- generic map( Nb_bits => Nb_bits,
- Instruction_bus_size => Instruction_Bus_Size,
- Bits_Controle_LC => Bits_Controle_LC_3,
- Bits_Controle_MUX => Bits_Controle_MUX_3
- )
- port map( RST => RST,
- IN_A => A_to_3,
- IN_B => B_to_3,
- IN_C => C_to_3,
- IN_Instruction => Instruction_to_3,
- OUT_A => A_from_3,
- OUT_B => B_from_3,
- OUT_Instruction => Instruction_from_3,
- N => N,
- O => O,
- Z => Z,
- C => C
- );
-
- instance_Etage4 : Etage4_Memoire_NS
- generic map( Nb_bits => Nb_bits,
- Mem_size => Memoire_Size,
- Adresse_mem_size => Adresse_mem_size,
- Instruction_bus_size => Instruction_Bus_Size,
- Bits_Controle_LC => Bits_Controle_LC_4,
- Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
- Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
- Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT,
- Code_Instruction_CALL => Code_Instruction_CALL,
- Code_Instruction_RET => Code_Instruction_RET
- )
- port map( CLK => CLK,
- RST => RST,
- IN_A => A_to_4,
- IN_B => B_to_4,
- IN_Instruction => Instruction_to_4,
- OUT_A => A_from_4,
- OUT_B => B_from_4,
- OUT_Instruction => Instruction_from_4,
- OUT_AddrRetour => AdresseRetour
- );
-
- STD_IN_Request <= intern_STD_IN_Request;
-
- process
- begin
- wait until CLK'event and CLK = '1';
- if (intern_STD_IN_Request = '0') then
- A_to_2 <= A_from_1;
- B_to_2 <= B_from_1;
- C_to_2 <= C_from_1;
- Instruction_to_2 <= Instruction_from_1;
-
- A_to_3 <= A_from_2;
- B_to_3 <= B_from_2;
- C_to_3 <= C_from_2;
- Instruction_to_3 <= Instruction_from_2;
-
- A_to_4 <= A_from_3;
- B_to_4 <= B_from_3;
- Instruction_to_4 <= Instruction_from_3;
-
- A_to_5 <= A_from_4;
- B_to_5 <= B_from_4;
- Instruction_to_5 <= Instruction_from_4;
- end if;
- end process;
- end Behavioral;
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