235 lines
10 KiB
VHDL
235 lines
10 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: INSA-Toulouse
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-- Engineer: Paul Faure
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--
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-- Create Date: 13.04.2021 10:19:15
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-- Module Name: System - Behavioral
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-- Project Name: Processeur sécurisé
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-- Target Devices: Basys 3 ARTIX7
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-- Tool Versions: Vivado 2016.4
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-- Description: Environnement du processeur, mapping entre le processeur et les periphériques, affectation des ports la carte
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--
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-- Dependencies:
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-- - Clock_Divider
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-- - Pipeline
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-- - Pipeline_NS
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-- - PeripheriqueEcran
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-- - PeripheriqueClavier
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Lien avec le fichier de contraintes
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-- Récupération du VGA
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-- Récupération du PS2
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-- Récupération d'un bouton pour RST
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-- Récupération de la clock
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entity System is
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Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
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vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
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vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
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Hsync : out STD_LOGIC;
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Vsync : out STD_LOGIC;
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PS2Clk : in STD_LOGIC;
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PS2Data : in STD_LOGIC;
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btnC : in STD_LOGIC;
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CLK : STD_LOGIC);
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end System;
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architecture Structural of System is
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component Pipeline is
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Generic (Nb_bits : Natural := 8;
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Instruction_En_Memoire_Size : Natural := 29;
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Addr_Memoire_Instruction_Size : Natural := 3;
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Memoire_Instruction_Size : Natural := 8;
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Instruction_Bus_Size : Natural := 5;
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Nb_Instructions : Natural := 32;
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Nb_Registres : Natural := 16;
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Addr_registres_size : Natural := 4;
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Memoire_Size : Natural := 32;
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Adresse_mem_size : Natural := 5;
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Memoire_Adresses_Retour_Size : Natural := 16;
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Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
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Port (CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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STD_IN_Av : in STD_LOGIC;
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STD_IN_Request : out STD_LOGIC;
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STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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STD_OUT_Av : out STD_LOGIC;
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STD_OUT_Int : out STD_LOGIC);
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end component;
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component Pipeline_NS is
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Generic (Nb_bits : Natural := 8;
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Instruction_En_Memoire_Size : Natural := 29;
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Addr_Memoire_Instruction_Size : Natural := 3;
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Memoire_Instruction_Size : Natural := 8;
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Instruction_Bus_Size : Natural := 5;
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Nb_Instructions : Natural := 32;
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Nb_Registres : Natural := 16;
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Addr_registres_size : Natural := 4;
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Memoire_Size : Natural := 32;
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Adresse_mem_size : Natural := 5);
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Port (CLK : STD_LOGIC;
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RST : STD_LOGIC;
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STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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STD_IN_Av : in STD_LOGIC;
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STD_IN_Request : out STD_LOGIC;
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STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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STD_OUT_Av : out STD_LOGIC;
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STD_OUT_Int : out STD_LOGIC);
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end component;
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component PeripheriqueEcran
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Generic ( Nb_Bits : Natural);
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Port ( CLK : in STD_LOGIC;
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CLK_VGA : in STD_LOGIC;
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RST : in STD_LOGIC;
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vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
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vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
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vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
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Hsync : out STD_LOGIC;
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Vsync : out STD_LOGIC;
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STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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STD_OUT_Av : in STD_LOGIC;
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STD_OUT_Int : in STD_LOGIC);
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end component;
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component PeripheriqueClavier
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Generic (Nb_Bits : Natural);
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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PS2Clk : in STD_LOGIC;
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PS2Data : in STD_LOGIC;
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STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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STD_IN_Av : out STD_LOGIC;
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STD_IN_Request : in STD_LOGIC;
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STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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STD_OUT_Av : out STD_LOGIC);
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end component;
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component Clock_Divider is
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Port ( CLK_IN : in STD_LOGIC;
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CLK_OUT : out STD_LOGIC);
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end component;
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-- signaux auxiliaires
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signal my_RST : STD_LOGIC; -- Signal de RST (inversion par rapport au btnC)
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signal my_CLK : STD_LOGIC; -- Signal de clock (divisée par rapport CLK)
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-- signaux de gestion de l'entrée
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signal STD_IN : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Entrée
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signal STD_IN_Av : STD_LOGIC := '0'; -- Entrée disponible en lecture sur le clavier
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signal STD_IN_Request : STD_LOGIC := '0'; -- Demande d'une entrée au clavier
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-- signaux de gestion de la sortie
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signal STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie vers l'écran
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signal STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible pour l'écran
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signal STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) pour l'écran
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signal pipeline_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie depuis le Pipeline
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signal pipeline_STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible depuis le Pipeline
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signal pipeline_STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) depuis le pipeline
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signal clavier_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie depuis le Clavier
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signal clavier_STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible depuis le Clavier
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signal clavier_STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) depuis le Clavier
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constant SECURISED : boolean := false; -- Booléen de sélection entre la version sécurisée et non sécurisée
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begin
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-- Diviseur de clock
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clk_div : Clock_Divider
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port map (CLK_IN => CLK,
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CLK_OUT => my_CLK);
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-- Generation du pipeline en fonction de la condition sécurisé ou non
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instance: if (SECURISED) generate
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instance_securisee : entity work.Pipeline
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generic map (Nb_bits => 16,
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Instruction_En_Memoire_Size => 53,
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Addr_Memoire_Instruction_Size => 9,
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Memoire_Instruction_Size => 512,
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Instruction_Bus_Size => 5,
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Nb_Instructions => 32,
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Nb_Registres => 16,
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Addr_registres_size => 4,
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Memoire_Size => 64,
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Adresse_mem_size => 6,
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Memoire_Adresses_Retour_Size => 4,
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Adresse_Memoire_Adresses_Retour_Size => 2)
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port map (CLK => my_CLK,
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RST => my_RST,
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STD_IN => STD_IN,
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STD_IN_Av => STD_IN_Av,
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STD_IN_Request => STD_IN_Request,
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STD_OUT => pipeline_STD_OUT,
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STD_OUT_Av => pipeline_STD_OUT_Av,
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STD_OUT_Int => pipeline_STD_OUT_Int);
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else generate
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instance_non_securisee : entity work.Pipeline_NS
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generic map (Nb_bits => 16,
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Instruction_En_Memoire_Size => 53,
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Addr_Memoire_Instruction_Size => 9,
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Memoire_Instruction_Size => 512,
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Instruction_Bus_Size => 5,
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Nb_Instructions => 32,
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Nb_Registres => 16,
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Addr_registres_size => 4,
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Memoire_Size => 64,
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Adresse_mem_size => 6)
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port map (CLK => my_CLK,
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RST => my_RST,
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STD_IN => STD_IN,
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STD_IN_Av => STD_IN_Av,
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STD_IN_Request => STD_IN_Request,
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STD_OUT => pipeline_STD_OUT,
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STD_OUT_Av => pipeline_STD_OUT_Av,
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STD_OUT_Int => pipeline_STD_OUT_Int);
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end generate;
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instance_perif_ecran : PeripheriqueEcran
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generic map ( Nb_Bits => 16)
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port map ( CLK => my_CLK,
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CLK_VGA => CLK,
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RST => my_RST,
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vgaRed => vgaRed,
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vgaBlue => vgaBlue,
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vgaGreen => vgaGreen,
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Hsync => Hsync,
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Vsync => Vsync,
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STD_OUT => STD_OUT,
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STD_OUT_Av => STD_OUT_Av,
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STD_OUT_Int => STD_OUT_Int);
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instance_perif_clavier : PeripheriqueClavier
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generic map (Nb_Bits => 16)
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port map ( CLK => my_CLK,
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RST => my_RST,
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PS2Clk => PS2Clk,
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PS2Data => PS2Data,
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STD_IN => STD_IN,
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STD_IN_Av => STD_IN_Av,
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STD_IN_Request => STD_IN_Request,
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STD_OUT => clavier_STD_OUT,
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STD_OUT_Av => clavier_STD_OUT_Av);
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-- Gestion du RST (inversion d'état)
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my_RST <= '1' when btnC = '0' else
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'0';
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-- Gestion de l'affichage sur l'écran lors d'une demande d'entrée le clavier affiche sur l'écran
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STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT;
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STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av;
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STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int;
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end Structural;
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