48 lines
No EOL
1.9 KiB
VHDL
48 lines
No EOL
1.9 KiB
VHDL
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-- Company: INSA-Toulouse
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-- Engineer: Paul Faure
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--
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-- Create Date: 16.04.2021 14:35:04
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-- Module Name: MemoireDonnees - Behavioral
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-- Project Name: Processeur sécurisé
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-- Target Devices: Basys 3 ARTIX7
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-- Tool Versions: Vivado 2016.4
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-- Description: Memoire des donnees utilisateur
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--
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-- Dependencies: None
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity MemoireDonnees is
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Generic (Nb_bits : Natural; -- Taille d'un mot en mémoire
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Addr_size : Natural; -- Nombre de bits nécessaires a l'adressage de la mémoire
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Mem_size : Natural); -- Nombre de mot stockables
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Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
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RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
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D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
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RST : in STD_LOGIC; -- Reset
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CLK : in STD_LOGIC; -- Clock
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D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
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end MemoireDonnees;
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architecture Behavioral of MemoireDonnees is
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signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0'); -- Buffer pour la mémoire
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begin
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process
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begin
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wait until CLK'event and CLK = '1';
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if (RST = '0') then
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MEMORY <= (others => '0');
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else
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if (RW = '0') then
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MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
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end if;
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end if;
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end process;
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-- Lecture assynchrone et en permanence
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D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
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end Behavioral; |