85 lines
2.4 KiB
VHDL
85 lines
2.4 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19.04.2021 17:35:57
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-- Design Name:
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-- Module Name: Test_Pipeline - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_Pipeline is
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-- Port ( );
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end Test_Pipeline;
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architecture Behavioral of Test_Pipeline is
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component Pipeline is
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Generic (Nb_bits : Natural := 8;
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Instruction_En_Memoire_Size : Natural := 29;
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Addr_Memoire_Instruction_Size : Natural := 3;
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Memoire_Instruction_Size : Natural := 8;
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Instruction_Bus_Size : Natural := 5;
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Nb_Instructions : Natural := 32;
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Nb_Registres : Natural := 16;
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Memoire_Size : Natural := 32;
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Memoire_Adresses_Retour_Size : Natural := 16;
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Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
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Port (CLK : STD_LOGIC;
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RST : STD_LOGIC;
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STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
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end component;
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signal my_CLK : STD_LOGIC := '0';
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signal my_RST : STD_LOGIC := '1';
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signal my_STD_IN : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
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signal my_STD_OUT : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
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constant CLK_period : time := 10 ns;
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begin
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instance : Pipeline
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generic map (Addr_Memoire_Instruction_Size => 8,
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Memoire_Instruction_Size => 256)
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port map (CLK => my_CLK,
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RST => my_RST,
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STD_IN => my_STD_IN,
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STD_OUT => my_STD_OUT);
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CLK_process :process
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begin
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my_CLK <= '1';
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wait for CLK_period/2;
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my_CLK <= '0';
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wait for CLK_period/2;
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end process;
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process
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begin
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wait;
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end process;
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end Behavioral;
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