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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 09.04.2021 22:03:10
- -- Design Name:
- -- Module Name: System - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity System is
- Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
- btnL : in STD_LOGIC;
- btnC : in STD_LOGIC;
- btnR : in STD_LOGIC;
- btnD : in STD_LOGIC;
- LED : out STD_LOGIC_VECTOR (0 to 7);
- CLK : in STD_LOGIC);
- end System;
-
- architecture Structural of System is
-
- component ClockDivider1000
- Port ( clk_in : in STD_LOGIC;
- clk_out : out STD_LOGIC);
- end component;
-
- component Compteur
- Port ( CK : in STD_LOGIC;
- RST : in STD_LOGIC;
- SENS : in STD_LOGIC;
- LOAD : in STD_LOGIC;
- EN : in STD_LOGIC;
- Din : in STD_LOGIC_VECTOR (7 downto 0);
- Dout : out STD_LOGIC_VECTOR (7 downto 0));
- end component;
-
- signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
- begin
- DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
- DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
- CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
- end Structural;
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