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Compteur.vhd 1.6KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 09.04.2021 21:20:39
  6. -- Design Name:
  7. -- Module Name: Compteur - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. -- use IEEE.NUMERIC_STD.ALL;
  26. -- Uncomment the following library declaration if instantiating
  27. -- any Xilinx leaf cells in this code.
  28. --library UNISIM;
  29. --use UNISIM.VComponents.all;
  30. entity Compteur is
  31. Port ( CK : in STD_LOGIC;
  32. RST : in STD_LOGIC;
  33. SENS : in STD_LOGIC;
  34. LOAD : in STD_LOGIC;
  35. EN : in STD_LOGIC;
  36. Din : in STD_LOGIC_VECTOR (7 downto 0);
  37. Dout : out STD_LOGIC_VECTOR (7 downto 0));
  38. end Compteur;
  39. architecture Behavioral of Compteur is
  40. signal aux: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
  41. begin
  42. Dout <= aux;
  43. process
  44. begin
  45. wait until CK'event and CK='1';
  46. if RST = '0' then
  47. aux <= (others => '0');
  48. elsif LOAD = '1' then
  49. aux <= Din;
  50. elsif EN = '0' then
  51. if SENS = '1' then
  52. aux <= aux + 1;
  53. else
  54. aux <= aux - 1;
  55. end if;
  56. end if;
  57. end process;
  58. end Behavioral;