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ClockDivider1000.vhd 1.3KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 09.04.2021 21:44:36
  6. -- Design Name:
  7. -- Module Name: ClockDivider1000 - Structural
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity ClockDivider1000 is
  30. Port ( clk_in : in STD_LOGIC;
  31. clk_out : out STD_LOGIC);
  32. end ClockDivider1000;
  33. architecture Structural of ClockDivider1000 is
  34. component ClockDivider10
  35. Port ( clk_in : in STD_LOGIC;
  36. clk_out : out STD_LOGIC);
  37. end component;
  38. signal aux1, aux2 : STD_LOGIC;
  39. begin
  40. U1: ClockDivider10 port map(clk_in, aux1);
  41. U2: ClockDivider10 port map(aux1, aux2);
  42. U3: ClockDivider10 port map(aux2, clk_out);
  43. end Structural;