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ClockDivider10.vhd 1.3KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 09.04.2021 21:42:26
  6. -- Design Name:
  7. -- Module Name: ClockDivider10 - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity ClockDivider10 is
  30. Port ( clk_in : in STD_LOGIC;
  31. clk_out : out STD_LOGIC);
  32. end ClockDivider10;
  33. architecture Behavioral of ClockDivider10 is
  34. subtype int10 is INTEGER range 0 to 10;
  35. signal N : int10 := 0;
  36. signal aux : STD_LOGIC;
  37. begin
  38. process
  39. begin
  40. wait until clk_in'event and clk_in = '1';
  41. N <= N + 1;
  42. if N = 10 then
  43. aux <= not aux;
  44. N <= 0;
  45. end if;
  46. end process;
  47. clk_out <= aux;
  48. end Behavioral;