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test_Compteur.vhd 1.3KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 09.04.2021 22:51:31
  6. -- Design Name:
  7. -- Module Name: test_Compteur - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity test_Compteur is
  30. -- Port ( );
  31. end test_Compteur;
  32. architecture Behavioral of test_Compteur is
  33. component Compteur is
  34. Port ( CK : in STD_LOGIC;
  35. RST : in STD_LOGIC;
  36. SENS : in STD_LOGIC;
  37. LOAD : in STD_LOGIC;
  38. EN : in STD_LOGIC;
  39. Din : in STD_LOGIC_VECTOR (7 downto 0);
  40. Dout : out STD_LOGIC_VECTOR (7 downto 0));
  41. end component;
  42. signal CK
  43. begin
  44. end Behavioral;