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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 09.04.2021 22:51:31
- -- Design Name:
- -- Module Name: test_Compteur - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity test_Compteur is
- -- Port ( );
- end test_Compteur;
-
- architecture Behavioral of test_Compteur is
- component Compteur is
- Port ( CK : in STD_LOGIC;
- RST : in STD_LOGIC;
- SENS : in STD_LOGIC;
- LOAD : in STD_LOGIC;
- EN : in STD_LOGIC;
- Din : in STD_LOGIC_VECTOR (7 downto 0);
- Dout : out STD_LOGIC_VECTOR (7 downto 0));
- end component;
-
- signal CK
- begin
-
-
- end Behavioral;
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