51 rader
1,3 KiB
VHDL
51 rader
1,3 KiB
VHDL
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-- Company: INSA-Toulouse
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-- Engineer: Paul Faure
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--
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-- Create Date: 08.05.2021 21:00:25
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-- Module Name: Clock_Divider - Behavioral
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-- Project Name: Processeur sécurisé
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-- Target Devices: Basys 3 ARTIX7
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-- Tool Versions: Vivado 2016.4
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-- Description: Diviseur de clock (rapport de 1000)
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--
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-- Dependencies: None
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Clock_Divider is
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Port ( CLK_IN : in STD_LOGIC;
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CLK_OUT : out STD_LOGIC);
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end Clock_Divider;
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architecture Behavioral of Clock_Divider is
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-- Compteur pour le diviseur
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signal N : Integer := 0;
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-- Signal enregistrant l'ancienne valeur de CLK
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signal CLK : STD_LOGIC := '1';
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begin
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process
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begin
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-- Synchronisation
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wait until CLK_IN'event and CLK_IN = '1';
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-- Incrementation du compteur
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N <= N + 1;
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if (N = 1000) then
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-- Remise a 0 et changement d'état de la CLK
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N <= 0;
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if (CLK = '1') then
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CLK <= '0';
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else
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CLK <= '1';
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end if;
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end if;
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end process;
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-- Sortie du signal (assynchrone -> imédiat)
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CLK_OUT <= CLK;
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end Behavioral;
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