123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988 |
- #-----------------------------------------------------------
- # Vivado v2016.4 (64-bit)
- # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
- # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
- # Start of session at: Mon May 10 16:43:40 2021
- # Process ID: 13872
- # Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
- # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1028 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
- # Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
- # Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
- #-----------------------------------------------------------
- start_gui
- open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr
- CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg'.
- CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg'.
- Scanning sources...
- Finished scanning sources
- INFO: [IP_Flow 19-234] Refreshing IP repositories
- INFO: [IP_Flow 19-1704] No user IP repositories specified
- INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
- open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 839.340 ; gain = 198.637
- launch_simulation
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
- INFO: [USF-XSim-3] XSim::Elaborate design
- INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- Vivado Simulator 2016.4
- Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.std_logic_arith
- Compiling package ieee.std_logic_unsigned
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
- Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
- Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
- Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
- Built simulation snapshot Test_Pipeline_behav
-
- ****** Webtalk v2016.4 (64-bit)
- **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
- **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
- ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-
- source C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
- INFO: [Common 17-206] Exiting Webtalk at Mon May 10 17:15:25 2021...
- INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
- INFO: [USF-XSim-4] XSim::Simulate design
- WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
- WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
- WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
- WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
- INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- INFO: [USF-XSim-98] *** Running xsim
- with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
- INFO: [USF-XSim-8] Loading simulator feature
- Vivado Simulator 2016.4
- Time resolution is 1 ps
- source Test_Pipeline.tcl
- # set curr_wave [current_wave_config]
- # if { [string length $curr_wave] == 0 } {
- # if { [llength [get_objects]] > 0} {
- # add_wave /
- # set_property needs_save false [current_wave_config]
- # } else {
- # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
- # }
- # }
- # run 1000ns
- ERROR: Index 191 out of bound 127 downto 0
- Time: 10 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/line__68
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd:68
- INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
- INFO: [USF-XSim-97] XSim simulation ran for 1000ns
- launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 872.664 ; gain = 3.988
- relaunch_sim
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
- INFO: [USF-XSim-3] XSim::Elaborate design
- INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- Vivado Simulator 2016.4
- Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.std_logic_arith
- Compiling package ieee.std_logic_unsigned
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
- Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
- Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
- Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
- Built simulation snapshot Test_Pipeline_behav
- INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
- Vivado Simulator 2016.4
- Time resolution is 1 ps
- ERROR: Array sizes do not match, left array has 5 elements, right array has 8 elements
- Time: 0 ps Iteration: 0 Process: /Test_Pipeline/instance/instance_Etage4/line__190
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd:190
- relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 884.223 ; gain = 0.000
- relaunch_sim
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
- INFO: [USF-XSim-3] XSim::Elaborate design
- INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- Vivado Simulator 2016.4
- Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.std_logic_arith
- Compiling package ieee.std_logic_unsigned
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
- Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
- Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
- Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
- Built simulation snapshot Test_Pipeline_behav
- INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
- Vivado Simulator 2016.4
- Time resolution is 1 ps
- ERROR: Index 185 out of bound 95 downto 0
- Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
- relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 886.633 ; gain = 0.000
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 10 us
- ERROR: Index 185 out of bound 95 downto 0
- Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 10 us
- ERROR: Index 185 out of bound 95 downto 0
- Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 10 us
- ERROR: Index 185 out of bound 95 downto 0
- Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 10 us
- ERROR: Index 185 out of bound 95 downto 0
- Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
- relaunch_sim
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
- INFO: [USF-XSim-3] XSim::Elaborate design
- INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- Vivado Simulator 2016.4
- Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.std_logic_arith
- Compiling package ieee.std_logic_unsigned
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
- Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
- Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
- Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
- Built simulation snapshot Test_Pipeline_behav
- INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
- Vivado Simulator 2016.4
- Time resolution is 1 ps
- ERROR: Index 185 out of bound 95 downto 0
- Time: 520 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
-
- HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
- relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
- relaunch_sim
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- ERROR: [VRFC 10-1412] syntax error near begin [C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd:44]
- INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd ignored due to errors
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
- INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log'
- ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
- ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
- ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
- ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
-
- relaunch_sim
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
- INFO: [USF-XSim-3] XSim::Elaborate design
- INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- Vivado Simulator 2016.4
- Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.std_logic_arith
- Compiling package ieee.std_logic_unsigned
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
- Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
- Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
- Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
- Built simulation snapshot Test_Pipeline_behav
- INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
- Vivado Simulator 2016.4
- Time resolution is 1 ps
- relaunch_sim
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
- INFO: [USF-XSim-3] XSim::Elaborate design
- INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- Vivado Simulator 2016.4
- Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.std_logic_arith
- Compiling package ieee.std_logic_unsigned
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
- Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
- Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
- Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
- Built simulation snapshot Test_Pipeline_behav
- INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
- Vivado Simulator 2016.4
- Time resolution is 1 ps
- relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 100 us
- reset_run synth_1
- WARNING: [Vivado 12-1017] Problems encountered:
- 1. Failed to delete one or more files in run directory C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1
-
- launch_runs synth_1 -jobs 2
- [Mon May 10 18:17:42 2021] Launched synth_1...
- Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1/runme.log
- launch_runs impl_1 -jobs 2
- [Mon May 10 18:20:21 2021] Launched impl_1...
- Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
- launch_runs impl_1 -to_step write_bitstream -jobs 2
- [Mon May 10 18:21:46 2021] Launched impl_1...
- Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
- open_hw
- connect_hw_server
- INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
- INFO: [Labtools 27-2222] Launching hw_server...
- INFO: [Labtools 27-2221] Launch Output:
-
- ****** Xilinx hw_server v2016.4
- **** Build date : Jan 23 2017-19:37:29
- ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-
-
- open_hw_target
- INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
- set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
- current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
- refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
- INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
- WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
- Resolution:
- 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
- 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
- set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
- set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
- program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
- INFO: [Labtools 27-3164] End of startup status: HIGH
- refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
- INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
- WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
- Resolution:
- 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
- 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
- WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
- WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
- WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
- WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 100 us
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 100 us
- save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
- ERROR: [Wavedata 42-440] There is no current wave configuration open to save
- save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
- ERROR: [Wavedata 42-440] There is no current wave configuration open to save
- save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
- ERROR: [Wavedata 42-440] There is no current wave configuration open to save
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 100 us
- save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
- ERROR: [Wavedata 42-440] There is no current wave configuration open to save
- restart
- INFO: [Simtcl 6-17] Simulation restarted
- run 100 us
- save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
- ERROR: [Wavedata 42-440] There is no current wave configuration open to save
- save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
- ERROR: [Wavedata 42-440] There is no current wave configuration open to save
- save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
- ERROR: [Wavedata 42-440] There is no current wave configuration open to save
- ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA.
- Check cable connectivity and that the target board is powered up then
- use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
- ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
- close_hw
- relaunch_sim
- INFO: [SIM-utils-51] Simulation object is 'sim_1'
- INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
- INFO: [USF-XSim-97] Finding global include files...
- INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
- INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
- INFO: [USF-XSim-2] XSim::Compile design
- INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity ALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity System
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity BancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Pipeline
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Clock_Divider
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestBancRegistres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestALU
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_LC
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_MUX
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
- INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
- INFO: [VRFC 10-307] analyzing entity Test_Pipeline
- INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
- INFO: [USF-XSim-3] XSim::Elaborate design
- INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
- Vivado Simulator 2016.4
- Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.std_logic_arith
- Compiling package ieee.std_logic_unsigned
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
- Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
- Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
- Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
- Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
- Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
- Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
- Built simulation snapshot Test_Pipeline_behav
- INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
- Vivado Simulator 2016.4
- Time resolution is 1 ps
|