No Description
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

vivado.log 84KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988
  1. #-----------------------------------------------------------
  2. # Vivado v2016.4 (64-bit)
  3. # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
  4. # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
  5. # Start of session at: Mon May 10 16:43:40 2021
  6. # Process ID: 13872
  7. # Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1028 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
  9. # Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
  10. # Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
  11. #-----------------------------------------------------------
  12. start_gui
  13. open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr
  14. CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg'.
  15. CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg'.
  16. Scanning sources...
  17. Finished scanning sources
  18. INFO: [IP_Flow 19-234] Refreshing IP repositories
  19. INFO: [IP_Flow 19-1704] No user IP repositories specified
  20. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
  21. open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 839.340 ; gain = 198.637
  22. launch_simulation
  23. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  24. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  25. INFO: [USF-XSim-97] Finding global include files...
  26. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  27. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  28. INFO: [USF-XSim-2] XSim::Compile design
  29. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  30. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  31. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  32. INFO: [VRFC 10-307] analyzing entity ALU
  33. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  34. INFO: [VRFC 10-307] analyzing entity System
  35. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  36. INFO: [VRFC 10-307] analyzing entity BancRegistres
  37. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  38. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  39. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  40. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  41. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  42. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  43. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  44. INFO: [VRFC 10-307] analyzing entity MUX
  45. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  46. INFO: [VRFC 10-307] analyzing entity LC
  47. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  48. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  49. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  50. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  51. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  52. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  53. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  54. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  55. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  56. INFO: [VRFC 10-307] analyzing entity Pipeline
  57. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  58. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  59. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  60. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  61. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  62. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  63. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  64. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  65. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  66. INFO: [VRFC 10-307] analyzing entity TestALU
  67. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  68. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  69. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  70. INFO: [VRFC 10-307] analyzing entity Test_LC
  71. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  72. INFO: [VRFC 10-307] analyzing entity Test_MUX
  73. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  74. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  75. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  76. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  77. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  78. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  79. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  80. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  81. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  82. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  83. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
  84. INFO: [USF-XSim-3] XSim::Elaborate design
  85. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  86. Vivado Simulator 2016.4
  87. Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
  88. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
  89. Using 2 slave threads.
  90. Starting static elaboration
  91. Completed static elaboration
  92. Starting simulation data flow analysis
  93. Completed simulation data flow analysis
  94. Time Resolution for simulation is 1ps
  95. Compiling package std.standard
  96. Compiling package std.textio
  97. Compiling package ieee.std_logic_1164
  98. Compiling package ieee.std_logic_arith
  99. Compiling package ieee.std_logic_unsigned
  100. Compiling package ieee.numeric_std
  101. Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
  102. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
  103. Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
  104. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  105. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  106. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  107. Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
  108. Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
  109. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  110. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  111. Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
  112. Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
  113. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  114. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  115. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  116. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  117. Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
  118. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
  119. Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
  120. Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
  121. Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
  122. Built simulation snapshot Test_Pipeline_behav
  123. ****** Webtalk v2016.4 (64-bit)
  124. **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
  125. **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
  126. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  127. source C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
  128. INFO: [Common 17-206] Exiting Webtalk at Mon May 10 17:15:25 2021...
  129. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
  130. INFO: [USF-XSim-4] XSim::Simulate design
  131. WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
  132. WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
  133. WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
  134. WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
  135. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  136. INFO: [USF-XSim-98] *** Running xsim
  137. with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
  138. INFO: [USF-XSim-8] Loading simulator feature
  139. Vivado Simulator 2016.4
  140. Time resolution is 1 ps
  141. source Test_Pipeline.tcl
  142. # set curr_wave [current_wave_config]
  143. # if { [string length $curr_wave] == 0 } {
  144. # if { [llength [get_objects]] > 0} {
  145. # add_wave /
  146. # set_property needs_save false [current_wave_config]
  147. # } else {
  148. # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
  149. # }
  150. # }
  151. # run 1000ns
  152. ERROR: Index 191 out of bound 127 downto 0
  153. Time: 10 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/line__68
  154. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd
  155. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd:68
  156. INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
  157. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
  158. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 872.664 ; gain = 3.988
  159. relaunch_sim
  160. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  161. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  162. INFO: [USF-XSim-97] Finding global include files...
  163. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  164. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  165. INFO: [USF-XSim-2] XSim::Compile design
  166. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  167. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  168. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  169. INFO: [VRFC 10-307] analyzing entity ALU
  170. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  171. INFO: [VRFC 10-307] analyzing entity System
  172. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  173. INFO: [VRFC 10-307] analyzing entity BancRegistres
  174. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  175. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  176. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  177. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  178. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  179. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  180. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  181. INFO: [VRFC 10-307] analyzing entity MUX
  182. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  183. INFO: [VRFC 10-307] analyzing entity LC
  184. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  185. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  186. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  187. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  188. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  189. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  190. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  191. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  192. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  193. INFO: [VRFC 10-307] analyzing entity Pipeline
  194. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  195. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  196. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  197. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  198. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  199. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  200. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  201. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  202. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  203. INFO: [VRFC 10-307] analyzing entity TestALU
  204. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  205. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  206. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  207. INFO: [VRFC 10-307] analyzing entity Test_LC
  208. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  209. INFO: [VRFC 10-307] analyzing entity Test_MUX
  210. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  211. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  212. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  213. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  214. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  215. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  216. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  217. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  218. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  219. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  220. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
  221. INFO: [USF-XSim-3] XSim::Elaborate design
  222. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  223. Vivado Simulator 2016.4
  224. Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
  225. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
  226. Using 2 slave threads.
  227. Starting static elaboration
  228. Completed static elaboration
  229. Starting simulation data flow analysis
  230. Completed simulation data flow analysis
  231. Time Resolution for simulation is 1ps
  232. Compiling package std.standard
  233. Compiling package std.textio
  234. Compiling package ieee.std_logic_1164
  235. Compiling package ieee.std_logic_arith
  236. Compiling package ieee.std_logic_unsigned
  237. Compiling package ieee.numeric_std
  238. Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
  239. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
  240. Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
  241. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  242. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  243. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  244. Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
  245. Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
  246. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  247. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  248. Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
  249. Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
  250. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  251. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  252. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  253. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  254. Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
  255. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
  256. Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
  257. Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
  258. Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
  259. Built simulation snapshot Test_Pipeline_behav
  260. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
  261. Vivado Simulator 2016.4
  262. Time resolution is 1 ps
  263. ERROR: Array sizes do not match, left array has 5 elements, right array has 8 elements
  264. Time: 0 ps Iteration: 0 Process: /Test_Pipeline/instance/instance_Etage4/line__190
  265. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
  266. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd:190
  267. relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 884.223 ; gain = 0.000
  268. relaunch_sim
  269. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  270. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  271. INFO: [USF-XSim-97] Finding global include files...
  272. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  273. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  274. INFO: [USF-XSim-2] XSim::Compile design
  275. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  276. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  277. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  278. INFO: [VRFC 10-307] analyzing entity ALU
  279. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  280. INFO: [VRFC 10-307] analyzing entity System
  281. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  282. INFO: [VRFC 10-307] analyzing entity BancRegistres
  283. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  284. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  285. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  286. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  287. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  288. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  289. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  290. INFO: [VRFC 10-307] analyzing entity MUX
  291. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  292. INFO: [VRFC 10-307] analyzing entity LC
  293. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  294. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  295. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  296. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  297. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  298. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  299. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  300. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  301. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  302. INFO: [VRFC 10-307] analyzing entity Pipeline
  303. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  304. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  305. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  306. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  307. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  308. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  309. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  310. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  311. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  312. INFO: [VRFC 10-307] analyzing entity TestALU
  313. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  314. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  315. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  316. INFO: [VRFC 10-307] analyzing entity Test_LC
  317. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  318. INFO: [VRFC 10-307] analyzing entity Test_MUX
  319. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  320. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  321. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  322. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  323. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  324. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  325. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  326. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  327. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  328. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  329. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
  330. INFO: [USF-XSim-3] XSim::Elaborate design
  331. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  332. Vivado Simulator 2016.4
  333. Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
  334. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
  335. Using 2 slave threads.
  336. Starting static elaboration
  337. Completed static elaboration
  338. Starting simulation data flow analysis
  339. Completed simulation data flow analysis
  340. Time Resolution for simulation is 1ps
  341. Compiling package std.standard
  342. Compiling package std.textio
  343. Compiling package ieee.std_logic_1164
  344. Compiling package ieee.std_logic_arith
  345. Compiling package ieee.std_logic_unsigned
  346. Compiling package ieee.numeric_std
  347. Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
  348. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
  349. Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
  350. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  351. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  352. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  353. Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
  354. Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
  355. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  356. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  357. Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
  358. Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
  359. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  360. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  361. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  362. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  363. Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
  364. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
  365. Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
  366. Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
  367. Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
  368. Built simulation snapshot Test_Pipeline_behav
  369. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
  370. Vivado Simulator 2016.4
  371. Time resolution is 1 ps
  372. ERROR: Index 185 out of bound 95 downto 0
  373. Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
  374. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
  375. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
  376. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 886.633 ; gain = 0.000
  377. restart
  378. INFO: [Simtcl 6-17] Simulation restarted
  379. run 10 us
  380. ERROR: Index 185 out of bound 95 downto 0
  381. Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
  382. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
  383. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
  384. restart
  385. INFO: [Simtcl 6-17] Simulation restarted
  386. run 10 us
  387. ERROR: Index 185 out of bound 95 downto 0
  388. Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
  389. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
  390. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
  391. restart
  392. INFO: [Simtcl 6-17] Simulation restarted
  393. run 10 us
  394. ERROR: Index 185 out of bound 95 downto 0
  395. Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
  396. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
  397. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
  398. restart
  399. INFO: [Simtcl 6-17] Simulation restarted
  400. run 10 us
  401. ERROR: Index 185 out of bound 95 downto 0
  402. Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
  403. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
  404. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
  405. relaunch_sim
  406. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  407. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  408. INFO: [USF-XSim-97] Finding global include files...
  409. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  410. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  411. INFO: [USF-XSim-2] XSim::Compile design
  412. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  413. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  414. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  415. INFO: [VRFC 10-307] analyzing entity ALU
  416. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  417. INFO: [VRFC 10-307] analyzing entity System
  418. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  419. INFO: [VRFC 10-307] analyzing entity BancRegistres
  420. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  421. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  422. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  423. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  424. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  425. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  426. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  427. INFO: [VRFC 10-307] analyzing entity MUX
  428. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  429. INFO: [VRFC 10-307] analyzing entity LC
  430. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  431. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  432. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  433. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  434. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  435. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  436. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  437. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  438. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  439. INFO: [VRFC 10-307] analyzing entity Pipeline
  440. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  441. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  442. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  443. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  444. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  445. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  446. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  447. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  448. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  449. INFO: [VRFC 10-307] analyzing entity TestALU
  450. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  451. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  452. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  453. INFO: [VRFC 10-307] analyzing entity Test_LC
  454. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  455. INFO: [VRFC 10-307] analyzing entity Test_MUX
  456. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  457. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  458. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  459. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  460. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  461. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  462. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  463. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  464. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  465. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  466. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
  467. INFO: [USF-XSim-3] XSim::Elaborate design
  468. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  469. Vivado Simulator 2016.4
  470. Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
  471. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
  472. Using 2 slave threads.
  473. Starting static elaboration
  474. Completed static elaboration
  475. Starting simulation data flow analysis
  476. Completed simulation data flow analysis
  477. Time Resolution for simulation is 1ps
  478. Compiling package std.standard
  479. Compiling package std.textio
  480. Compiling package ieee.std_logic_1164
  481. Compiling package ieee.std_logic_arith
  482. Compiling package ieee.std_logic_unsigned
  483. Compiling package ieee.numeric_std
  484. Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
  485. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
  486. Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
  487. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  488. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  489. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  490. Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
  491. Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
  492. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  493. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  494. Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
  495. Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
  496. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  497. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  498. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  499. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  500. Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
  501. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
  502. Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
  503. Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
  504. Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
  505. Built simulation snapshot Test_Pipeline_behav
  506. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
  507. Vivado Simulator 2016.4
  508. Time resolution is 1 ps
  509. ERROR: Index 185 out of bound 95 downto 0
  510. Time: 520 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
  511. File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
  512. HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
  513. relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
  514. relaunch_sim
  515. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  516. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  517. INFO: [USF-XSim-97] Finding global include files...
  518. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  519. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  520. INFO: [USF-XSim-2] XSim::Compile design
  521. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  522. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  523. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  524. INFO: [VRFC 10-307] analyzing entity ALU
  525. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  526. INFO: [VRFC 10-307] analyzing entity System
  527. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  528. INFO: [VRFC 10-307] analyzing entity BancRegistres
  529. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  530. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  531. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  532. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  533. ERROR: [VRFC 10-1412] syntax error near begin [C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd:44]
  534. INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd ignored due to errors
  535. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  536. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  537. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  538. INFO: [VRFC 10-307] analyzing entity MUX
  539. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  540. INFO: [VRFC 10-307] analyzing entity LC
  541. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  542. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  543. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  544. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  545. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  546. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  547. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  548. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  549. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  550. INFO: [VRFC 10-307] analyzing entity Pipeline
  551. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  552. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  553. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  554. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  555. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  556. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  557. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  558. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  559. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  560. INFO: [VRFC 10-307] analyzing entity TestALU
  561. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  562. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  563. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  564. INFO: [VRFC 10-307] analyzing entity Test_LC
  565. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  566. INFO: [VRFC 10-307] analyzing entity Test_MUX
  567. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  568. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  569. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  570. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  571. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  572. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  573. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  574. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  575. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  576. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  577. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
  578. INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log'
  579. ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
  580. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
  581. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
  582. ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
  583. relaunch_sim
  584. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  585. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  586. INFO: [USF-XSim-97] Finding global include files...
  587. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  588. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  589. INFO: [USF-XSim-2] XSim::Compile design
  590. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  591. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  592. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  593. INFO: [VRFC 10-307] analyzing entity ALU
  594. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  595. INFO: [VRFC 10-307] analyzing entity System
  596. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  597. INFO: [VRFC 10-307] analyzing entity BancRegistres
  598. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  599. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  600. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  601. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  602. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  603. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  604. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  605. INFO: [VRFC 10-307] analyzing entity MUX
  606. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  607. INFO: [VRFC 10-307] analyzing entity LC
  608. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  609. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  610. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  611. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  612. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  613. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  614. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  615. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  616. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  617. INFO: [VRFC 10-307] analyzing entity Pipeline
  618. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  619. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  620. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  621. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  622. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  623. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  624. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  625. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  626. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  627. INFO: [VRFC 10-307] analyzing entity TestALU
  628. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  629. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  630. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  631. INFO: [VRFC 10-307] analyzing entity Test_LC
  632. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  633. INFO: [VRFC 10-307] analyzing entity Test_MUX
  634. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  635. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  636. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  637. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  638. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  639. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  640. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  641. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  642. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  643. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  644. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
  645. INFO: [USF-XSim-3] XSim::Elaborate design
  646. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  647. Vivado Simulator 2016.4
  648. Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
  649. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
  650. Using 2 slave threads.
  651. Starting static elaboration
  652. Completed static elaboration
  653. Starting simulation data flow analysis
  654. Completed simulation data flow analysis
  655. Time Resolution for simulation is 1ps
  656. Compiling package std.standard
  657. Compiling package std.textio
  658. Compiling package ieee.std_logic_1164
  659. Compiling package ieee.std_logic_arith
  660. Compiling package ieee.std_logic_unsigned
  661. Compiling package ieee.numeric_std
  662. Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
  663. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
  664. Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
  665. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  666. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  667. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  668. Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
  669. Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
  670. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  671. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  672. Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
  673. Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
  674. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  675. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  676. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  677. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  678. Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
  679. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
  680. Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
  681. Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
  682. Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
  683. Built simulation snapshot Test_Pipeline_behav
  684. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
  685. Vivado Simulator 2016.4
  686. Time resolution is 1 ps
  687. relaunch_sim
  688. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  689. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  690. INFO: [USF-XSim-97] Finding global include files...
  691. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  692. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  693. INFO: [USF-XSim-2] XSim::Compile design
  694. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  695. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  696. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  697. INFO: [VRFC 10-307] analyzing entity ALU
  698. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  699. INFO: [VRFC 10-307] analyzing entity System
  700. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  701. INFO: [VRFC 10-307] analyzing entity BancRegistres
  702. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  703. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  704. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  705. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  706. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  707. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  708. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  709. INFO: [VRFC 10-307] analyzing entity MUX
  710. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  711. INFO: [VRFC 10-307] analyzing entity LC
  712. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  713. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  714. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  715. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  716. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  717. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  718. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  719. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  720. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  721. INFO: [VRFC 10-307] analyzing entity Pipeline
  722. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  723. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  724. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  725. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  726. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  727. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  728. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  729. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  730. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  731. INFO: [VRFC 10-307] analyzing entity TestALU
  732. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  733. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  734. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  735. INFO: [VRFC 10-307] analyzing entity Test_LC
  736. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  737. INFO: [VRFC 10-307] analyzing entity Test_MUX
  738. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  739. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  740. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  741. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  742. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  743. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  744. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  745. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  746. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  747. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  748. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
  749. INFO: [USF-XSim-3] XSim::Elaborate design
  750. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  751. Vivado Simulator 2016.4
  752. Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
  753. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
  754. Using 2 slave threads.
  755. Starting static elaboration
  756. Completed static elaboration
  757. Starting simulation data flow analysis
  758. Completed simulation data flow analysis
  759. Time Resolution for simulation is 1ps
  760. Compiling package std.standard
  761. Compiling package std.textio
  762. Compiling package ieee.std_logic_1164
  763. Compiling package ieee.std_logic_arith
  764. Compiling package ieee.std_logic_unsigned
  765. Compiling package ieee.numeric_std
  766. Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
  767. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
  768. Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
  769. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  770. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  771. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  772. Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
  773. Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
  774. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  775. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  776. Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
  777. Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
  778. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  779. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  780. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  781. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  782. Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
  783. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
  784. Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
  785. Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
  786. Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
  787. Built simulation snapshot Test_Pipeline_behav
  788. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
  789. Vivado Simulator 2016.4
  790. Time resolution is 1 ps
  791. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
  792. restart
  793. INFO: [Simtcl 6-17] Simulation restarted
  794. run 100 us
  795. reset_run synth_1
  796. WARNING: [Vivado 12-1017] Problems encountered:
  797. 1. Failed to delete one or more files in run directory C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1
  798. launch_runs synth_1 -jobs 2
  799. [Mon May 10 18:17:42 2021] Launched synth_1...
  800. Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1/runme.log
  801. launch_runs impl_1 -jobs 2
  802. [Mon May 10 18:20:21 2021] Launched impl_1...
  803. Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
  804. launch_runs impl_1 -to_step write_bitstream -jobs 2
  805. [Mon May 10 18:21:46 2021] Launched impl_1...
  806. Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
  807. open_hw
  808. connect_hw_server
  809. INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
  810. INFO: [Labtools 27-2222] Launching hw_server...
  811. INFO: [Labtools 27-2221] Launch Output:
  812. ****** Xilinx hw_server v2016.4
  813. **** Build date : Jan 23 2017-19:37:29
  814. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  815. open_hw_target
  816. INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
  817. set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
  818. current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
  819. refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
  820. INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
  821. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
  822. Resolution:
  823. 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
  824. 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
  825. set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
  826. set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
  827. program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
  828. INFO: [Labtools 27-3164] End of startup status: HIGH
  829. refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
  830. INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
  831. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
  832. Resolution:
  833. 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
  834. 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
  835. WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
  836. WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
  837. WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
  838. WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
  839. restart
  840. INFO: [Simtcl 6-17] Simulation restarted
  841. run 100 us
  842. restart
  843. INFO: [Simtcl 6-17] Simulation restarted
  844. run 100 us
  845. save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
  846. ERROR: [Wavedata 42-440] There is no current wave configuration open to save
  847. save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
  848. ERROR: [Wavedata 42-440] There is no current wave configuration open to save
  849. save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
  850. ERROR: [Wavedata 42-440] There is no current wave configuration open to save
  851. restart
  852. INFO: [Simtcl 6-17] Simulation restarted
  853. run 100 us
  854. save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
  855. ERROR: [Wavedata 42-440] There is no current wave configuration open to save
  856. restart
  857. INFO: [Simtcl 6-17] Simulation restarted
  858. run 100 us
  859. save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
  860. ERROR: [Wavedata 42-440] There is no current wave configuration open to save
  861. save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
  862. ERROR: [Wavedata 42-440] There is no current wave configuration open to save
  863. save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
  864. ERROR: [Wavedata 42-440] There is no current wave configuration open to save
  865. ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA.
  866. Check cable connectivity and that the target board is powered up then
  867. use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
  868. ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
  869. close_hw
  870. relaunch_sim
  871. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  872. INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
  873. INFO: [USF-XSim-97] Finding global include files...
  874. INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
  875. INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
  876. INFO: [USF-XSim-2] XSim::Compile design
  877. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  878. "xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
  879. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
  880. INFO: [VRFC 10-307] analyzing entity ALU
  881. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
  882. INFO: [VRFC 10-307] analyzing entity System
  883. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
  884. INFO: [VRFC 10-307] analyzing entity BancRegistres
  885. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
  886. INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
  887. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
  888. INFO: [VRFC 10-307] analyzing entity MemoireInstructions
  889. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
  890. INFO: [VRFC 10-307] analyzing entity MemoireDonnees
  891. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
  892. INFO: [VRFC 10-307] analyzing entity MUX
  893. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
  894. INFO: [VRFC 10-307] analyzing entity LC
  895. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
  896. INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
  897. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
  898. INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
  899. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
  900. INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
  901. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
  902. INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
  903. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
  904. INFO: [VRFC 10-307] analyzing entity Pipeline
  905. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
  906. INFO: [VRFC 10-307] analyzing entity Clock_Divider
  907. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
  908. INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
  909. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
  910. INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
  911. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
  912. INFO: [VRFC 10-307] analyzing entity TestBancRegistres
  913. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
  914. INFO: [VRFC 10-307] analyzing entity TestALU
  915. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
  916. INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
  917. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
  918. INFO: [VRFC 10-307] analyzing entity Test_LC
  919. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
  920. INFO: [VRFC 10-307] analyzing entity Test_MUX
  921. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
  922. INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
  923. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
  924. INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
  925. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
  926. INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
  927. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
  928. INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
  929. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
  930. INFO: [VRFC 10-307] analyzing entity Test_Pipeline
  931. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
  932. INFO: [USF-XSim-3] XSim::Elaborate design
  933. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
  934. Vivado Simulator 2016.4
  935. Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
  936. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
  937. Using 2 slave threads.
  938. Starting static elaboration
  939. Completed static elaboration
  940. Starting simulation data flow analysis
  941. Completed simulation data flow analysis
  942. Time Resolution for simulation is 1ps
  943. Compiling package std.standard
  944. Compiling package std.textio
  945. Compiling package ieee.std_logic_1164
  946. Compiling package ieee.std_logic_arith
  947. Compiling package ieee.std_logic_unsigned
  948. Compiling package ieee.numeric_std
  949. Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
  950. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
  951. Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
  952. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  953. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  954. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  955. Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
  956. Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
  957. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  958. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  959. Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
  960. Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
  961. Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
  962. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  963. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
  964. Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
  965. Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
  966. Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
  967. Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
  968. Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
  969. Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
  970. Built simulation snapshot Test_Pipeline_behav
  971. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
  972. Vivado Simulator 2016.4
  973. Time resolution is 1 ps