----------------------------------------------------------------------------------
-- Company:  INSA-Toulouse
-- Engineer: Paul Faure
-- 
-- Create Date: 13.04.2021 10:07:41
-- Module Name: ALU - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: ALU 
-- 
-- Dependencies: None
--
-- Comments : Assynchrone
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Generic (Nb_bits : Natural); -- Taille d'un mot binaire
    Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Entrée 1 de l'ALU
           B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Entrée 2 de l'ALU
           OP : in STD_LOGIC_VECTOR (2 downto 0); -- Code d'opération de l'ALU
           S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Sortie de l'ALU
           N : out STD_LOGIC; -- Flag Negative
           O : out STD_LOGIC; -- Flag Overload
           Z : out STD_LOGIC; -- Flag Zero
           C : out STD_LOGIC);-- Flag Carry
end ALU;

architecture Behavioral of ALU is
    signal A9 :  STD_LOGIC_VECTOR (Nb_bits downto 0); -- Ajout d'un bit de poids fort supplémentaire (à 0)
    signal B9 :  STD_LOGIC_VECTOR (Nb_bits downto 0); -- Ajout d'un bit de poids fort supplémentaire (à 0)
    signal ADD :  STD_LOGIC_VECTOR (Nb_bits downto 0); -- A+B
    signal SUB :  STD_LOGIC_VECTOR (Nb_bits downto 0); -- A-B
    signal MUL :  STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0); -- A*B
    
    -- Signaux interne
    signal intern_N : STD_LOGIC;
    signal intern_Z : STD_LOGIC;
    
    -- Constantes
    constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
    constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
    
    
begin
    A9 <= '0' & A; -- Ajout d'un bit de poids fort supplémentaire (à 0)
    B9 <= '0' & B; -- Ajout d'un bit de poids fort supplémentaire (à 0)
    ADD <= A9 + B9; -- A+B
    SUB <= A9 - B9; -- A-B
    MUL <= A * B;   -- A*B 
    
    -- Selection de la sortie
    S <= ADD (Nb_bits-1 downto 0) when OP = "001" else 
         SUB (Nb_bits-1 downto 0) when OP = "010" else 
         MUL (Nb_bits-1 downto 0) when OP = "011" else
         -- Add division
         (0 => intern_N, others => '0') when OP = "101" else                                    -- Inferieur (<)
         (0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else   -- Superieur (>)
         (0 => intern_Z, others => '0') when OP = "111" else                                    -- Egal      (=)
         (others => '0');
         
         
    intern_N <= SUB (Nb_bits-1);
    intern_Z <= '1' when (SUB = ZERO_N1) else 
         '0';
         
    N <= intern_N;
    O <= '0' when (MUL ((2*Nb_bits)-1 downto Nb_bits) = ZERO_N) else
         '1';
    Z <= intern_Z;
    C <= ADD (Nb_bits);
end Behavioral;