---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 29.06.2021 16:16:32 -- Design Name: -- Module Name: TestTableASCII - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.font.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity TestTableASCII is -- Port ( ); end TestTableASCII; architecture Behavioral of TestTableASCII is component TableASCII is Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6); Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1)); end component; signal my_CodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000"; signal my_Font : STD_LOGIC_VECTOR (0 to 63) := (others => '0'); begin instance : TableASCII port map( CodeASCII => my_CodeASCII, Font => my_Font ); process begin my_CodeASCII <= "0000000" after 5 ns, "0000000" after 10 ns, "1000001" after 15 ns, "1000011" after 25 ns; wait; end process; end Behavioral;