Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 | Date : Fri Apr 09 23:16:38 2021 | Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200) | Command : report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx | Design : GPIO_demo | Device : xc7a35tcpg236-1 | Design State : routed | Grade : commercial | Process : typical | Characterization : Production ------------------------------------------------------------------------------------------------------------------------------------------------- Power Report Table of Contents ----------------- 1. Summary 1.1 On-Chip Components 1.2 Power Supply Summary 1.3 Confidence Level 2. Settings 2.1 Environment 2.2 Clock Constraints 3. Detailed Reports 3.1 By Hierarchy 1. Summary ---------- +--------------------------+-------+ | Total On-Chip Power (W) | 0.223 | | Dynamic (W) | 0.151 | | Device Static (W) | 0.072 | | Effective TJA (C/W) | 5.0 | | Max Ambient (C) | 83.9 | | Junction Temperature (C) | 26.1 | | Confidence Level | Low | | Setting File | --- | | Simulation Activity File | --- | | Design Nets Matched | NA | +--------------------------+-------+ 1.1 On-Chip Components ---------------------- +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ | Clocks | 0.005 | 5 | --- | --- | | Slice Logic | 0.003 | 1426 | --- | --- | | LUT as Logic | 0.002 | 564 | 20800 | 2.71 | | CARRY4 | <0.001 | 132 | 8150 | 1.62 | | Register | <0.001 | 578 | 41600 | 1.39 | | F7/F8 Muxes | <0.001 | 3 | 32600 | <0.01 | | Others | 0.000 | 18 | --- | --- | | Signals | 0.002 | 1137 | --- | --- | | MMCM | 0.123 | 1 | 5 | 20.00 | | I/O | 0.018 | 67 | 106 | 63.21 | | Static Power | 0.072 | | | | | Total | 0.223 | | | | +----------------+-----------+----------+-----------+-----------------+ 1.2 Power Supply Summary ------------------------ +-----------+-------------+-----------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | +-----------+-------------+-----------+-------------+------------+ | Vccint | 1.000 | 0.020 | 0.010 | 0.010 | | Vccaux | 1.800 | 0.081 | 0.069 | 0.013 | | Vcco33 | 3.300 | 0.006 | 0.005 | 0.001 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | | Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | +-----------+-------------+-----------+-------------+------------+ 1.3 Confidence Level -------------------- +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ | User Input Data | Confidence | Details | Action | +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ | Design implementation state | High | Design is routed | | | Clock nodes activity | High | User specified more than 95% of clocks | | | I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | | Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | | Device models | High | Device models are Production | | | | | | | | Overall confidence level | Low | | | +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ 2. Settings ----------- 2.1 Environment --------------- +-----------------------+--------------------------+ | Ambient Temp (C) | 25.0 | | ThetaJA (C/W) | 5.0 | | Airflow (LFM) | 250 | | Heat Sink | medium (Medium Profile) | | ThetaSA (C/W) | 4.6 | | Board Selection | medium (10"x10") | | # of Board Layers | 12to15 (12 to 15 Layers) | | Board Temperature (C) | 25.0 | +-----------------------+--------------------------+ 2.2 Clock Constraints --------------------- +--------------------+----------------------------------------------------+-----------------+ | Clock | Domain | Constraint (ns) | +--------------------+----------------------------------------------------+-----------------+ | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 | 9.3 | | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 | 10.0 | | sys_clk_pin | CLK | 10.0 | +--------------------+----------------------------------------------------+-----------------+ 3. Detailed Reports ------------------- 3.1 By Hierarchy ---------------- +-----------------------------+-----------+ | Name | Power (W) | +-----------------------------+-----------+ | GPIO_demo | 0.151 | | Inst_UART_TX_CTRL | <0.001 | | Inst_btn_debounce | <0.001 | | Inst_vga_ctrl | 0.130 | | Inst_MouseCtl | 0.004 | | Inst_Ps2Interface | 0.001 | | ps2_clk_IOBUF_inst | 0.000 | | ps2_data_IOBUF_inst | 0.000 | | Inst_MouseDisplay | <0.001 | | clk_wiz_0_inst | 0.124 | | U0 | 0.124 | +-----------------------------+-----------+