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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.04.2021 21:44:36
-- Design Name: 
-- Module Name: ClockDivider1000 - Structural
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ClockDivider1000 is
    Port ( clk_in : in STD_LOGIC;
           clk_out : out STD_LOGIC);
end ClockDivider1000;

architecture Structural of ClockDivider1000 is
    component ClockDivider10
        Port ( clk_in : in STD_LOGIC;
               clk_out : out STD_LOGIC);
    end component;
    
    signal aux1, aux2 : STD_LOGIC;
begin
    U1: ClockDivider10 port map(clk_in, aux1);
    U2: ClockDivider10 port map(aux1, aux2);
    U3: ClockDivider10 port map(aux2, clk_out);
end Structural;