----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.04.2021 10:19:15
-- Design Name: 
-- Module Name: System - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity System is
    Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
           sw : in STD_LOGIC_VECTOR (7 downto 0);
           btnC : in STD_LOGIC;
           CLK : STD_LOGIC);
end System;

architecture Structural of System is
    component Pipeline is
    Generic (Nb_bits : Natural := 8;
             Instruction_En_Memoire_Size : Natural := 29;
             Addr_Memoire_Instruction_Size : Natural := 3;
             Memoire_Instruction_Size : Natural := 8;
             Instruction_Bus_Size : Natural := 5;
             Nb_Instructions : Natural := 32;
             Nb_Registres : Natural := 16;
             Memoire_Size : Natural := 32;
             Memoire_Adresses_Retour_Size : Natural := 16;
             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
    Port (CLK : STD_LOGIC;
          RST : STD_LOGIC;
          STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
          STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
    end component;
    
    component Clock_Divider is
        Port ( CLK_IN : in STD_LOGIC;
               CLK_OUT : out STD_LOGIC);
    end component;
    
    signal my_RST : STD_LOGIC;
    signal my_CLK : STD_LOGIC;
    signal buff_CLK : STD_LOGIC;
        
begin
    clk_div : Clock_Divider
    port map (CLK_IN => CLK,
              CLK_OUT => buff_CLK);
              
    clk_div_2 : Clock_Divider
    port map (CLK_IN => buff_CLK,
              CLK_OUT => my_CLK);
              
    instance : Pipeline
    generic map (Addr_Memoire_Instruction_Size => 8,
                 Memoire_Instruction_Size => 256)
    port map (CLK => my_CLK,
              RST => my_RST,
              STD_IN => sw,
              STD_OUT => led);
              
    my_RST <= '0' when btnC = '1' else
              '1';
end Structural;