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-- Company: 
-- Engineer: 
-- 
-- Create Date: 28.06.2021 15:55:57
-- Design Name: 
-- Module Name: Test_VGAControler - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Test_VGAControler is
--  Port ( );
end Test_VGAControler;

architecture Behavioral of Test_VGAControler is

    constant Display_CaracterWidht  : Natural := 16;
    constant Display_CaracterHeight : Natural := 16;

    constant screen_width   : natural := 1280;
    constant screen_height  : natural := 1024;
    
    constant X_PulseWidth : Natural := 112;
    constant X_FrontPorch : Natural := 48;
    constant X_BackPorch  : Natural := 248;
    constant Y_PulseWidth : Natural := 3;
    constant Y_FrontPorch : Natural := 1;
    constant Y_BackPorch  : Natural := 38;
        
    subtype X_T is Natural range 0 to screen_width - 1;
    subtype Y_T is Natural range 0 to screen_height - 1;
    
    constant C_Blocks : Natural := screen_width/Display_CaracterWidht;
    constant L_Blocks : Natural := screen_height/Display_CaracterHeight;
    
    subtype L_T is Natural range 0 to L_Blocks - 1;
    subtype C_T is Natural range 0 to C_Blocks - 1;

    component VGAControler is
    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
               VGA_HS    : out STD_LOGIC;
               VGA_VS    : out STD_LOGIC;
               
               X         : out X_T;
               Y         : out Y_T;
               PIXEL_ON  : in STD_LOGIC;
               
               CLK       : in STD_LOGIC;
               RST       : in STD_LOGIC);
    end component; 
    
    
    signal my_VGA_RED   : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal my_VGA_BLUE  : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal my_VGA_GREEN : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal my_VGA_HS    : STD_LOGIC := '0';
    signal my_VGA_VS    : STD_LOGIC := '0';
   
    signal my_X         : X_T := 0;
    signal my_Y         : Y_T := 0;
    signal my_PIXEL_ON  : STD_LOGIC := '0';
   
    signal my_CLK       : STD_LOGIC := '0';
    signal my_RST       : STD_LOGIC := '1';
    
    constant CLK_period : time := 10 ns;

begin
    instance : VGAControler 
    port map(  VGA_RED   => my_VGA_RED,
               VGA_BLUE  => my_VGA_BLUE,
               VGA_GREEN => my_VGA_GREEN,
               VGA_HS    => my_VGA_HS,
               VGA_VS    => my_VGA_VS,
                 
               X         => my_X,
               Y         => my_Y,
               PIXEL_ON  => my_PIXEL_ON,
                 
               CLK       => my_CLK,
               RST       => my_RST);

    CLK_process : process
    begin
        my_CLK <= '0';
        wait for CLK_period/2;
        my_CLK <= '1';
        wait for CLK_period/2;
    end process;

    process 
    begin   
        my_PIXEL_ON <= '1' after 50 ns, '0' after 100 ns, '1' after 150 ns, '0' after 200 ns;
        wait;
    end process;  
      
end Behavioral;