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-- Company: 
-- Engineer: 
-- 
-- Create Date: 17.04.2021 22:43:43
-- Design Name: 
-- Module Name: Test_MUX - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_MUX is
--  Port ( );
end Test_MUX;

architecture Behavioral of Test_MUX is
component MUX is
    Generic (Nb_bits : Natural;
            Instruction_Vector_Size : Natural;
            Bits_Controle : STD_LOGIC_VECTOR);
    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
           IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
    
    signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal my_IN1 : STD_LOGIC_VECTOR (15 downto 0);
    signal my_IN2 : STD_LOGIC_VECTOR (15 downto 0);
    signal my_OUTPUT : STD_LOGIC_VECTOR (15 downto 0);
    
begin

    instance : MUX
    generic map (Nb_bits => 16,
                 Instruction_Vector_Size => 4,
                 Bits_Controle => x"aaaa")
    port map (
        Instruction => my_Instruction,
        IN1 => my_IN1,
        IN2 => my_IN2,
        OUTPUT => my_OUTPUT
    );
    
    process 
    begin
        my_IN1 <= x"abcd";
        my_IN2 <= x"1234";
        my_Instruction <= "0000" after 1 ns, "0001" after 2 ns, "0010" after 3 ns, "0011" after 4 ns, "0100" after 5 ns, "0101" after 6 ns, "0110" after 7 ns, "0111" after 8 ns;
        wait;
    end process;    
end Behavioral;