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-- Company: 
-- Engineer: 
-- 
-- Create Date: 17.04.2021 22:43:43
-- Design Name: 
-- Module Name: Test_LC - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_LC is
--  Port ( );
end Test_LC;

architecture Behavioral of Test_LC is
component LC is
    Generic (Instruction_Vector_Size : Natural;
            Command_size : Natural;
            Bits_Controle : STD_LOGIC_VECTOR);
    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
           Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end component;
    
    signal my_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
    signal my_Commande : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    constant Bits_Controle : STD_LOGIC_VECTOR (15 downto 0) := x"c138";
begin

    instance : LC
    generic map (Instruction_Vector_Size => 3,
                 Command_size => 2,
                 Bits_Controle => Bits_Controle)
    port map (
        Instruction => my_Instruction,
        Commande => my_Commande
    );
    
    process 
    begin
        my_Instruction <= "000" after 1 ns, "001" after 2 ns, "010" after 3 ns, "011" after 4 ns, "100" after 5 ns, "101" after 6 ns, "110" after 7 ns, "111" after 8 ns;
        wait;
    end process;    
end Behavioral;