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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.04.2021 21:25:53
-- Design Name: 
-- Module Name: TestALU - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TestALU is
--  Port ( );
end TestALU;

architecture Behavioral of TestALU is
    component   ALU is
        Generic (Nb_bits : Natural);
        Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
              B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
              OP : in STD_LOGIC_VECTOR (1 downto 0);
              S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
              N : out STD_LOGIC;
              O : out STD_LOGIC;
              Z : out STD_LOGIC;
              C : out STD_LOGIC);
    end component;
    
    signal my_A : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
    signal my_B : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
    signal my_OP : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal my_S : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
    signal my_N : STD_LOGIC := '0';
    signal my_O : STD_LOGIC := '0';
    signal my_Z : STD_LOGIC := '0';
    signal my_C : STD_LOGIC := '0';
    
begin

    instance : ALU
    generic map (Nb_bits => 16)
    port map (
        A => my_A,
        B => my_B,
        OP => my_OP,
        S => my_S,
        N => my_N,
        O => my_O,
        Z => my_Z,
        C => my_C
    );
    
    process 
    begin
        my_A <= x"0007" after 10 ns, x"00ff" after 100 ns;
        my_B <= x"0008" after 10 ns, x"ff01" after 100 ns;
        my_OP <= "01" after 10 ns, "10" after 30 ns, "11" after 50 ns, "01" after 67 ns, "00" after 100 ns;
        
        wait;
    end process;    
end Behavioral;