---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01.07.2021 13:37:43 -- Design Name: -- Module Name: SystemKeyboard - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity SystemKeyboard is Port (CLK : in STD_LOGIC; PS2Clk : in STD_LOGIC; PS2Data : in STD_LOGIC; led : out STD_LOGIC_VECTOR (0 to 10); btnC : in STD_LOGIC); end SystemKeyboard; architecture Behavioral of SystemKeyboard is component Keyboard Port (CLK : in STD_LOGIC; PS2Clk : in STD_LOGIC; PS2Data : in STD_LOGIC; Data_read : in STD_LOGIC; Data_av : out STD_LOGIC; Data : out STD_LOGIC_VECTOR (0 to 6); alert : out STD_LOGIC); end component; signal intern_Data_read : STD_LOGIC := '0'; signal intern_Data_av : STD_LOGIC := '0'; signal Data_Read : STD_LOGIC_VECTOR (0 to 6); begin instance_Keyboard : Keyboard port map (CLK => CLK, PS2Clk => PS2Clk, PS2Data => PS2Data, Data_read => intern_Data_read, Data_av => intern_Data_av, Data => Data_Read, alert => led(10)); led(7) <= '0'; led(8) <= intern_Data_av; led(9) <= intern_Data_read; process begin wait until CLK'event and CLK = '1'; if (intern_Data_av = '1' and btnC = '1') then led(0 to 6) <= Data_read; intern_Data_read <= '1'; else intern_Data_read <= '0'; end if; end process; end Behavioral;