---------------------------------------------------------------------------------- -- Company: INSA-Toulouse -- Engineer: Paul Faure -- -- Create Date: 13.04.2021 10:19:15 -- Module Name: System - Behavioral -- Project Name: Processeur sécurisé -- Target Devices: Basys 3 ARTIX7 -- Tool Versions: Vivado 2016.4 -- Description: Environnement du processeur, mapping entre le processeur et la carte -- -- Dependencies: -- - Clock_Divider -- - Pipeline ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Lien avec le fichier de contraintes -- Récupération des leds pour STD_OUT -- Récupération des switchs pour STD_IN -- Récupération d'un bouton pour RST -- Récupération de la clock entity System is Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0); vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; PS2Clk : in STD_LOGIC; PS2Data : in STD_LOGIC; btnC : in STD_LOGIC; CLK : STD_LOGIC); end System; architecture Structural of System is component Pipeline is Generic (Nb_bits : Natural := 8; Instruction_En_Memoire_Size : Natural := 29; Addr_Memoire_Instruction_Size : Natural := 3; Memoire_Instruction_Size : Natural := 8; Instruction_Bus_Size : Natural := 5; Nb_Instructions : Natural := 32; Nb_Registres : Natural := 16; Addr_registres_size : Natural := 4; Memoire_Size : Natural := 32; Adresse_mem_size : Natural := 5; Memoire_Adresses_Retour_Size : Natural := 16; Adresse_Memoire_Adresses_Retour_Size : Natural := 4); Port (CLK : in STD_LOGIC; RST : in STD_LOGIC; STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_IN_Av : in STD_LOGIC; STD_IN_Request : out STD_LOGIC; STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_OUT_Av : out STD_LOGIC; STD_OUT_Int : out STD_LOGIC); end component; component Pipeline_NS is Generic (Nb_bits : Natural := 8; Instruction_En_Memoire_Size : Natural := 29; Addr_Memoire_Instruction_Size : Natural := 3; Memoire_Instruction_Size : Natural := 8; Instruction_Bus_Size : Natural := 5; Nb_Instructions : Natural := 32; Nb_Registres : Natural := 16; Memoire_Size : Natural := 32); Port (CLK : STD_LOGIC; RST : STD_LOGIC; STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; component PeripheriqueEcran Generic ( Nb_Bits : Natural); Port ( CLK : in STD_LOGIC; CLK_VGA : in STD_LOGIC; RST : in STD_LOGIC; vgaRed : out STD_LOGIC_VECTOR (3 downto 0); vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); STD_OUT_Av : in STD_LOGIC; STD_OUT_Int : in STD_LOGIC); end component; component PeripheriqueClavier Generic (Nb_Bits : Natural); Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; PS2Clk : in STD_LOGIC; PS2Data : in STD_LOGIC; STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); STD_IN_Av : out STD_LOGIC; STD_IN_Request : in STD_LOGIC; STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); STD_OUT_Av : out STD_LOGIC); end component; component Clock_Divider is Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end component; -- signaux auxiliaires signal my_RST : STD_LOGIC; signal my_CLK : STD_LOGIC; signal STD_IN : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal STD_IN_Av : STD_LOGIC := '0'; signal STD_IN_Request : STD_LOGIC := '0'; signal intern_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal intern_STD_OUT_Av : STD_LOGIC := '0'; signal intern_STD_OUT_Int : STD_LOGIC := '0'; signal pipeline_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal pipeline_STD_OUT_Av : STD_LOGIC := '0'; signal pipeline_STD_OUT_Int : STD_LOGIC := '0'; signal clavier_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal clavier_STD_OUT_Av : STD_LOGIC := '0'; signal clavier_STD_OUT_Int : STD_LOGIC := '0'; constant SECURISED : boolean := true; begin -- Diviseur de clock clk_div : Clock_Divider port map (CLK_IN => CLK, CLK_OUT => my_CLK); -- Generation du processeur en fonction de la condition sécurisé ou non instance: if (SECURISED) generate instance_securisee : entity work.Pipeline generic map (Nb_bits => 16, Instruction_En_Memoire_Size => 53, Addr_Memoire_Instruction_Size => 9, Memoire_Instruction_Size => 512, Instruction_Bus_Size => 5, Nb_Instructions => 32, Nb_Registres => 16, Addr_registres_size => 4, Memoire_Size => 32, Adresse_mem_size => 5, Memoire_Adresses_Retour_Size => 4, Adresse_Memoire_Adresses_Retour_Size => 2) port map (CLK => my_CLK, RST => my_RST, STD_IN => STD_IN, STD_IN_Av => STD_IN_Av, STD_IN_Request => STD_IN_Request, STD_OUT => pipeline_STD_OUT, STD_OUT_Av => pipeline_STD_OUT_Av, STD_OUT_Int => pipeline_STD_OUT_Int); else generate instance_non_securisee : entity work.Pipeline_NS generic map (Addr_Memoire_Instruction_Size => 9, Memoire_Instruction_Size => 512) port map (CLK => my_CLK, RST => my_RST, STD_IN => STD_IN, STD_OUT => pipeline_STD_OUT); end generate; instance_perif_ecran : PeripheriqueEcran generic map ( Nb_Bits => 16) port map ( CLK => my_CLK, CLK_VGA => CLK, RST => my_RST, vgaRed => vgaRed, vgaBlue => vgaBlue, vgaGreen => vgaGreen, Hsync => Hsync, Vsync => Vsync, STD_OUT => intern_STD_OUT, STD_OUT_Av => intern_STD_OUT_Av, STD_OUT_Int => intern_STD_OUT_Int); instance_perif_clavier : PeripheriqueClavier generic map (Nb_Bits => 16) port map ( CLK => my_CLK, RST => my_RST, PS2Clk => PS2Clk, PS2Data => PS2Data, STD_IN => STD_IN, STD_IN_Av => STD_IN_Av, STD_IN_Request => STD_IN_Request, STD_OUT => clavier_STD_OUT, STD_OUT_Av => clavier_STD_OUT_Av); -- Gestion du RST (inversion d'état) my_RST <= '1' when btnC = '0' else '0'; intern_STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT; intern_STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av; intern_STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int; end Structural;