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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.04.2021 21:20:39
-- Design Name: 
-- Module Name: Compteur - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Compteur is
    Port ( CK : in STD_LOGIC;
           RST : in STD_LOGIC;
           SENS : in STD_LOGIC;
           LOAD : in STD_LOGIC;
           EN : in STD_LOGIC;
           Din : in STD_LOGIC_VECTOR (7 downto 0);
           Dout : out STD_LOGIC_VECTOR (7 downto 0));
end Compteur;

architecture Behavioral of Compteur is
    signal aux: STD_LOGIC_VECTOR (7 downto 0);
begin
    Dout <= aux;
    process
    begin
        wait until CK'event and CK='1';
        if RST = '0' then
            aux <= (others => '0');
        elsif LOAD = '1' then
            aux <= Din;
        elsif EN = '0' then
            if SENS = '1' then
                aux <= aux + 1;
            else 
                aux <= aux - 1;
            end if;
        end if;
    end process;
end Behavioral;