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-- Company: 
-- Engineer: 
-- 
-- Create Date: 01.07.2021 09:09:30
-- Design Name: 
-- Module Name: KeyboardControler - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity KeyboardControler is
  Port (CLK : in STD_LOGIC;
  
        PS2Clk : in STD_LOGIC;
        PS2Data : in STD_LOGIC;
        
        Data_av : out STD_LOGIC;
        Data : out STD_LOGIC_VECTOR (0 to 7);
        
        alert : out STD_LOGIC);
end KeyboardControler;

architecture Behavioral of KeyboardControler is

    subtype compteur_T is Natural range 0 to 10;
    signal compteur : compteur_T := 0;
    signal current_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
    signal previous_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
    signal parity : STD_LOGIC := '0';
    signal intern_alert : STD_LOGIC := '0';
    signal intern_Data_av : STD_LOGIC := '0';
    signal dejaSignale : boolean := false;

begin
    
    process 
    begin
        wait until PS2Clk'event and PS2Clk = '1';
        case compteur is
        when 0 =>
            parity <= '1'; 
            intern_alert <= '0';   
            intern_Data_av <= '0';
        when 1 =>
            current_data(7) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 2 =>
            current_data(6) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 3 =>
            current_data(5) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 4 =>
            current_data(4) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 5 =>
            current_data(3) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 6 =>
            current_data(2) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 7 =>
            current_data(1) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 8 =>
            current_data(0) <= PS2Data;
            parity <= parity XOR PS2Data;
        when 9 =>
            if (parity = PS2Data) then
                intern_alert <= '0';
            else 
                intern_alert <= '1';
            end if;
        when 10 =>
            if (intern_alert = '0') then
                previous_data <= current_data;
                if (not (previous_data = "11110000" or current_data = "11110000" or previous_data = "11100000")) then
                    Data <= current_data;
                    intern_Data_av <= '1';
                end if; 
            end if;
        end case;
    
        compteur <= (compteur + 1) mod 11;
    end process;
    
    process
    begin
        wait until CLK'event and CLK = '1';
        if (intern_Data_av = '1' and not dejaSignale) then
            Data_av <= '1';
            dejaSignale <= true;
        else 
            Data_av <= '0';
        end if;
        if (intern_Data_av = '0') then
            dejaSignale <= false;
        end if;
    end process; 

    alert <= intern_alert;
    
end Behavioral;