---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05.07.2021 15:20:28 -- Design Name: -- Module Name: Compteur_X - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.ScreenProperties.all; entity Compteur_X is Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; Value : out X_T; Carry : out STD_LOGIC); end Compteur_X; architecture Behavioral of Compteur_X is signal current : X_T := 0; signal intern_Carry : STD_LOGIC := '0'; begin process begin wait until CLK'event and CLK = '1'; if (RST = '0') then current <= 0; else current <= current + 1; if (current = screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1) then intern_Carry <= '1'; current <= 0; else intern_Carry <= '0'; end if; end if; end process; Value <= current; Carry <= intern_Carry; end Behavioral;