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-- Company: 
-- Engineer: 
-- 
-- Create Date: 05.07.2021 16:38:12
-- Design Name: 
-- Module Name: Test_Compteur - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;




-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_Compteur is
--  Port ( );
end Test_Compteur;

architecture Behavioral of Test_Compteur is

    constant screen_width   : natural := 1280;
    constant screen_height  : natural := 1040;
        
    subtype X_T is Natural range 0 to screen_width - 1;
    subtype Y_T is Natural range 0 to screen_height - 1;

    component Compteur_X is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           Value : out X_T;
           Carry : out STD_LOGIC);
    end component;
    
    component Compteur_Y is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           Value : out Y_T);
    end component;
   
    signal my_Carry : STD_LOGIC := '0';
    signal my_Value : X_T := 0;
    signal my_Value_Y : X_T := 0;
   
    signal my_CLK       : STD_LOGIC := '0';
    signal my_RST       : STD_LOGIC := '1';
    
    constant CLK_period : time := 10 ns;

begin

    inst_Compteur_X : Compteur_X 
    Port map ( CLK => my_CLK,
               RST => my_RST,
               Value => my_Value,
               Carry => my_Carry);
               
    inst_Compteur_Y : Compteur_Y 
    Port map ( CLK => my_Carry,
               RST => my_RST,
               Value => my_Value_Y);

    CLK_process : process
    begin
        my_CLK <= '0';
        wait for CLK_period/2;
        my_CLK <= '1';
        wait for CLK_period/2;
    end process;

    process 
    begin   
        wait;
    end process;  
      
end Behavioral;