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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.04.2021 14:35:04
-- Design Name: 
-- Module Name: MemoireAdressesRetour - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MemoireAdressesRetour is
    Generic (Nb_bits : Natural;
             Addr_size : Natural;
             Mem_size : Natural);
    Port ( R : in STD_LOGIC;
           W : in STD_LOGIC;
           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           RST : in STD_LOGIC;
           CLK : in STD_LOGIC;
           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
           E : out STD_LOGIC;
           F : out STD_LOGIC);
end MemoireAdressesRetour;

architecture Behavioral of MemoireAdressesRetour is
    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
    signal Addr : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
    constant EMPTY : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
    constant FULL : STD_LOGIC_VECTOR (Addr_size downto 0) := (Addr_size => '1', others => '0');
begin
    process
    begin
        wait until CLK'event and CLK = '1';
        if (RST = '0' ) then
            MEMORY <= (others => '0');
            Addr <= (others => '0');
        else
            if (W = '1') then
                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
                Addr <= Addr + 1;
            elsif (R = '1') then 
                Addr <= Addr - 1;
            end if;
        end if;
    end process;
    E <= '1' when Addr = EMPTY else
         '0';
    F <= '1' when Addr = FULL else
         '0';
         
    D_OUT <= (others => '0') when Addr = EMPTY else
             MEMORY (to_integer(unsigned(Addr)) * Nb_bits - 1 downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
end Behavioral;