----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.04.2021 21:42:26
-- Design Name: 
-- Module Name: ClockDivider10 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ClockDivider10 is
    Port ( clk_in : in STD_LOGIC;
           clk_out : out STD_LOGIC);
end ClockDivider10;

architecture Behavioral of ClockDivider10 is
    subtype int10 is INTEGER range 0 to 10;
    signal N : int10 := 0;
    signal aux : STD_LOGIC;
begin
    process
    begin
        wait until clk_in'event and clk_in = '1';
        N <= N + 1;
        if N = 10 then
            aux <= not aux;
            N <= 0;
        end if;
    end process;
    clk_out <= aux;
end Behavioral;