Version fonctionnelle processeur non sécurisé

.gitignore

 Processeur.runs/*
 Processeur.sim/*
 vivado*
-.Xil
+.Xil
+*.log

Processeur.srcs/sim_1/new/Test_Pipeline.vhd

              Instruction_Bus_Size : Natural := 5;
              Nb_Instructions : Natural := 32;
              Nb_Registres : Natural := 16;
-             Memoire_Size : Natural := 32;
-             Memoire_Adresses_Retour_Size : Natural := 16;
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
+             Memoire_Size : Natural := 32);
     Port (CLK : STD_LOGIC;
           RST : STD_LOGIC;
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
     
     process 
     begin
+        my_STD_IN <= "00000001" after 300 us, "00000010" after 710 us, "00000011" after 1120 us, "00000100" after 1530 us, "00000101" after 1940 us, "00000110" after 2350 us, "00000111" after 2760 us, "00001000" after 3170 us, "00001001" after 3580 us, "00000000" after 3990 us; 
         wait;
     end process;
 end Behavioral;

Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd

              Nb_bits : Natural; -- Taille d'un mot binaire
              Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
              Nb_registres : Natural; -- Nombre de registres du processeurs
-             Mem_adresse_retour_size : Natural; -- Taille de la mémoire des adresses de retour (nombre d'adresse maximum) (profondeur d'appel maximale)
-             Adresse_size_mem_adresse_retour : Natural; -- Nombre de bits pour adresser la mémoire des adresses de retour
              Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande A (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeA)
              Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande B (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeB)
              Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande C (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeC)
     Port ( CLK : in STD_LOGIC; -- Clock
            RST : in STD_LOGIC; -- Reset
            Z : in STD_LOGIC;   -- Flag Zero de l'ALU (utile pour le JMZ)
+           Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
            D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
     end component;
     
-    component MemoireAdressesRetour is
-        Generic (Nb_bits : Natural;
-                 Addr_size : Natural;
-                 Mem_size : Natural);
-        Port ( R : in STD_LOGIC;
-               W : in STD_LOGIC;
-               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
-               RST : in STD_LOGIC;
-               CLK : in STD_LOGIC;
-               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
-               E : out STD_LOGIC;
-               F : out STD_LOGIC);
-    end component;
-    
     -- Signaux pour récuperer l'instruction de la mémoire
     signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
-    signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
     signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
     
     
     subtype Registre is integer range -1 to Nb_registres - 1;
     type Tab_registres is array (1 to 3) of Registre;
     signal Tableau : Tab_registres := (others => - 1);
-    
-    -- Signaux de gestion pour la mémoire des adresses de retour
-    signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
-    signal E : STD_LOGIC;
-    signal F : STD_LOGIC;
-    signal R_Aux : STD_LOGIC := '0';
-    signal W_Aux : STD_LOGIC := '0';
 
     -- constantes pour injecter des bulles dans le pipeline
     constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
                  Mem_size => Mem_instruction_size)
     port map (Addr => Pointeur_Instruction,
               D_OUT => Instruction_courante);
-              
-    instance_MemoireAdressesRetour : MemoireAdressesRetour
-    generic map (Nb_bits => Addr_size_mem_instruction,
-                 Addr_size => Adresse_size_mem_adresse_retour,
-                 Mem_size => Mem_adresse_retour_size
-    )
-    port map ( R => R_Aux,
-               W => W_Aux,
-               D_IN => Pointeur_instruction_next,
-               RST => RST,
-               CLK => CLK,
-               D_OUT => Adresse_Retour,
-               E => E,
-               F => F
-    );
 
               
     process 
             if (not bulles) then
                 -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
                 if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
-                    -- CAS PARTICULIER : CALL ou JMP, on transmet et on saute
-                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
+                    -- CAS PARTICULIER : CALL ou JMP, on transmet (en modifiant le paramètre A pour le CALL (addr de retour à stocker))et on saute
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); -- STOCKER
                     B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
-                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
+                    A <= ((Nb_bits - 1 downto Addr_size_mem_instruction => '0') & Pointeur_Instruction) + 1;
                     Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
                     Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
-                    -- CAS PARTICULIER : RET, on transmet et on revient 
-                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
-                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
-                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
-                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
-                    Pointeur_Instruction <= Adresse_Retour;
+                    -- CAS PARTICULIER : RET, on transmet une seule fois, on attend et on revient 
+                    compteur <= compteur + 1;
+                    if (compteur = 1) then
+                        C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
+                        B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
+                        A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
+                        Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
+                    elsif (compteur = 5) then
+                        Pointeur_Instruction <= Addr_Retour (Addr_size_mem_instruction - 1 downto 0);
+                        compteur <= 0;
+                    else 
+                        C <= Argument_nul;
+                        B <= Argument_nul;
+                        A <= Argument_nul;
+                        Instruction <= Instruction_nulle;
+                    end if;
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
                     -- CAS PARTICULIER : JMZ, on attends que l'instruction précedente arrive sur l'ALU, si le flag Zero est a un on saute, sinon on continue normalement
                     compteur <= compteur + 1;
                             locked <= true;
                         end if;
                         compteur <= compteur + 1;
-                        if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)))) then
+                        if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) * 1000) then
                             Pointeur_Instruction <= Pointeur_Instruction + 1;
                             compteur <= 0;
                         end if;
         )
     );
     
-    -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour
-    R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
-             '0';
-    W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
-             '0';
-             
-             
-    Pointeur_instruction_next <= Pointeur_instruction + 1;
+
 end Behavioral;

Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd

     
     -- Un multiplexeur pourrait être utilisé ici, mais cela n'a pas été jugé pertinent
     Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else
-                                STD_IN when IN_2_Instruction = Code_Instruction_GET else
+                                STD_IN when IN_5_Instruction = Code_Instruction_GET else
                                 IN_5_B;
     
     

Processeur.srcs/sources_1/new/Etage4_Memoire.vhd

     CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
              '0';
              
-    New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
-    EBP <= New_EBP when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_CALL else 
-           Last_EBP (Adresse_mem_size - 1 downto 0) when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_RET else
-           (others => '0') when RST = '0' else 
-           EBP;
+    process 
+    begin
+        wait until CLK'event and CLK = '1';
+        if (IN_Instruction = Code_Instruction_CALL) then
+            EBP <= New_EBP;
+        elsif (IN_Instruction = Code_Instruction_RET) then 
+            EBP <= Last_EBP (Adresse_mem_size - 1 downto 0);
+        elsif (RST = '0') then
+            EBP <= (others => '0');
+        end if;
+    end process;
+           
+   New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
     IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP;
            
     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;

Processeur.srcs/sources_1/new/MemoireDonnees.vhd

                 MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP;
                 MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet;
             elsif (RET = '1') then
-                OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2));
-                OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
+                MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto ((to_integer(unsigned(Addr)) - 2) * Nb_bits)) <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr)));
             elsif (RW = '0') then
                 MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
             end if;
     
     -- Lecture assynchrone et en permanence
     D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
+    
+    -- Sortie lors du ret en assynchrone
+    OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2)) when (RET = '1') else 
+               (others => '0'); 
+    OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1)) when (RET = '1') else 
+                   (others => '0');
 end Behavioral;

Processeur.srcs/sources_1/new/Pipeline.vhd

              Nb_Registres : Natural := 16;
              Addr_registres_size : Natural := 4;
              Memoire_Size : Natural := 32;
-             Adresse_mem_size : Natural := 5;
-             Memoire_Adresses_Retour_Size : Natural := 16;
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
+             Adresse_mem_size : Natural := 5);
     Port (CLK : STD_LOGIC;
           RST : STD_LOGIC;
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
              Nb_bits : Natural;
              Instruction_bus_size : Natural;
              Nb_registres : Natural;
-             Mem_adresse_retour_size : Natural;
-             Adresse_size_mem_adresse_retour : Natural;
              Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
              Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
              Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
     Port ( CLK : in STD_LOGIC;
            RST : in STD_LOGIC;
            Z : in STD_LOGIC;
+           Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
                   Mem_size : Natural;
                   Adresse_mem_size : Natural;
                   Instruction_bus_size : Natural;
-                  Mem_EBP_size : Natural;
-                  Adresse_size_mem_EBP : Natural;
                   Bits_Controle_LC : STD_LOGIC_VECTOR;
                   Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
                   Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
                IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
                OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
                OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
-               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
+               OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); 
     end component;
     
     signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
     signal Z : STD_LOGIC := '0';
     signal O : STD_LOGIC := '0';
     signal C : STD_LOGIC := '0';
+    signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
     
     constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
     constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
     constant Bits_Controle_LC_3         : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
     constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
-    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
-    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
-    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
+    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; -- LC
+    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1101111110101111111111";
+    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1001111011001111111111"; -- EBP
     constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
     constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
     constant Code_Instruction_JMP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
                  Nb_bits => Nb_bits,
                  Instruction_bus_size => Instruction_Bus_Size,
                  Nb_registres => Nb_Registres,
-                 Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
-                 Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
                  Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
                  Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
                  Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
         CLK => CLK,
         RST => RST,
         Z => Z,
+        Addr_Retour => AdresseRetour,
         A => A_from_1,
         B => B_from_1,
         C => C_from_1,
                  Mem_size => Memoire_Size,
                  Adresse_mem_size => Adresse_mem_size,
                  Instruction_bus_size => Instruction_Bus_Size,
-                 Mem_EBP_size => Memoire_Adresses_Retour_Size,
-                 Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
                  Bits_Controle_LC => Bits_Controle_LC_4,
                  Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
                  Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
                  IN_Instruction => Instruction_to_4,
                  OUT_A => A_from_4,
                  OUT_B => B_from_4,
-                 OUT_Instruction => Instruction_from_4
+                 OUT_Instruction => Instruction_from_4,
+                 OUT_AddrRetour => AdresseRetour
     );
 
     process

Processeur.srcs/sources_1/new/System.vhd

              Instruction_Bus_Size : Natural := 5;
              Nb_Instructions : Natural := 32;
              Nb_Registres : Natural := 16;
-             Memoire_Size : Natural := 32;
-             Memoire_Adresses_Retour_Size : Natural := 16;
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
+             Memoire_Size : Natural := 32);
     Port (CLK : STD_LOGIC;
           RST : STD_LOGIC;
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
     -- signaux auxiliaires
     signal my_RST : STD_LOGIC;
     signal my_CLK : STD_LOGIC;
-    signal buff_CLK : STD_LOGIC;
         
-begin
-    -- Premier diviseur de clock
+begin     
+    -- Diviseur de clock
     clk_div : Clock_Divider
     port map (CLK_IN => CLK,
-              CLK_OUT => buff_CLK);
-              
-    -- Second diviseur de clock
-    clk_div_2 : Clock_Divider
-    port map (CLK_IN => buff_CLK,
               CLK_OUT => my_CLK);
               
     -- Le processeur, augmentation de la taille de la mémoire d'instruction

Processeur.xpr

     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
     <Option Name="DSANumComputeUnits" Val="16"/>
-    <Option Name="WTXSimLaunchSim" Val="287"/>
+    <Option Name="WTXSimLaunchSim" Val="339"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="Test_Etage4_Memoire"/>
+        <Option Name="TopModule" Val="Test_Pipeline"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>

SimulationsConfig/Test_Pipeline_behav1.wcfg

    <wave_state>
    </wave_state>
    <db_ref_list>
-      <db_ref path="Test_Pipeline_behav1.wdb" id="1">
+      <db_ref path="Test_Pipeline_behav.wdb" id="1">
          <top_modules>
             <top_module name="Test_Pipeline" />
          </top_modules>
       </db_ref>
    </db_ref_list>
    <zoom_setting>
-      <ZoomStartTime time="320666666fs"></ZoomStartTime>
-      <ZoomEndTime time="441266667fs"></ZoomEndTime>
-      <Cursor1Time time="404267000fs"></Cursor1Time>
+      <ZoomStartTime time="9750000000fs"></ZoomStartTime>
+      <ZoomEndTime time="10289000001fs"></ZoomEndTime>
+      <Cursor1Time time="10000000000fs"></Cursor1Time>
    </zoom_setting>
    <column_width_setting>
       <NameColumnWidth column_width="146"></NameColumnWidth>
-      <ValueColumnWidth column_width="73"></ValueColumnWidth>
+      <ValueColumnWidth column_width="71"></ValueColumnWidth>
    </column_width_setting>
-   <WVObjectSize size="10" />
-   <wvobject fp_name="/Test_Pipeline/my_CLK" type="logic">
+   <WVObjectSize size="12" />
+   <wvobject type="logic" fp_name="/Test_Pipeline/my_CLK">
       <obj_property name="ElementShortName">my_CLK</obj_property>
       <obj_property name="ObjectShortName">my_CLK</obj_property>
    </wvobject>
-   <wvobject fp_name="/Test_Pipeline/my_RST" type="logic">
+   <wvobject type="logic" fp_name="/Test_Pipeline/my_RST">
       <obj_property name="ElementShortName">my_RST</obj_property>
       <obj_property name="ObjectShortName">my_RST</obj_property>
    </wvobject>
-   <wvobject fp_name="/Test_Pipeline/my_STD_IN" type="array">
+   <wvobject type="array" fp_name="/Test_Pipeline/my_STD_IN">
       <obj_property name="ElementShortName">my_STD_IN[7:0]</obj_property>
       <obj_property name="ObjectShortName">my_STD_IN[7:0]</obj_property>
    </wvobject>
-   <wvobject fp_name="/Test_Pipeline/my_STD_OUT" type="array">
+   <wvobject type="array" fp_name="/Test_Pipeline/my_STD_OUT">
       <obj_property name="ElementShortName">my_STD_OUT[7:0]</obj_property>
       <obj_property name="ObjectShortName">my_STD_OUT[7:0]</obj_property>
    </wvobject>
-   <wvobject fp_name="/Test_Pipeline/CLK_period" type="other">
+   <wvobject type="other" fp_name="/Test_Pipeline/CLK_period">
       <obj_property name="ElementShortName">CLK_period</obj_property>
       <obj_property name="ObjectShortName">CLK_period</obj_property>
    </wvobject>
-   <wvobject fp_name="group20" type="group">
+   <wvobject type="group" fp_name="group20">
       <obj_property name="label">Etage1</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_1" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_1">
          <obj_property name="ElementShortName">Instruction_from_1[4:0]</obj_property>
          <obj_property name="ObjectShortName">Instruction_from_1[4:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_1" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_1">
          <obj_property name="ElementShortName">A_from_1[7:0]</obj_property>
          <obj_property name="ObjectShortName">A_from_1[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_1" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_1">
          <obj_property name="ElementShortName">B_from_1[7:0]</obj_property>
          <obj_property name="ObjectShortName">B_from_1[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/C_from_1" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/C_from_1">
          <obj_property name="ElementShortName">C_from_1[7:0]</obj_property>
          <obj_property name="ObjectShortName">C_from_1[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject fp_name="group21" type="group">
+   <wvobject type="group" fp_name="group21">
       <obj_property name="label">Etage2</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_2" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_2">
          <obj_property name="ElementShortName">Instruction_from_2[4:0]</obj_property>
          <obj_property name="ObjectShortName">Instruction_from_2[4:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_2" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_2">
          <obj_property name="ElementShortName">A_from_2[7:0]</obj_property>
          <obj_property name="ObjectShortName">A_from_2[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_2" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_2">
          <obj_property name="ElementShortName">B_from_2[7:0]</obj_property>
          <obj_property name="ObjectShortName">B_from_2[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/C_from_2" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/C_from_2">
          <obj_property name="ElementShortName">C_from_2[7:0]</obj_property>
          <obj_property name="ObjectShortName">C_from_2[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject fp_name="group22" type="group">
+   <wvobject type="group" fp_name="group22">
       <obj_property name="label">Etage3</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_3" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_3">
          <obj_property name="ElementShortName">Instruction_from_3[4:0]</obj_property>
          <obj_property name="ObjectShortName">Instruction_from_3[4:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_3" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_3">
          <obj_property name="ElementShortName">A_from_3[7:0]</obj_property>
          <obj_property name="ObjectShortName">A_from_3[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_3" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_3">
          <obj_property name="ElementShortName">B_from_3[7:0]</obj_property>
          <obj_property name="ObjectShortName">B_from_3[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject fp_name="group23" type="group">
+   <wvobject type="group" fp_name="group23">
       <obj_property name="label">Etage4</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_4" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_4">
          <obj_property name="ElementShortName">Instruction_from_4[4:0]</obj_property>
          <obj_property name="ObjectShortName">Instruction_from_4[4:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_4" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_4">
          <obj_property name="ElementShortName">A_from_4[7:0]</obj_property>
          <obj_property name="ObjectShortName">A_from_4[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_4" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_4">
          <obj_property name="ElementShortName">B_from_4[7:0]</obj_property>
          <obj_property name="ObjectShortName">B_from_4[7:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject fp_name="group31" type="group">
+   <wvobject type="group" fp_name="group31">
       <obj_property name="label">Registres</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/REGISTRES" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/REGISTRES">
          <obj_property name="ElementShortName">REGISTRES[127:0]</obj_property>
          <obj_property name="ObjectShortName">REGISTRES[127:0]</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrA" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrA">
          <obj_property name="ElementShortName">AddrA[3:0]</obj_property>
          <obj_property name="ObjectShortName">AddrA[3:0]</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrB" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrB">
          <obj_property name="ElementShortName">AddrB[3:0]</obj_property>
          <obj_property name="ObjectShortName">AddrB[3:0]</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrC" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrC">
          <obj_property name="ElementShortName">AddrC[3:0]</obj_property>
          <obj_property name="ObjectShortName">AddrC[3:0]</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrW" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrW">
          <obj_property name="ElementShortName">AddrW[3:0]</obj_property>
          <obj_property name="ObjectShortName">AddrW[3:0]</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/W" type="logic">
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/W">
          <obj_property name="ElementShortName">W</obj_property>
          <obj_property name="ObjectShortName">W</obj_property>
       </wvobject>
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/DATA" type="array">
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/DATA">
          <obj_property name="ElementShortName">DATA[7:0]</obj_property>
          <obj_property name="ObjectShortName">DATA[7:0]</obj_property>
       </wvobject>
    </wvobject>
+   <wvobject type="group" fp_name="group115">
+      <obj_property name="label">Memoire</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/MEMORY">
+         <obj_property name="ElementShortName">MEMORY[255:0]</obj_property>
+         <obj_property name="ObjectShortName">MEMORY[255:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_OUT">
+         <obj_property name="ElementShortName">D_OUT[7:0]</obj_property>
+         <obj_property name="ObjectShortName">D_OUT[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_AddrRet">
+         <obj_property name="ElementShortName">OUT_AddrRet[7:0]</obj_property>
+         <obj_property name="ObjectShortName">OUT_AddrRet[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_EBP">
+         <obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
+         <obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_AddrRet">
+         <obj_property name="ElementShortName">IN_AddrRet[7:0]</obj_property>
+         <obj_property name="ObjectShortName">IN_AddrRet[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_EBP">
+         <obj_property name="ElementShortName">IN_EBP[7:0]</obj_property>
+         <obj_property name="ObjectShortName">IN_EBP[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/CALL">
+         <obj_property name="ElementShortName">CALL</obj_property>
+         <obj_property name="ObjectShortName">CALL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RET">
+         <obj_property name="ElementShortName">RET</obj_property>
+         <obj_property name="ObjectShortName">RET</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/Addr">
+         <obj_property name="ElementShortName">Addr[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Addr[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_IN">
+         <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
+         <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RW">
+         <obj_property name="ElementShortName">RW</obj_property>
+         <obj_property name="ObjectShortName">RW</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Last_EBP">
+         <obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
+         <obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/EBP">
+         <obj_property name="ElementShortName">EBP[4:0]</obj_property>
+         <obj_property name="ObjectShortName">EBP[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees">
+         <obj_property name="ElementShortName">Addr_MemoireDonnees[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/IN_Addr_MemoireDonnees">
+         <obj_property name="ElementShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
+         <obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees_EBP">
+         <obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group121">
+      <obj_property name="label">Instructions</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage1/Z">
+         <obj_property name="ElementShortName">Z</obj_property>
+         <obj_property name="ObjectShortName">Z</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Addr_Retour">
+         <obj_property name="ElementShortName">Addr_Retour[7:0]</obj_property>
+         <obj_property name="ObjectShortName">Addr_Retour[7:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Pointeur_instruction">
+         <obj_property name="ElementShortName">Pointeur_instruction[7:0]</obj_property>
+         <obj_property name="ObjectShortName">Pointeur_instruction[7:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Instruction_courante">
+         <obj_property name="ElementShortName">Instruction_courante[28:0]</obj_property>
+         <obj_property name="ObjectShortName">Instruction_courante[28:0]</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Tableau">
+         <obj_property name="ElementShortName">Tableau[1:3]</obj_property>
+         <obj_property name="ObjectShortName">Tableau[1:3]</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/bulles">
+         <obj_property name="ElementShortName">bulles</obj_property>
+         <obj_property name="ObjectShortName">bulles</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/compteur">
+         <obj_property name="ElementShortName">compteur</obj_property>
+         <obj_property name="ObjectShortName">compteur</obj_property>
+      </wvobject>
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/locked">
+         <obj_property name="ElementShortName">locked</obj_property>
+         <obj_property name="ObjectShortName">locked</obj_property>
+      </wvobject>
+   </wvobject>
 </wave_config>