From eef4708fbaefab57b4c4e49d0ca7311e9f0f8b85 Mon Sep 17 00:00:00 2001 From: Faure Paul Date: Mon, 19 Jul 2021 18:55:23 +0200 Subject: [PATCH] Finito, reste a mettre au propre --- Processeur.srcs/sources_1/new/Ecran.vhd | 22 +- .../new/Etage1_LectureInstruction_NS.vhd | 32 +- .../sources_1/new/MemoireInstructions.vhd | 2 +- Processeur.srcs/sources_1/new/Pipeline.vhd | 2 +- Processeur.srcs/sources_1/new/Pipeline_NS.vhd | 106 +++-- .../sources_1/new/ScreenDriver.vhd | 26 +- .../sources_1/new/ScreenProperties.vhd | 6 +- Processeur.srcs/sources_1/new/System.vhd | 34 +- Processeur.xpr | 2 +- SimulationsConfig/TestSystem_behav.wcfg | 426 ++++++++---------- 10 files changed, 336 insertions(+), 322 deletions(-) diff --git a/Processeur.srcs/sources_1/new/Ecran.vhd b/Processeur.srcs/sources_1/new/Ecran.vhd index 48df9eb..6e68be5 100644 --- a/Processeur.srcs/sources_1/new/Ecran.vhd +++ b/Processeur.srcs/sources_1/new/Ecran.vhd @@ -67,6 +67,11 @@ architecture Behavioral of Ecran is signal CurrentCodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000"; signal CurrentFont : STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1) := (others => '0'); + signal position_X : X_T := 0; + signal position_Y : Y_T := 0; + + signal active : Boolean := false; + begin instance_TableASCII : TableASCII @@ -106,14 +111,19 @@ begin L_inc <= "0000000" when L + 1 = L_Blocks else L + 1; InitialL_inc <= "0000000" when InitialL + 1 = L_Blocks else InitialL + 1; - L_Lecture <= Y/Display_CaracterHeight + to_integer(unsigned(InitialL)) - L_Blocks when (Y/Display_CaracterHeight + to_integer(unsigned(InitialL))) >= L_Blocks else Y/Display_CaracterHeight + to_integer(unsigned(InitialL)); - - point_dereferencement <= (7 * (C_Blocks * L_Lecture + (X/Display_CaracterWidht))); point_dereferencement_ecriture <= 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C))); - CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y < screen_height and X < screen_width and RST='1') else - "0000000"; + + + + position_X <= X - margin when X >= 0 + margin and X < screen_width - margin else 0; + position_Y <= Y - margin when Y >= 0 + margin and Y < screen_height - margin else 0; + active <= X >= 0 + margin and X < screen_width - margin and Y >= 0 + margin and Y < screen_height - margin; + L_Lecture <= position_Y/Display_CaracterHeight + to_integer(unsigned(InitialL)) - L_Blocks when (position_Y/Display_CaracterHeight + to_integer(unsigned(InitialL))) >= L_Blocks else position_Y/Display_CaracterHeight + to_integer(unsigned(InitialL)); + point_dereferencement <= (7 * (C_Blocks * L_Lecture + (position_X/Display_CaracterWidht))); + + CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6); - OUT_ON <= CurrentFont(((Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width)); + OUT_ON <= CurrentFont(((position_Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (position_X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width)) when active else '0'; end Behavioral; diff --git a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd index d760337..2284461 100644 --- a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd +++ b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd @@ -50,12 +50,15 @@ entity Etage1_LectureInstruction_NS is Code_Instruction_JMP : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMP Code_Instruction_JMZ : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMZ + Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI + Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL Code_Instruction_RET : STD_LOGIC_VECTOR; -- Numéro de l'instruction RET Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP Port ( CLK : in STD_LOGIC; -- Clock RST : in STD_LOGIC; -- Reset Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ) + STD_IN_Request : in STD_LOGIC; Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4 A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B @@ -94,6 +97,9 @@ architecture Behavioral of Etage1_LectureInstruction_NS is -- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k signal compteur : integer := 0; + -- Compteur de protection des collisions entre les prints + signal Compteur_PRI : integer range 0 to Nb_bits/4 + 1 := 0; + -- Signal d'arret (STOP 0) signal locked : boolean := false; @@ -115,16 +121,20 @@ begin Tableau <= (others => -1); Pointeur_Instruction <= (others => '0'); compteur <= 0; + Compteur_PRI <= 0; locked <= false; C <= Argument_nul; B <= Argument_nul; A <= Argument_nul; Instruction <= Instruction_nulle; - else + elsif (STD_IN_Request = '0') then -- Avancement des instructions en écritures dans le pipeline Tableau(3) <= Tableau(2); Tableau(2) <= Tableau(1); Tableau(1) <= -1; + if (Compteur_PRI > 0) then + Compteur_PRI <= Compteur_PRI - 1; + end if; if (not bulles) then -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if) if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then @@ -184,6 +194,14 @@ begin B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); + elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) then + -- CAS PARTICULIER : PRI, on transmet l'instruction et fixe le compteur pour proteger des collisions + Compteur_PRI <= Nb_bits/4 + 1; + C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); + B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); + A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); + Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); + Pointeur_Instruction <= Pointeur_Instruction + 1; else -- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); @@ -248,6 +266,18 @@ begin or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3)) ) + ) + or + ( + ( + (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) + or + (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRIC) + ) + and + ( + not (Compteur_PRI = 0) + ) ); diff --git a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd index 407e8b3..101bb99 100644 --- a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd +++ b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd @@ -32,7 +32,7 @@ end MemoireInstructions; architecture Behavioral of MemoireInstructions is -- Do not touch until (-- Skadoosh) -- Do not add any Skadoosh - signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := 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+ signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := 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-- Skadoosh begin D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr))); diff --git a/Processeur.srcs/sources_1/new/Pipeline.vhd b/Processeur.srcs/sources_1/new/Pipeline.vhd index 2e27daf..e3b661b 100644 --- a/Processeur.srcs/sources_1/new/Pipeline.vhd +++ b/Processeur.srcs/sources_1/new/Pipeline.vhd @@ -208,7 +208,7 @@ architecture Behavioral of Pipeline is constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111"; constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000"; constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001"; - constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; -------- TO BE DONE + constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011"; constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100"; constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101"; diff --git a/Processeur.srcs/sources_1/new/Pipeline_NS.vhd b/Processeur.srcs/sources_1/new/Pipeline_NS.vhd index 8494c9a..f4becba 100644 --- a/Processeur.srcs/sources_1/new/Pipeline_NS.vhd +++ b/Processeur.srcs/sources_1/new/Pipeline_NS.vhd @@ -44,8 +44,12 @@ entity Pipeline_NS is Adresse_mem_size : Natural := 5); Port (CLK : STD_LOGIC; RST : STD_LOGIC; - STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC); end Pipeline_NS; architecture Behavioral of Pipeline_NS is @@ -63,12 +67,15 @@ architecture Behavioral of Pipeline_NS is Instructions_critiques_ecriture : STD_LOGIC_VECTOR; Code_Instruction_JMP : STD_LOGIC_VECTOR; Code_Instruction_JMZ : STD_LOGIC_VECTOR; + Code_Instruction_PRI : STD_LOGIC_VECTOR; + Code_Instruction_PRIC : STD_LOGIC_VECTOR; Code_Instruction_CALL : STD_LOGIC_VECTOR; Code_Instruction_RET : STD_LOGIC_VECTOR; Code_Instruction_STOP : STD_LOGIC_VECTOR); Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; Z : in STD_LOGIC; + STD_IN_Request : in STD_LOGIC; Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4 A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); @@ -85,11 +92,16 @@ architecture Behavioral of Pipeline_NS is Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; Code_Instruction_PRI : STD_LOGIC_VECTOR; + Code_Instruction_PRIC : STD_LOGIC_VECTOR; Code_Instruction_GET : STD_LOGIC_VECTOR); Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; - STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC; IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); @@ -178,27 +190,31 @@ architecture Behavioral of Pipeline_NS is signal C : STD_LOGIC := '0'; signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); - constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111"; - constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001"; + signal intern_STD_IN_Request : STD_LOGIC := '0'; + + + constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11110011101111111111111"; + constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111000011000000001"; constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000"; - constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001"; - constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; -- LC - constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1101111110101111111111"; - constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1001111011001111111111"; -- EBP - constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000"; - constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110"; + constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111111111100000001"; + constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111001011111111111"; + constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111110101111111111"; + constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "10011111011001111111111"; + constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000001010000000000"; + constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110"; constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111"; constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000"; constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001"; - constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; - constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011"; - constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100"; - constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101"; + constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; + constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011"; + constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100"; + constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101"; + constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10110"; - constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000"; - constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110"; - constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110"; - constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110"; + constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00001100010000000000000"; + constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000111100111111110"; + constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000000000011111110"; + constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110"; begin instance_Etage1 : Etage1_LectureInstruction_NS generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size, @@ -213,6 +229,8 @@ begin Instructions_critiques_ecriture => Instructions_critiques_ecriture, Code_Instruction_JMP => Code_Instruction_JMP, Code_Instruction_JMZ => Code_Instruction_JMZ, + Code_Instruction_PRI => Code_Instruction_PRI, + Code_Instruction_PRIC => Code_Instruction_PRIC, Code_Instruction_CALL => Code_Instruction_CALL, Code_Instruction_RET => Code_Instruction_RET, Code_Instruction_STOP => Code_Instruction_STOP @@ -221,6 +239,7 @@ begin CLK => CLK, RST => RST, Z => Z, + STD_IN_Request => intern_STD_IN_Request, Addr_Retour => AdresseRetour, A => A_from_1, B => B_from_1, @@ -237,12 +256,17 @@ begin Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A, Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B, Code_Instruction_PRI => Code_Instruction_PRI, + Code_Instruction_PRIC => Code_Instruction_PRIC, Code_Instruction_GET => Code_Instruction_GET ) port map( CLK => CLK, RST => RST, - STD_IN => STD_IN, - STD_OUT => STD_OUT, + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => intern_STD_IN_Request, + STD_OUT => STD_OUT, + STD_OUT_Av => STD_OUT_Av, + STD_OUT_Int => STD_OUT_Int, IN_2_A => A_to_2, IN_2_B => B_to_2, IN_2_C => C_to_2, @@ -298,27 +322,31 @@ begin OUT_Instruction => Instruction_from_4, OUT_AddrRetour => AdresseRetour ); + + STD_IN_Request <= intern_STD_IN_Request; process begin wait until CLK'event and CLK = '1'; - A_to_2 <= A_from_1; - B_to_2 <= B_from_1; - C_to_2 <= C_from_1; - Instruction_to_2 <= Instruction_from_1; - - A_to_3 <= A_from_2; - B_to_3 <= B_from_2; - C_to_3 <= C_from_2; - Instruction_to_3 <= Instruction_from_2; - - A_to_4 <= A_from_3; - B_to_4 <= B_from_3; - Instruction_to_4 <= Instruction_from_3; - - A_to_5 <= A_from_4; - B_to_5 <= B_from_4; - Instruction_to_5 <= Instruction_from_4; + if (intern_STD_IN_Request = '0') then + A_to_2 <= A_from_1; + B_to_2 <= B_from_1; + C_to_2 <= C_from_1; + Instruction_to_2 <= Instruction_from_1; + + A_to_3 <= A_from_2; + B_to_3 <= B_from_2; + C_to_3 <= C_from_2; + Instruction_to_3 <= Instruction_from_2; + + A_to_4 <= A_from_3; + B_to_4 <= B_from_3; + Instruction_to_4 <= Instruction_from_3; + + A_to_5 <= A_from_4; + B_to_5 <= B_from_4; + Instruction_to_5 <= Instruction_from_4; + end if; end process; end Behavioral; diff --git a/Processeur.srcs/sources_1/new/ScreenDriver.vhd b/Processeur.srcs/sources_1/new/ScreenDriver.vhd index f1f9d1a..f729cf7 100644 --- a/Processeur.srcs/sources_1/new/ScreenDriver.vhd +++ b/Processeur.srcs/sources_1/new/ScreenDriver.vhd @@ -48,16 +48,17 @@ architecture Behavioral of ScreenDriver is signal intern_value : STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0) := (others => '0'); signal current_hexa : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); - subtype compteur_T is Natural range 0 to Nb_bits/4 - 1; - signal compteur : compteur_T := 0; - signal work_in_progess : BOOLEAN := false; - signal x_to_send : BOOLEAN := false; + subtype compteur_T is Integer range -2 to Nb_bits/4 - 1; + signal compteur : compteur_T := -2; signal first_detected : BOOLEAN := false; + + + constant Code_ASCII_Zero : STD_LOGIC_VECTOR (0 to 6) := "0110000"; begin - current_hexa <= intern_value(Nb_Bits - 1 - compteur * 4 downto Nb_Bits - compteur * 4 - 4); + current_hexa <= intern_value(Nb_Bits - 1 - compteur * 4 downto Nb_Bits - compteur * 4 - 4) when compteur >= 0 and compteur < Nb_Bits else "0000"; process begin @@ -67,15 +68,14 @@ begin OutData <= Value (6 downto 0); else intern_value <= Value; - OutData <= "0110000"; - x_to_send <= true; + OutData <= Code_ASCII_Zero; + compteur <= compteur + 1; end if; OutDataAv <= '1'; - elsif x_to_send then + elsif compteur = -1 then OutData <= "1111000"; - x_to_send <= false; - work_in_progess <= true; - elsif work_in_progess then + compteur <= compteur + 1; + elsif compteur >= 0 then if (current_hexa >= "0000" and current_hexa <= "1001") then if (not(current_hexa = "0000") or first_detected or compteur = Nb_bits/4 - 1 ) then OutData <= "011" & current_hexa; @@ -91,9 +91,7 @@ begin end if; if (compteur = Nb_bits/4 - 1) then - compteur <= 0; - work_in_progess <= false; - x_to_send <= false; + compteur <= -2; first_detected <= false; else compteur <= compteur + 1; diff --git a/Processeur.srcs/sources_1/new/ScreenProperties.vhd b/Processeur.srcs/sources_1/new/ScreenProperties.vhd index dad662b..9ad151b 100644 --- a/Processeur.srcs/sources_1/new/ScreenProperties.vhd +++ b/Processeur.srcs/sources_1/new/ScreenProperties.vhd @@ -2,6 +2,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; package ScreenProperties is + + constant margin : Natural := 64; constant Display_CaracterWidht : Natural := 64; constant Display_CaracterHeight : Natural := 64; @@ -19,8 +21,8 @@ package ScreenProperties is subtype X_T is Natural range 0 to screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1; subtype Y_T is Natural range 0 to screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1; - constant C_Blocks : Natural := screen_width/Display_CaracterWidht; - constant L_Blocks : Natural := screen_height/Display_CaracterHeight; + constant C_Blocks : Natural := (screen_width - (2 * margin))/Display_CaracterWidht; + constant L_Blocks : Natural := (screen_height - (2 * margin))/Display_CaracterHeight; constant Ecran_Taille : Natural := C_Blocks * L_Blocks * 7; constant L_Size : Natural := C_Blocks * 7; diff --git a/Processeur.srcs/sources_1/new/System.vhd b/Processeur.srcs/sources_1/new/System.vhd index d027b58..5553807 100644 --- a/Processeur.srcs/sources_1/new/System.vhd +++ b/Processeur.srcs/sources_1/new/System.vhd @@ -68,11 +68,17 @@ architecture Structural of System is Instruction_Bus_Size : Natural := 5; Nb_Instructions : Natural := 32; Nb_Registres : Natural := 16; - Memoire_Size : Natural := 32); + Addr_registres_size : Natural := 4; + Memoire_Size : Natural := 32; + Adresse_mem_size : Natural := 5); Port (CLK : STD_LOGIC; RST : STD_LOGIC; - STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC); end component; component PeripheriqueEcran @@ -126,7 +132,7 @@ architecture Structural of System is signal clavier_STD_OUT_Av : STD_LOGIC := '0'; signal clavier_STD_OUT_Int : STD_LOGIC := '0'; - constant SECURISED : boolean := true; + constant SECURISED : boolean := false; begin @@ -161,12 +167,24 @@ begin STD_OUT_Int => pipeline_STD_OUT_Int); else generate instance_non_securisee : entity work.Pipeline_NS - generic map (Addr_Memoire_Instruction_Size => 9, - Memoire_Instruction_Size => 512) + generic map (Nb_bits => 16, + Instruction_En_Memoire_Size => 53, + Addr_Memoire_Instruction_Size => 9, + Memoire_Instruction_Size => 512, + Instruction_Bus_Size => 5, + Nb_Instructions => 32, + Nb_Registres => 16, + Addr_registres_size => 4, + Memoire_Size => 64, + Adresse_mem_size => 6) port map (CLK => my_CLK, RST => my_RST, - STD_IN => STD_IN, - STD_OUT => pipeline_STD_OUT); + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => STD_IN_Request, + STD_OUT => pipeline_STD_OUT, + STD_OUT_Av => pipeline_STD_OUT_Av, + STD_OUT_Int => pipeline_STD_OUT_Int); end generate; instance_perif_ecran : PeripheriqueEcran diff --git a/Processeur.xpr b/Processeur.xpr index bf2d4ab..e810b40 100644 --- a/Processeur.xpr +++ b/Processeur.xpr @@ -35,7 +35,7 @@