Implémentation demo

Processeur.srcs/sources_1/new/System.vhd

               CLK_OUT => my_CLK);
               
     instance : Pipeline
-    generic map (Addr_Memoire_Instruction_Size => 7,
-                 Memoire_Instruction_Size => 128)
+    generic map (Addr_Memoire_Instruction_Size => 8,
+                 Memoire_Instruction_Size => 256)
     port map (CLK => my_CLK,
               RST => my_RST,
               STD_IN => sw,