diff --git a/Processeur.srcs/sim_1/new/Test_Pipeline.vhd b/Processeur.srcs/sim_1/new/Test_Pipeline.vhd index c7682c2..454feab 100644 --- a/Processeur.srcs/sim_1/new/Test_Pipeline.vhd +++ b/Processeur.srcs/sim_1/new/Test_Pipeline.vhd @@ -63,8 +63,8 @@ architecture Behavioral of Test_Pipeline is begin instance : Pipeline - generic map (Addr_Memoire_Instruction_Size => 7, - Memoire_Instruction_Size => 128) + generic map (Addr_Memoire_Instruction_Size => 8, + Memoire_Instruction_Size => 256) port map (CLK => my_CLK, RST => my_RST, STD_IN => my_STD_IN, diff --git a/Processeur.srcs/sources_1/new/ALU.vhd b/Processeur.srcs/sources_1/new/ALU.vhd index 1538bae..80ab03f 100644 --- a/Processeur.srcs/sources_1/new/ALU.vhd +++ b/Processeur.srcs/sources_1/new/ALU.vhd @@ -1,75 +1,69 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 13.04.2021 10:07:41 --- Design Name: -- Module Name: ALU - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- +-- Description: ALU -- +-- Dependencies: None +-- +-- Comments : Assynchrone ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity ALU is - Generic (Nb_bits : Natural); - Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - OP : in STD_LOGIC_VECTOR (2 downto 0); - S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - N : out STD_LOGIC; - O : out STD_LOGIC; - Z : out STD_LOGIC; - C : out STD_LOGIC); + Generic (Nb_bits : Natural); -- Taille d'un mot binaire + Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Entrée 1 de l'ALU + B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Entrée 2 de l'ALU + OP : in STD_LOGIC_VECTOR (2 downto 0); -- Code d'opération de l'ALU + S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Sortie de l'ALU + N : out STD_LOGIC; -- Flag Negative + O : out STD_LOGIC; -- Flag Overload + Z : out STD_LOGIC; -- Flag Zero + C : out STD_LOGIC);-- Flag Carry end ALU; architecture Behavioral of ALU is - signal A9 : STD_LOGIC_VECTOR (Nb_bits downto 0); - signal B9 : STD_LOGIC_VECTOR (Nb_bits downto 0); - signal ADD : STD_LOGIC_VECTOR (Nb_bits downto 0); - signal SUB : STD_LOGIC_VECTOR (Nb_bits downto 0); - signal MUL : STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0); + signal A9 : STD_LOGIC_VECTOR (Nb_bits downto 0); -- Ajout d'un bit de poids fort supplémentaire (à 0) + signal B9 : STD_LOGIC_VECTOR (Nb_bits downto 0); -- Ajout d'un bit de poids fort supplémentaire (à 0) + signal ADD : STD_LOGIC_VECTOR (Nb_bits downto 0); -- A+B + signal SUB : STD_LOGIC_VECTOR (Nb_bits downto 0); -- A-B + signal MUL : STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0); -- A*B + + -- Signaux interne signal intern_N : STD_LOGIC; signal intern_Z : STD_LOGIC; + + -- Constantes constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0'); constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0'); begin - A9 <= '0' & A; - B9 <= '0' & B; - ADD <= A9 + B9; - SUB <= A9 - B9; - MUL <= A * B; + A9 <= '0' & A; -- Ajout d'un bit de poids fort supplémentaire (à 0) + B9 <= '0' & B; -- Ajout d'un bit de poids fort supplémentaire (à 0) + ADD <= A9 + B9; -- A+B + SUB <= A9 - B9; -- A-B + MUL <= A * B; -- A*B + -- Selection de la sortie S <= ADD (Nb_bits-1 downto 0) when OP = "001" else SUB (Nb_bits-1 downto 0) when OP = "010" else MUL (Nb_bits-1 downto 0) when OP = "011" else -- Add division - (0 => intern_N, others => '0') when OP = "101" else - (0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else - (0 => intern_Z, others => '0') when OP = "111" else + (0 => intern_N, others => '0') when OP = "101" else -- Inferieur (<) + (0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else -- Superieur (>) + (0 => intern_Z, others => '0') when OP = "111" else -- Egal (=) (others => '0'); diff --git a/Processeur.srcs/sources_1/new/BancRegistres.vhd b/Processeur.srcs/sources_1/new/BancRegistres.vhd index 92838c2..dae8d0f 100644 --- a/Processeur.srcs/sources_1/new/BancRegistres.vhd +++ b/Processeur.srcs/sources_1/new/BancRegistres.vhd @@ -1,70 +1,62 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 15.04.2021 08:23:48 --- Design Name: -- Module Name: BancRegistres - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Banc de registre -- +-- Dependencies: None +-- +-- Comments : +-- - Il est possible de lire 3 registres en simultané +-- - Si on souhaite lire et ecrire dans un même registre, l'écriture est prioritaire ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; ---use IEEE.STD_LOGIC_UNSIGNED.ALL; ---use IEEE.STD_LOGIC_ARITH.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity BancRegistres is - Generic (Nb_bits : Natural; - Addr_size : Natural; - Nb_regs : Natural); - Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); - AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); - AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); - AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); - W : in STD_LOGIC; - DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - RST : in STD_LOGIC; - CLK : in STD_LOGIC; - QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0)); + Generic (Nb_bits : Natural; -- Taille d'un mot dans un registre + Addr_size : Natural; -- Nombres de bits nécessaires pour adresser les registres + Nb_regs : Natural); -- Nombre de registre + Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- Adresse (numéro) du registre A à lire + AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- Adresse (numéro) du registre B à lire + AddrC : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- Adresse (numéro) du registre C à lire + AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- Adresse (numéro) du registre W où ecrire + W : in STD_LOGIC; -- Flag d'écriture ('1' -> écriture) + DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Donnée a écrire + RST : in STD_LOGIC; -- Reset + CLK : in STD_LOGIC; -- Clock + QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Sortie : Valeur contenue dans le registre AddrA + QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Sortie : Valeur contenue dans le registre AddrB + QC : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));-- Sortie : Valeur contenue dans le registre AddrC end BancRegistres; --- ASK MEILLEURE IDEE UN TABLEAU + architecture Behavioral of BancRegistres is - signal REGISTRES : STD_LOGIC_VECTOR ((Nb_regs * Nb_bits)-1 downto 0) := (others => '0'); + signal REGISTRES : STD_LOGIC_VECTOR ((Nb_regs * Nb_bits)-1 downto 0) := (others => '0'); -- Buffer (registres) begin process begin + -- Synchronisation wait until CLK'event and CLK = '1'; if (RST = '0') then REGISTRES <= (others => '0'); else + -- Ecriture if (W = '1') then REGISTRES (((to_integer(unsigned(AddrW)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(AddrW))) <= DATA; end if; end if; end process; + + -- Lecture en Assynchrone (donc écriture prioritaire) QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA))); QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB))); QC <= REGISTRES (((to_integer(unsigned(AddrC)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrC))); diff --git a/Processeur.srcs/sources_1/new/Clock_Divider.vhd b/Processeur.srcs/sources_1/new/Clock_Divider.vhd index 4daa657..619ffca 100644 --- a/Processeur.srcs/sources_1/new/Clock_Divider.vhd +++ b/Processeur.srcs/sources_1/new/Clock_Divider.vhd @@ -1,50 +1,42 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 08.05.2021 21:00:25 --- Design Name: -- Module Name: Clock_Divider - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Diviseur de clock (rapport de 1000) -- +-- Dependencies: None ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity Clock_Divider is Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end Clock_Divider; architecture Behavioral of Clock_Divider is + -- Compteur pour le diviseur signal N : Integer := 0; + -- Signal enregistrant l'ancienne valeur de CLK signal CLK : STD_LOGIC := '1'; begin process begin + -- Synchronisation wait until CLK_IN'event and CLK_IN = '1'; + + -- Incrementation du compteur N <= N + 1; + if (N = 1000) then + -- Remise a 0 et changement d'état de la CLK N <= 0; if (CLK = '1') then CLK <= '0'; @@ -53,5 +45,7 @@ begin end if; end if; end process; + + -- Sortie du signal (assynchrone -> imédiat) CLK_OUT <= CLK; end Behavioral; diff --git a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd index 2c326b1..3c09720 100644 --- a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd +++ b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd @@ -1,64 +1,71 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 18.04.2021 21:19:41 --- Design Name: -- Module Name: Etage1_LectureInstruction - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Etage 1 du processeur +-- - Gestion des instructions, lecture en mémoire +-- - Gestion des aléas sur les registres +-- - Gestion des sauts et appels de fonction -- -- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- +-- - MemoireInstruction +-- - MemoireAdressesRetour ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; entity Etage1_LectureInstruction is - Generic (Instruction_size_in_memory : Natural; - Addr_size_mem_instruction : Natural; - Mem_instruction_size : Natural; - Nb_bits : Natural; - Instruction_bus_size : Natural; - Nb_registres : Natural; - Mem_adresse_retour_size : Natural; - Adresse_size_mem_adresse_retour : Natural; - Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; - Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; - Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; - Instructions_critiques_ecriture : STD_LOGIC_VECTOR; - Code_Instruction_JMP : STD_LOGIC_VECTOR; - Code_Instruction_JMZ : STD_LOGIC_VECTOR; - Code_Instruction_CALL : STD_LOGIC_VECTOR; - Code_Instruction_RET : STD_LOGIC_VECTOR; - Code_Instruction_STOP : STD_LOGIC_VECTOR); - Port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; - Z : in STD_LOGIC; - A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); + Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire) + Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction + Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées) + Nb_bits : Natural; -- Taille d'un mot binaire + Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) + Nb_registres : Natural; -- Nombre de registres du processeurs + Mem_adresse_retour_size : Natural; -- Taille de la mémoire des adresses de retour (nombre d'adresse maximum) (profondeur d'appel maximale) + Adresse_size_mem_adresse_retour : Natural; -- Nombre de bits pour adresser la mémoire des adresses de retour + Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande A (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeA) + Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande B (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeB) + Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande C (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeC) + Instructions_critiques_ecriture : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques en écriture (toujours sur l'opérande A) (si le bit i est a un, l'instruction i ecrit une valeur dans le registre n°opérandeA) + + -- Exemple 1 : Soit MUL i j k avec pour numéro d'instruction 7 avec le comportement Ri <- Rj*Rk + -- Instructions_critiques_lecture_A(7) = '0' --> MUL ne lit pas dans le registre de l'opérande A + -- Instructions_critiques_lecture_B(7) = '1' --> MUL lit dans le registre de l'opérande B + -- Instructions_critiques_lecture_C(7) = '1' --> MUL lit dans le registre de l'opérande C + -- Instructions_critiques_ecriture(7) = '1' --> MUL ecrit dans le registre de l'opérande A + + -- Exemple 2 : Soit AFC i val avec pour numéro d'instruction 5 avec le comportement Ri <- val + -- Instructions_critiques_lecture_A(5) = '0' --> AFC ne lit pas dans le registre de l'opérande A + -- Instructions_critiques_lecture_B(5) = '0' --> AFC ne lit pas dans le registre de l'opérande B (pour AFC, B est directement la valeur, pas un numero de registre, il n'y a donc pas de lecture) + -- Instructions_critiques_lecture_C(5) = '0' --> AFC ne lit pas dans le registre de l'opérande C + -- Instructions_critiques_ecriture(5) = '1' --> AFC ecrit dans le registre de l'opérande A + + Code_Instruction_JMP : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMP + Code_Instruction_JMZ : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMZ + Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL + Code_Instruction_RET : STD_LOGIC_VECTOR; -- Numéro de l'instruction RET + Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP + Port ( CLK : in STD_LOGIC; -- Clock + RST : in STD_LOGIC; -- Reset + Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ) + A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A + B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B + C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C + Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction end Etage1_LectureInstruction; + + architecture Behavioral of Etage1_LectureInstruction is component MemoireInstructions is Generic (Nb_bits : Natural; @@ -82,26 +89,35 @@ architecture Behavioral of Etage1_LectureInstruction is F : out STD_LOGIC); end component; + -- Signaux pour récuperer l'instruction de la mémoire signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0'); signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0'); signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0'); + + -- Tableau pour gérer les aléas des registres (lecture en étage 2 avant écriture en étage 5) subtype Registre is integer range -1 to Nb_registres - 1; type Tab_registres is array (1 to 3) of Registre; signal Tableau : Tab_registres := (others => - 1); + -- Signaux de gestion pour la mémoire des adresses de retour signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0'); signal E : STD_LOGIC; signal F : STD_LOGIC; signal R_Aux : STD_LOGIC := '0'; signal W_Aux : STD_LOGIC := '0'; + -- constantes pour injecter des bulles dans le pipeline constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0'); constant Argument_nul : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); + -- condition pour detecter si une bulle doit être injectée signal bulles : boolean := false; + -- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k signal compteur : integer := 0; + + -- Signal d'arret (STOP 0) signal locked : boolean := false; begin @@ -130,8 +146,10 @@ begin process begin + -- Synchronisation wait until CLK'event and CLK = '1'; if (RST = '0') then + -- Reset de l'étage Tableau <= (others => -1); Pointeur_Instruction <= (others => '0'); compteur <= 0; @@ -141,23 +159,28 @@ begin A <= Argument_nul; Instruction <= Instruction_nulle; else + -- Avancement des instructions en écritures dans le pipeline Tableau(3) <= Tableau(2); Tableau(2) <= Tableau(1); Tableau(1) <= -1; if (not bulles) then + -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if) if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then + -- CAS PARTICULIER : CALL ou JMP, on transmet et on saute C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits); elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then + -- CAS PARTICULIER : RET, on transmet et on revient C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); Pointeur_Instruction <= Adresse_Retour; elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then + -- CAS PARTICULIER : JMZ, on attends que l'instruction précedente arrive sur l'ALU, si le flag Zero est a un on saute, sinon on continue normalement compteur <= compteur + 1; C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); @@ -172,6 +195,9 @@ begin compteur <= 0; end if; elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_STOP) then + -- CAS PARTICULIER : STOP, si on est bloqué, on ne fait rien, programme arrété + -- sinon, on regarde si l'on doit se bloquer + -- sinon, on incremente le compteur et on attends if (not locked) then if (Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits) = Argument_nul) then locked <= true; @@ -187,6 +213,7 @@ begin A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); else + -- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); @@ -197,6 +224,7 @@ begin Pointeur_Instruction <= Pointeur_Instruction + 1; end if; else + -- Si besoin de bulle, on l'injecte C <= Argument_nul; B <= Argument_nul; A <= Argument_nul; @@ -206,19 +234,19 @@ begin end process; - -- Condition degueu -> Instruction critique en lecture simple qui lit dans B et B dans tableau ou instruction critique en lecture double qui lit dans C et C dans tableau + -- Condition horrible -> Instruction critique en lecture sur A qui lit dans A=i et Ri dans tableau ou instruction critique en lecture sur B qui lit dans B=j et Rj dans tableau ou instruction critique en lecture sur C qui lit dans C=k et Rk dans tableau bulles <= ( ( - Instructions_critiques_lecture_A(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1' + Instructions_critiques_lecture_A(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1' -- Intruction critique sur A ) and ( - (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(1)) + (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(1)) -- A est or - (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(2)) + (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(2)) -- dans le or - (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(3)) + (to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(3)) -- tableau ) ) or @@ -250,10 +278,12 @@ begin ) ); - + -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else '0'; W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else '0'; + + Pointeur_instruction_next <= Pointeur_instruction + 1; end Behavioral; diff --git a/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd b/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd index 14bbf93..f7ac55a 100644 --- a/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd +++ b/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd @@ -1,61 +1,51 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 18.04.2021 21:19:41 --- Design Name: -- Module Name: Etage2_5_Registres - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Etage 2 et 5 du processeur +-- - Gestion des registres, lecture étage 2 et écriture étage 5 +-- - Lecture et Ecriture dans les entrées sorties du processeur -- -- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- +-- - BancRegistres +-- - LC +-- - MUX ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity Etage2_5_Registres is - Generic ( Nb_bits : Natural; - Nb_registres : Natural; - Addr_registres_size : Natural; - Instruction_bus_size : Natural; - Bits_Controle_LC_5 : STD_LOGIC_VECTOR; - Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; - Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; - Code_Instruction_PRI : STD_LOGIC_VECTOR; - Code_Instruction_GET : STD_LOGIC_VECTOR); - Port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; - STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); - OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); - IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); + Generic ( Nb_bits : Natural; -- Taille d'un mot binaire + Nb_registres : Natural; -- Nombre de registres du processeurs + Addr_registres_size : Natural; -- Nombre de bits pour adresser les registres + Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) + Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd) + Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd) + Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd) + Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI + Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET + Port ( CLK : in STD_LOGIC; -- Clock + RST : in STD_LOGIC; -- Reset + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur + IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2 + IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2 + IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2 + IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction de l'étage 2 + OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A de l'étage 2 + OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B de l'étage 2 + OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C de l'étage 2 + OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction de l'étage 2 + IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 5 + IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 5 + IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Entrée de l'instruction de l'étage 5 end Etage2_5_Registres; architecture Behavioral of Etage2_5_Registres is @@ -94,10 +84,14 @@ architecture Behavioral of Etage2_5_Registres is OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; - signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0"; - signal Entree_BancRegistre_DATA : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); - signal Sortie_BancRegistres_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); - signal Sortie_BancRegistres_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); + signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0"; -- Signal de sortie du LC + + signal Entree_BancRegistre_DATA : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Entrée DATA du banc de registre (B de l'étage 5 ou STD_IN) + + signal Sortie_BancRegistres_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Sortie du banc de registre a passer par le multiplexeur sur A + signal Sortie_BancRegistres_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Sortie du banc de registre a passer par le multiplexeur sur B + + -- Signaux internes signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); @@ -153,9 +147,11 @@ begin intern_OUT_2_C; OUT_2_Instruction <= (others => '0') when RST = '0' else IN_2_Instruction; - + + -- Gestion de STD_OU (peut être améliorée) process begin + -- Synchronisation sur la clock wait until CLK'event and CLK = '1'; if (RST = '0') then intern_STD_OUT <= (others => '0'); @@ -168,6 +164,9 @@ begin STD_OUT <= intern_STD_OUT when RST = '1' else (others => '0'); + + + -- Un multiplexeur pourrait être utilisé ici, mais cela n'a pas été jugé pertinent Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else STD_IN when IN_2_Instruction = Code_Instruction_GET else IN_5_B; diff --git a/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd b/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd index 40738b0..a399387 100644 --- a/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd +++ b/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd @@ -1,53 +1,45 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- --- Create Date: 18.04.2021 21:19:41 --- Design Name: --- Module Name: Etage3_Calcul - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: +-- Create Date: 18.04.2021 21:19:41 +-- Module Name: Etage3_Calcul - Structural +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- +-- Description: Etage 3 du processeur +-- - Gestion de l'ALU -- -- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- +-- - ALU +-- - LC +-- - MUX +-- +-- Additional Comments: Etage assynchrone ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity Etage3_Calcul is - Generic ( Nb_bits : Natural; - Instruction_bus_size : Natural; - Bits_Controle_LC : STD_LOGIC_VECTOR; - Bits_Controle_MUX : STD_LOGIC_VECTOR); - Port ( RST : in STD_LOGIC; - IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); - OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); - N : out STD_LOGIC; - O : out STD_LOGIC; - Z : out STD_LOGIC; - C : out STD_LOGIC); + Generic ( Nb_bits : Natural; -- Taille d'un mot binaire + Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) + Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd) + Bits_Controle_MUX : STD_LOGIC_VECTOR); -- Vecteur de bit controlant le multiplexeur (cf MUX.vhd) + Port ( RST : in STD_LOGIC; -- Reset + IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A + IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B + IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C + IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction + OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A + OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B + OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction + N : out STD_LOGIC; -- Flag Negative + O : out STD_LOGIC; -- Flag Overload + Z : out STD_LOGIC; -- Flag Zero + C : out STD_LOGIC);-- Flag Carry end Etage3_Calcul; architecture Structural of Etage3_Calcul is @@ -81,9 +73,14 @@ architecture Structural of Etage3_Calcul is OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; + -- Sortie du Link Controleur commandant l'ALU signal OP_ALU : STD_LOGIC_VECTOR (2 downto 0) := (others => '0'); + + -- Sortie de l'ALU, a passer au multiplexeur signal Sortie_ALU : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); + + -- signaux internes signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_N : STD_LOGIC := '0'; signal intern_O : STD_LOGIC := '0'; diff --git a/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd b/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd index 82deed6..93afac9 100644 --- a/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd +++ b/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd @@ -1,21 +1,22 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 18.04.2021 21:19:41 --- Design Name: --- Module Name: Etage4_Memoire - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: +-- Module Name: Etage4_Memoire - Structural +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- +-- Description: Etage 4 du processeur +-- - Gestion de la mémoire +-- - Gestion de la sauvegarde du contexte lors des appels de fonction -- -- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- +-- - MemoireDonnees +-- - MemoireAdressesRetour +-- - LC +-- - MUX ---------------------------------------------------------------------------------- @@ -23,36 +24,27 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values --- use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity Etage4_Memoire is - Generic ( Nb_bits : Natural; - Mem_size : Natural; - Adresse_mem_size : Natural; - Instruction_bus_size : Natural; - Mem_EBP_size : Natural; - Adresse_size_mem_EBP : Natural; - Bits_Controle_LC : STD_LOGIC_VECTOR; - Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; - Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; - Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; - Code_Instruction_CALL : STD_LOGIC_VECTOR; - Code_Instruction_RET : STD_LOGIC_VECTOR); - Port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; - IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); - OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); + Generic ( Nb_bits : Natural; -- Taille d'un mot binaire + Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables) + Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees + Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) + Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale) + Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte + Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd) + Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd) + Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd) + Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd) + Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL + Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET + Port ( CLK : in STD_LOGIC; -- Clock + RST : in STD_LOGIC; -- Reset + IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A + IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B + IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction + OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A + OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B + OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction end Etage4_Memoire; architecture Structural of Etage4_Memoire is @@ -100,14 +92,21 @@ architecture Structural of Etage4_Memoire is OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; - signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); - signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); - signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); - signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0"; - signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); - signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); - signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); - signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); + + signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- EBP (offset à ajouter à l'adresse) + signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Nouvelle valeur d'EBP, a stocker lors d'un CALL (Cf fonctionnement MemoireAdressesRetour.vhd) + + signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse entrante dans le composant de mémoire de donnees + signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Sortie du mux de choix d'adresse entre A et B + signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse avec EBP ajouté (IN_Addr_MemoireDonnees + BP) + + signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0"; -- Sortie du Link Controler, signal de commande de la mémoire + + signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Sortie de la mémoire (a multiplexer) + + signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Signal interne + + -- Signaux de la memoire de contexte signal R_Aux : STD_LOGIC := '0'; signal W_Aux : STD_LOGIC := '0'; signal E : STD_LOGIC; @@ -115,14 +114,14 @@ architecture Structural of Etage4_Memoire is begin - instance_LC : LC + instance_LC : LC -- Link controleur sur la mémoire de donnees generic map (Instruction_Vector_Size => Instruction_bus_size, Command_size => 1, Bits_Controle => Bits_Controle_LC) port map ( Instruction => IN_Instruction, Commande => Commande_MemoireDonnees); - instance_MUX_IN : MUX + instance_MUX_IN : MUX -- Multiplexeur selectionnant A ou B pour adresse generic map (Nb_bits => Adresse_mem_size, Instruction_Vector_Size => Instruction_bus_size, Bits_Controle => Bits_Controle_MUX_IN) @@ -131,7 +130,7 @@ begin IN2 => IN_B (Adresse_mem_size - 1 downto 0), OUTPUT => IN_Addr_MemoireDonnees); - instance_MUX_IN_EBP : MUX + instance_MUX_IN_EBP : MUX -- Multiplexeur selectionnant l'adresse plus EBP ou l'adresse de base generic map (Nb_bits => Adresse_mem_size, Instruction_Vector_Size => Instruction_bus_size, Bits_Controle => Bits_Controle_MUX_IN_EBP) @@ -140,7 +139,7 @@ begin IN2 => Addr_MemoireDonnees_EBP, OUTPUT => Addr_MemoireDonnees); - instance_MUX_OUT : MUX + instance_MUX_OUT : MUX -- Multiplexeur selectionnant la sortie de l'étage (sur B) generic map (Nb_bits => Nb_bits, Instruction_Vector_Size => Instruction_bus_size, Bits_Controle => Bits_Controle_MUX_OUT) @@ -182,7 +181,7 @@ begin OUT_Instruction <= (others => '0') when RST = '0' else IN_Instruction; - + -- Controle de la mémoire de contexte (ici aussi un LC aurait été disproportionné) R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else '0'; W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else diff --git a/Processeur.srcs/sources_1/new/LC.vhd b/Processeur.srcs/sources_1/new/LC.vhd index 3e38d64..48fcaf0 100644 --- a/Processeur.srcs/sources_1/new/LC.vhd +++ b/Processeur.srcs/sources_1/new/LC.vhd @@ -1,42 +1,39 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 17.04.2021 21:49:57 --- Design Name: -- Module Name: LC - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Link Controler -- +-- Dependencies: None +-- +-- Comments : +-- - Associe une commande a l'instruction courante +-- - A l'instruction i est renvoyé le ieme paquet de taille Command_size +-- +-- Exemple : +-- - Soit le vecteur de bits de controle "010010100111" avec command size a 3 +-- - Pour l'instruction 0 sera renvoyé "111" +-- - Pour l'instruction 1 sera renvoyé "100" +-- - Pour l'instruction 2 sera renvoyé "010" +-- - Pour l'instruction 3 sera renvoyé "010" ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity LC is - Generic (Instruction_Vector_Size : Natural; - Command_size : Natural; - Bits_Controle : STD_LOGIC_VECTOR); - Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0); - Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0)); + Generic (Instruction_Vector_Size : Natural; -- Nombres de bits nécessaires pour coder les instructions + Command_size : Natural; -- Nombre de bits de la commande en sortie + Bits_Controle : STD_LOGIC_VECTOR); -- Vecteur de bit contenant les commandes + Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0); -- Instrcution courante + Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0)); -- Sortie de la commande end LC; architecture Behavioral of LC is diff --git a/Processeur.srcs/sources_1/new/MUX.vhd b/Processeur.srcs/sources_1/new/MUX.vhd index 234e6c1..e6dfdf1 100644 --- a/Processeur.srcs/sources_1/new/MUX.vhd +++ b/Processeur.srcs/sources_1/new/MUX.vhd @@ -1,44 +1,36 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 17.04.2021 21:49:57 --- Design Name: -- Module Name: MUX - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Multiplexeur -- +-- Dependencies: None +-- +-- Comments : +-- - Le multiplexeur selectionne une des deux entrées qu'il repercute en sortie en fonction de l'instruction +-- - Les Bits_Controle definissent cette sélection : +-- Si Bits_Controle(Instruction) = '1' alors la première entrée est selectionnée +-- Sinon, la seconde ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity MUX is - Generic (Nb_bits : Natural; - Instruction_Vector_Size : Natural; - Bits_Controle : STD_LOGIC_VECTOR); - Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0); - IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); + Generic (Nb_bits : Natural; -- Taille d'un mot en entrée + Instruction_Vector_Size : Natural; -- Nombres de bits nécessaires pour coder les instructions + Bits_Controle : STD_LOGIC_VECTOR); -- Vecteur de bit controlant le multiplexeur + Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0); -- Instrcution courante + IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée 1 + IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée 2 + OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie end MUX; architecture Behavioral of MUX is diff --git a/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd b/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd index 8c5ce38..5565331 100644 --- a/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd +++ b/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd @@ -1,67 +1,65 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 16.04.2021 14:35:04 --- Design Name: -- Module Name: MemoireAdressesRetour - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Memoire des informations de controle (adresse de retour ou EBP) -- +-- Dependencies: None +-- +-- Comments : Cette mémoire fonctionne comme une pile. +-- - La valeur renvoyée est toujours celle du sommet (D_OUT = sommet de la pile). +-- - Lors d'une écriture, D_IN est empilé +-- - Lors d'une lecture, le sommet de la pile est pop +-- +-- Warning : +-- - On peut revoir le nom (lecture et ecriture) +-- - Flags E et F non fonctionnels ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity MemoireAdressesRetour is - Generic (Nb_bits : Natural; - Addr_size : Natural; - Mem_size : Natural); - Port ( R : in STD_LOGIC; - W : in STD_LOGIC; - D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - RST : in STD_LOGIC; - CLK : in STD_LOGIC; - D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); - E : out STD_LOGIC; - F : out STD_LOGIC); + Generic (Nb_bits : Natural; -- Taille d'un mot en memoire (taille d'une adresse de la memoire d'instruction ou d'un mot pour EBP) + Addr_size : Natural; -- Nombre de bits necessaires pour adresser la mémoire + Mem_size : Natural); -- Nombre d'éléments stockés en mémoire + Port ( R : in STD_LOGIC; -- Si R = 1 on pop le sommet + W : in STD_LOGIC; -- Si W = 1 on push D_IN + D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data entrante + RST : in STD_LOGIC; -- Reset + CLK : in STD_LOGIC; -- Clock + D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Sortie du composant (toujours la valeur au sommet) + E : out STD_LOGIC; -- Flag Empty + F : out STD_LOGIC);-- Flag Full end MemoireAdressesRetour; architecture Behavioral of MemoireAdressesRetour is - signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0'); - signal Addr : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0'); + signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0'); -- Buffer (mémoire) + signal Addr : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0'); -- Signal INTERNE, mémoire non adressable de l'extérieur. Pointe vers le sommet de pile constant EMPTY : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0'); constant FULL : STD_LOGIC_VECTOR (Addr_size downto 0) := (Addr_size => '1', others => '0'); begin process begin + -- Synchronisation wait until CLK'event and CLK = '1'; if (RST = '0' ) then MEMORY <= (others => '0'); Addr <= (others => '0'); else + -- Push if (W = '1') then MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN; Addr <= Addr + 1; + -- Pop elsif (R = '1') then Addr <= Addr - 1; end if; @@ -73,6 +71,7 @@ begin F <= '1' when Addr = FULL else '0'; + -- Sortie du sommet de pile (ou 0 si pile vide) D_OUT <= (others => '0') when Addr = EMPTY else MEMORY (to_integer(unsigned(Addr)) * Nb_bits - 1 downto Nb_bits * (to_integer(unsigned(Addr)) - 1)); end Behavioral; diff --git a/Processeur.srcs/sources_1/new/MemoireDonnees.vhd b/Processeur.srcs/sources_1/new/MemoireDonnees.vhd index cad7f8c..adf035d 100644 --- a/Processeur.srcs/sources_1/new/MemoireDonnees.vhd +++ b/Processeur.srcs/sources_1/new/MemoireDonnees.vhd @@ -1,50 +1,35 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 16.04.2021 14:35:04 --- Design Name: -- Module Name: MemoireDonnees - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Memoire des donnees utilisateur -- +-- Dependencies: None ---------------------------------------------------------------------------------- - library IEEE; use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity MemoireDonnees is - Generic (Nb_bits : Natural; - Addr_size : Natural; - Mem_size : Natural); - Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); - RW : in STD_LOGIC; - D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - RST : in STD_LOGIC; - CLK : in STD_LOGIC; - D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); + Generic (Nb_bits : Natural; -- Taille d'un mot en mémoire + Addr_size : Natural; -- Nombre de bits nécessaires a l'adressage de la mémoire + Mem_size : Natural); -- Nombre de mot stockables + Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir + RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write) + D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0) + RST : in STD_LOGIC; -- Reset + CLK : in STD_LOGIC; -- Clock + D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire end MemoireDonnees; architecture Behavioral of MemoireDonnees is - signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0'); + signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0'); -- Buffer pour la mémoire begin process begin @@ -58,5 +43,6 @@ begin end if; end process; + -- Lecture assynchrone et en permanence D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr))); end Behavioral; \ No newline at end of file diff --git a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd index 579a0ba..51b2216 100644 --- a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd +++ b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd @@ -1,46 +1,40 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 16.04.2021 14:35:04 --- Design Name: -- Module Name: MemoireInstructions - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- +-- Description: Memoire d'instruction +-- - Accessible en lecture uniquement -- +-- Dependencies: None +-- +-- Comments : Memoire circulaire, si l'adresse est utilisée modulo la taille de la mémoire ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity MemoireInstructions is - Generic (Nb_bits : Natural; - Addr_size : Natural; - Mem_size : Natural); - Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); - D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); + Generic (Nb_bits : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire) + Addr_size : Natural; -- Nombre de bits pour adresser la mémoire + Mem_size : Natural); -- Taille de la mémoire (nombre d'instructions stockées) + Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- Une adresse + D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- L'instruction presente a cette adresse end MemoireInstructions; architecture Behavioral of MemoireInstructions is - signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := 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+ -- Do not touch until (-- Skadoosh) + -- Do not add any Skadoosh + signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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+ -- Skadoosh begin D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr))); end Behavioral; + diff --git a/Processeur.srcs/sources_1/new/System.vhd b/Processeur.srcs/sources_1/new/System.vhd index 95d0b6a..c954a9b 100644 --- a/Processeur.srcs/sources_1/new/System.vhd +++ b/Processeur.srcs/sources_1/new/System.vhd @@ -1,36 +1,28 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INSA-Toulouse +-- Engineer: Paul Faure -- -- Create Date: 13.04.2021 10:19:15 --- Design Name: -- Module Name: System - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Environnement du processeur, mapping entre le processeur et la carte -- -- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- +-- - Clock_Divider +-- - Pipeline ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - +-- Lien avec le fichier de contraintes +-- Récupération des leds pour STD_OUT +-- Récupération des switchs pour STD_IN +-- Récupération d'un bouton pour RST +-- Récupération de la clock entity System is Port ( led : out STD_LOGIC_VECTOR (7 downto 0); sw : in STD_LOGIC_VECTOR (7 downto 0); @@ -61,19 +53,23 @@ architecture Structural of System is CLK_OUT : out STD_LOGIC); end component; + -- signaux auxiliaires signal my_RST : STD_LOGIC; signal my_CLK : STD_LOGIC; signal buff_CLK : STD_LOGIC; begin + -- Premier diviseur de clock clk_div : Clock_Divider port map (CLK_IN => CLK, CLK_OUT => buff_CLK); + -- Second diviseur de clock clk_div_2 : Clock_Divider port map (CLK_IN => buff_CLK, CLK_OUT => my_CLK); + -- Le processeur, augmentation de la taille de la mémoire d'instruction instance : Pipeline generic map (Addr_Memoire_Instruction_Size => 8, Memoire_Instruction_Size => 256) @@ -82,7 +78,8 @@ begin STD_IN => sw, STD_OUT => led); - my_RST <= '0' when btnC = '1' else - '1'; + -- Gestion du RST (inversion d'état) + my_RST <= '1' when btnC = '0' else + '0'; end Structural; diff --git a/Processeur.xpr b/Processeur.xpr index 20b417f..3662545 100644 --- a/Processeur.xpr +++ b/Processeur.xpr @@ -3,7 +3,7 @@ - +