Browse Source

Preparation merge

Paul Faure 2 years ago
parent
commit
cd30c90fc7

Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd → Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd View File

3
 -- Engineer: Paul Faure
3
 -- Engineer: Paul Faure
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 -- 
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 -- 
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 -- Create Date: 18.04.2021 21:19:41
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 -- Create Date: 18.04.2021 21:19:41
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+-- Module Name: Etage1_LectureInstruction_NS - Behavioral
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 -- Project Name: Processeur sécurisé
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 -- Project Name: Processeur sécurisé
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 -- Target Devices: Basys 3 ARTIX7
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 -- Target Devices: Basys 3 ARTIX7
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 -- Tool Versions: Vivado 2016.4
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 -- Tool Versions: Vivado 2016.4
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 use IEEE.NUMERIC_STD.ALL;
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 use IEEE.NUMERIC_STD.ALL;
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-entity Etage1_LectureInstruction is
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+entity Etage1_LectureInstruction_NS is
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     Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
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     Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
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              Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction
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              Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction
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              Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
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              Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
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            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
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            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
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            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
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            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
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            Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction
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            Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction
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-end Etage1_LectureInstruction;
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+end Etage1_LectureInstruction_NS;
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65
 
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-architecture Behavioral of Etage1_LectureInstruction is
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+architecture Behavioral of Etage1_LectureInstruction_NS is
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     component MemoireInstructions is
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     component MemoireInstructions is
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     Generic (Nb_bits : Natural;
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     Generic (Nb_bits : Natural;
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              Addr_size : Natural;
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              Addr_size : Natural;

Processeur.srcs/sources_1/new/Etage4_Memoire.vhd → Processeur.srcs/sources_1/new/Etage4_Memoire_NS.vhd View File

3
 -- Engineer: Paul Faure
3
 -- Engineer: Paul Faure
4
 -- 
4
 -- 
5
 -- Create Date: 18.04.2021 21:19:41
5
 -- Create Date: 18.04.2021 21:19:41
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+-- Module Name: Etage4_Memoire_NS - Structural
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 -- Project Name: Processeur sécurisé
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 -- Project Name: Processeur sécurisé
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 -- Target Devices: Basys 3 ARTIX7
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 -- Target Devices: Basys 3 ARTIX7
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 -- Tool Versions: Vivado 2016.4
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 -- Tool Versions: Vivado 2016.4
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 use IEEE.STD_LOGIC_1164.ALL;
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 use IEEE.STD_LOGIC_1164.ALL;
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 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-entity Etage4_Memoire is
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+entity Etage4_Memoire_NS is
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     Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
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     Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
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               Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
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               Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
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               Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
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               Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
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            OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
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            OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
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            OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
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            OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
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            OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
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            OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
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-end Etage4_Memoire;
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+end Etage4_Memoire_NS;
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-architecture Structural of Etage4_Memoire is
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+architecture Structural of Etage4_Memoire_NS is
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     component MemoireDonnees is
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     component MemoireDonnees is
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     Generic (Nb_bits : Natural;
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     Generic (Nb_bits : Natural;
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              Addr_size : Natural;
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              Addr_size : Natural;
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     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
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     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
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-end Structural;
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+end Structural;

+ 1
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
File diff suppressed because it is too large
View File


Processeur.srcs/sources_1/new/Pipeline.vhd → Processeur.srcs/sources_1/new/Pipeline_NS.vhd View File

4
 -- 
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 -- 
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 -- Create Date: 19.04.2021 16:57:41
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 -- Create Date: 19.04.2021 16:57:41
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 -- Design Name: 
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 -- Design Name: 
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+-- Module Name: Pipeline_NS - Behavioral
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 -- Project Name: 
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 -- Project Name: 
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 -- Target Devices: 
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 -- Target Devices: 
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 -- Tool Versions: 
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 -- Tool Versions: 
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 --library UNISIM;
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 --library UNISIM;
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 --use UNISIM.VComponents.all;
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 --use UNISIM.VComponents.all;
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-entity Pipeline is
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+entity Pipeline_NS is
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     Generic (Nb_bits : Natural := 8;
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     Generic (Nb_bits : Natural := 8;
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              Instruction_En_Memoire_Size : Natural := 29;
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              Instruction_En_Memoire_Size : Natural := 29;
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              Addr_Memoire_Instruction_Size : Natural := 3;
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              Addr_Memoire_Instruction_Size : Natural := 3;
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           RST : STD_LOGIC;
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           RST : STD_LOGIC;
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           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
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           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
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-end Pipeline;
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+end Pipeline_NS;
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-architecture Behavioral of Pipeline is
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+architecture Behavioral of Pipeline_NS is
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-    component Etage1_LectureInstruction is
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+    component Etage1_LectureInstruction_NS is
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     Generic (Instruction_size_in_memory : Natural;
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     Generic (Instruction_size_in_memory : Natural;
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              Addr_size_mem_instruction : Natural;
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              Addr_size_mem_instruction : Natural;
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              Mem_instruction_size : Natural;
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              Mem_instruction_size : Natural;
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            C : out STD_LOGIC);
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            C : out STD_LOGIC);
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     end component;
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     end component;
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-    component Etage4_Memoire is
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+    component Etage4_Memoire_NS is
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         Generic ( Nb_bits : Natural;
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         Generic ( Nb_bits : Natural;
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                   Mem_size : Natural;
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                   Mem_size : Natural;
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                   Adresse_mem_size : Natural;
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                   Adresse_mem_size : Natural;
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     constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
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     constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
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     constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
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     constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
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 begin
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 begin
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-    instance_Etage1 : Etage1_LectureInstruction
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+    instance_Etage1 : Etage1_LectureInstruction_NS
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     generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
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     generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
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                  Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
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                  Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
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                  Mem_instruction_size => Memoire_Instruction_Size,
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                  Mem_instruction_size => Memoire_Instruction_Size,
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                  C => C
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                  C => C
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     );
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     );
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-    instance_Etage4 : Etage4_Memoire
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+    instance_Etage4 : Etage4_Memoire_NS
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     generic map( Nb_bits => Nb_bits,
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     generic map( Nb_bits => Nb_bits,
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                  Mem_size => Memoire_Size,
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                  Mem_size => Memoire_Size,
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                  Adresse_mem_size => Adresse_mem_size,
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                  Adresse_mem_size => Adresse_mem_size,
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         Instruction_to_5 <= Instruction_from_4;
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         Instruction_to_5 <= Instruction_from_4;
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     end process;        
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     end process;        
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 end Behavioral;
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 end Behavioral;
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+

+ 2
- 2
Processeur.srcs/sources_1/new/System.vhd View File

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 end System;
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 end System;
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 architecture Structural of System is
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 architecture Structural of System is
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-    component Pipeline is
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+    component Pipeline_NS is
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     Generic (Nb_bits : Natural := 8;
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     Generic (Nb_bits : Natural := 8;
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              Instruction_En_Memoire_Size : Natural := 29;
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              Instruction_En_Memoire_Size : Natural := 29;
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              Addr_Memoire_Instruction_Size : Natural := 3;
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              Addr_Memoire_Instruction_Size : Natural := 3;
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               CLK_OUT => my_CLK);
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               CLK_OUT => my_CLK);
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     -- Le processeur, augmentation de la taille de la mémoire d'instruction
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     -- Le processeur, augmentation de la taille de la mémoire d'instruction
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-    instance : Pipeline
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+    instance : Pipeline_NS
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     generic map (Addr_Memoire_Instruction_Size => 8,
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     generic map (Addr_Memoire_Instruction_Size => 8,
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                  Memoire_Instruction_Size => 256)
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                  Memoire_Instruction_Size => 256)
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     port map (CLK => my_CLK,
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     port map (CLK => my_CLK,

+ 6
- 6
Processeur.xpr View File

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           <Attr Name="UsedIn" Val="simulation"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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         </FileInfo>
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       </File>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
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         <FileInfo>
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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         </FileInfo>
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       </File>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
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         <FileInfo>
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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         </FileInfo>
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       </File>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
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         <FileInfo>
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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         </FileInfo>
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       </File>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
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         <FileInfo>
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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         </FileInfo>
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       </File>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Pipeline_NS.vhd">
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         <FileInfo>
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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         </FileInfo>
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       </File>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
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         <FileInfo>
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
138
           <Attr Name="UsedIn" Val="synthesis"/>
139
           <Attr Name="UsedIn" Val="simulation"/>
139
           <Attr Name="UsedIn" Val="simulation"/>

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