diff --git a/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc b/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
index 27543c5..e901bdc 100644
--- a/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
+++ b/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
@@ -111,7 +111,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
 set_property PACKAGE_PIN U18 [get_ports btnC]
 set_property IOSTANDARD LVCMOS33 [get_ports btnC]
 #set_property PACKAGE_PIN T18 [get_ports btnU]
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
+#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
 set_property PACKAGE_PIN W19 [get_ports btnL]
 set_property IOSTANDARD LVCMOS33 [get_ports btnL]
 set_property PACKAGE_PIN T17 [get_ports btnR]
diff --git a/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd b/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
deleted file mode 100644
index 88d42fb..0000000
--- a/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 09.04.2021 22:51:31
--- Design Name: 
--- Module Name: test_Compteur - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity test_Compteur is
---  Port ( );
-end test_Compteur;
-
-architecture Behavioral of test_Compteur is
-    component Compteur is
-        Port ( CK : in STD_LOGIC;
-               RST : in STD_LOGIC;
-               SENS : in STD_LOGIC;
-               LOAD : in STD_LOGIC;
-               EN : in STD_LOGIC;
-               Din : in STD_LOGIC_VECTOR (7 downto 0);
-               Dout : out STD_LOGIC_VECTOR (7 downto 0));
-    end component;
-     
-    signal CK          
-begin
-
-
-end Behavioral;
diff --git a/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd b/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd
index eb8a5ce..938774b 100644
--- a/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd
+++ b/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd
@@ -43,7 +43,7 @@ entity Compteur is
 end Compteur;
 
 architecture Behavioral of Compteur is
-    signal aux: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
+    signal aux: STD_LOGIC_VECTOR (7 downto 0);
 begin
     Dout <= aux;
     process
diff --git a/Compteur8BitsBasys3.xpr b/Compteur8BitsBasys3.xpr
index 1fb19bf..aa65aac 100644
--- a/Compteur8BitsBasys3.xpr
+++ b/Compteur8BitsBasys3.xpr
@@ -60,13 +60,13 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
+      <File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
+      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -100,13 +100,6 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/sim_1/new/test_Compteur.vhd">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="System"/>
diff --git a/proj/GPIO.cache/wt/gui_resources.wdf b/proj/GPIO.cache/wt/gui_resources.wdf
new file mode 100644
index 0000000..8c78a4f
--- /dev/null
+++ b/proj/GPIO.cache/wt/gui_resources.wdf
@@ -0,0 +1,13 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f6f6b:36:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:35:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3133:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6f70656e5f68617264776172655f6d616e61676572:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f72756e5f62697467656e:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:706176696577735f70726f6a6563745f73756d6d617279:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:70726f6772616d64656275677461625f70726f6772616d5f646576696365:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:70726f6772616d667067616469616c6f675f70726f6772616d:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:31:00:00
+eof:87845066
diff --git a/proj/GPIO.cache/wt/java_command_handlers.wdf b/proj/GPIO.cache/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..018d823
--- /dev/null
+++ b/proj/GPIO.cache/wt/java_command_handlers.wdf
@@ -0,0 +1,9 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:31:00:00
+eof:1593923137
diff --git a/proj/GPIO.cache/wt/project.wpc b/proj/GPIO.cache/wt/project.wpc
new file mode 100644
index 0000000..3c63dc5
--- /dev/null
+++ b/proj/GPIO.cache/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+57656254616c6b5472616e736d697373696f6e417474656d70746564:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/proj/GPIO.cache/wt/synthesis.wdf b/proj/GPIO.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..6e0f843
--- /dev/null
+++ b/proj/GPIO.cache/wt/synthesis.wdf
@@ -0,0 +1,38 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613335746370673233362d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:4750494f5f64656d6f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:52756e74696d654f7074696d697a6564:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333473:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3639322e3635364d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3432342e3137364d42:00:00
+eof:1465870805
diff --git a/proj/GPIO.cache/wt/synthesis_details.wdf b/proj/GPIO.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000..78f8d66
--- /dev/null
+++ b/proj/GPIO.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/proj/GPIO.cache/wt/webtalk_pa.xml b/proj/GPIO.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000..0c5b6c8
--- /dev/null
+++ b/proj/GPIO.cache/wt/webtalk_pa.xml
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri Apr 09 23:28:53 2021">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="f5d1f37f0c514482aeb99b8a58e27639" type="ProjectID"/>
+<property name="ProjectIteration" value="3" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AutoConnectTarget" value="1" type="JavaHandler"/>
+<property name="LaunchProgramFpga" value="1" type="JavaHandler"/>
+<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
+<property name="RunBitgen" value="1" type="JavaHandler"/>
+<property name="RunImplementation" value="1" type="JavaHandler"/>
+<property name="RunSynthesis" value="1" type="JavaHandler"/>
+<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Resources Info">
+<property name="BaseDialog_OK" value="6" type="GuiResourceData"/>
+<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiResourceData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="13" type="GuiResourceData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="2" type="GuiResourceData"/>
+<property name="PACommandNames_AUTO_CONNECT_TARGET" value="1" type="GuiResourceData"/>
+<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="1" type="GuiResourceData"/>
+<property name="PACommandNames_RUN_BITGEN" value="1" type="GuiResourceData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiResourceData"/>
+<property name="ProgramDebugTab_PROGRAM_DEVICE" value="1" type="GuiResourceData"/>
+<property name="ProgramFpgaDialog_PROGRAM" value="1" type="GuiResourceData"/>
+<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiResourceData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="4" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="3" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/proj/GPIO.hw/GPIO.lpr b/proj/GPIO.hw/GPIO.lpr
new file mode 100644
index 0000000..8c04d07
--- /dev/null
+++ b/proj/GPIO.hw/GPIO.lpr
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0">
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/proj/GPIO.hw/hw_1/hw.xml b/proj/GPIO.hw/hw_1/hw.xml
new file mode 100644
index 0000000..fa93dd2
--- /dev/null
+++ b/proj/GPIO.hw/hw_1/hw.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
+
+<hwsession version="1" minor="2">
+  <device name="xc7a35t_0" gui_info=""/>
+  <ObjectList object_type="hw_device" gui_info="">
+    <Object name="xc7a35t_0" gui_info="">
+      <Properties Property="PROBES.FILE" value=""/>
+      <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/$_project_name__demo.bit"/>
+    </Object>
+  </ObjectList>
+  <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/proj/GPIO.runs/.jobs/vrs_config_1.xml b/proj/GPIO.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000..c5f28e1
--- /dev/null
+++ b/proj/GPIO.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+</Runs>
+
diff --git a/proj/GPIO.runs/.jobs/vrs_config_2.xml b/proj/GPIO.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000..9f3ec3f
--- /dev/null
+++ b/proj/GPIO.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+</Runs>
+
diff --git a/proj/GPIO.runs/.jobs/vrs_config_3.xml b/proj/GPIO.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000..8064f23
--- /dev/null
+++ b/proj/GPIO.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+</Runs>
+
diff --git a/proj/GPIO.runs/impl_1/.Vivado_Implementation.queue.rst b/proj/GPIO.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/impl_1/.init_design.begin.rst b/proj/GPIO.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000..5804455
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
+    </Process>
+</ProcessHandle>
diff --git a/proj/GPIO.runs/impl_1/.init_design.end.rst b/proj/GPIO.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/impl_1/.opt_design.begin.rst b/proj/GPIO.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000..5804455
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
+    </Process>
+</ProcessHandle>
diff --git a/proj/GPIO.runs/impl_1/.opt_design.end.rst b/proj/GPIO.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/impl_1/.place_design.begin.rst b/proj/GPIO.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000..5804455
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
+    </Process>
+</ProcessHandle>
diff --git a/proj/GPIO.runs/impl_1/.place_design.end.rst b/proj/GPIO.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/impl_1/.route_design.begin.rst b/proj/GPIO.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000..5804455
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
+    </Process>
+</ProcessHandle>
diff --git a/proj/GPIO.runs/impl_1/.route_design.end.rst b/proj/GPIO.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/impl_1/.vivado.begin.rst b/proj/GPIO.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000..236874a
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,10 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="2772">
+    </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="12740">
+    </Process>
+</ProcessHandle>
diff --git a/proj/GPIO.runs/impl_1/.vivado.end.rst b/proj/GPIO.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/impl_1/.write_bitstream.begin.rst b/proj/GPIO.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000..e2e5929
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="1988">
+    </Process>
+</ProcessHandle>
diff --git a/proj/GPIO.runs/impl_1/.write_bitstream.end.rst b/proj/GPIO.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo.bit b/proj/GPIO.runs/impl_1/GPIO_demo.bit
new file mode 100644
index 0000000..555927e
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo.bit differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo.tcl b/proj/GPIO.runs/impl_1/GPIO_demo.tcl
new file mode 100644
index 0000000..366fe82
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo.tcl
@@ -0,0 +1,67 @@
+proc start_step { step } {
+  set stopFile ".stop.rst"
+  if {[file isfile .stop.rst]} {
+    puts ""
+    puts "*** Halting run - EA reset detected ***"
+    puts ""
+    puts ""
+    return -code error
+  }
+  set beginFile ".$step.begin.rst"
+  set platform "$::tcl_platform(platform)"
+  set user "$::tcl_platform(user)"
+  set pid [pid]
+  set host ""
+  if { [string equal $platform unix] } {
+    if { [info exist ::env(HOSTNAME)] } {
+      set host $::env(HOSTNAME)
+    }
+  } else {
+    if { [info exist ::env(COMPUTERNAME)] } {
+      set host $::env(COMPUTERNAME)
+    }
+  }
+  set ch [open $beginFile w]
+  puts $ch "<?xml version=\"1.0\"?>"
+  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+  puts $ch "    </Process>"
+  puts $ch "</ProcessHandle>"
+  close $ch
+}
+
+proc end_step { step } {
+  set endFile ".$step.end.rst"
+  set ch [open $endFile w]
+  close $ch
+}
+
+proc step_failed { step } {
+  set endFile ".$step.error.rst"
+  set ch [open $endFile w]
+  close $ch
+}
+
+set_msg_config -id {HDL 9-1061} -limit 100000
+set_msg_config -id {HDL 9-1654} -limit 100000
+
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+  create_msg_db write_bitstream.pb
+  open_checkpoint GPIO_demo_routed.dcp
+  set_property webtalk.parent_dir C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.cache/wt [current_project]
+  catch { write_mem_info -force GPIO_demo.mmi }
+  write_bitstream -force -no_partial_bitfile GPIO_demo.bit 
+  catch { write_sysdef -hwdef GPIO_demo.hwdef -bitfile GPIO_demo.bit -meminfo GPIO_demo.mmi -file GPIO_demo.sysdef }
+  catch {write_debug_probes -quiet -force debug_nets}
+  close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+  step_failed write_bitstream
+  return -code error $RESULT
+} else {
+  end_step write_bitstream
+  unset ACTIVE_STEP 
+}
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo.vdi b/proj/GPIO.runs/impl_1/GPIO_demo.vdi
new file mode 100644
index 0000000..a7d164d
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo.vdi
@@ -0,0 +1,475 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Fri Apr 09 23:15:32 2021
+# Process ID: 960
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
+# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
+#-----------------------------------------------------------
+source GPIO_demo.tcl -notrace
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2016.4
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
+INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
+Command: opt_design -directive RuntimeOptimized
+INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
+
+Starting Logic Optimization Task
+Implement Debug Cores | Checksum: 11fc7498c
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-2] Deriving generated clocks
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 16f269fca
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-10] Eliminated 6 cells.
+Phase 2 Constant propagation | Checksum: 233a26f9e
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 3 Sweep
+INFO: [Opt 31-12] Eliminated 363 unconnected nets.
+INFO: [Opt 31-11] Eliminated 2 unconnected cells.
+Phase 3 Sweep | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 4 BUFG optimization
+INFO: [Opt 31-12] Eliminated 0 unconnected nets.
+INFO: [Opt 31-11] Eliminated 0 unconnected cells.
+Phase 4 BUFG optimization | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+INFO: [Common 17-83] Releasing license: Implementation
+24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
+INFO: [Chipscope 16-241] No debug cores found in the current design.
+Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
+or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
+Command: place_design -directive RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
+
+Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 1.2 Build Placer Netlist Model
+Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 1.3 Constrain Clocks/Macros
+Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 1 Placer Initialization | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 2 Global Placement
+Phase 2 Global Placement | Checksum: 7e244a0f
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.5 Timing Path Optimizer
+Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 3 Detail Placement | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
+Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.3 Placer Reporting
+Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.4 Final Placement Cleanup
+Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Ending Placer Task | Checksum: dd20239e
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
+INFO: [Common 17-83] Releasing license: Implementation
+41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
+report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
+Command: route_design -directive RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
+
+Phase 1 Build RT Design
+Phase 1 Build RT Design | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2 Router Initialization
+
+Phase 2.1 Create Timer
+Phase 2.1 Create Timer | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2.2 Fix Topology Constraints
+Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2.3 Pre Route Cleanup
+Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+ Number of Nodes with overlaps = 0
+
+Phase 2.4 Update Timing
+Phase 2.4 Update Timing | Checksum: 111c71c3e
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
+
+Phase 2 Router Initialization | Checksum: 1ee683561
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 3 Initial Routing
+Phase 3 Initial Routing | Checksum: 10e02a291
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 107
+ Number of Nodes with overlaps = 0
+
+Phase 4.1.1 Update Timing
+Phase 4.1.1 Update Timing | Checksum: da308246
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 4.2 Global Iteration 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+
+Phase 4.2.1 Update Timing
+Phase 4.2.1 Update Timing | Checksum: 1185cfc05
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 16251cbd9
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
+
+Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 6 Post Hold Fix | Checksum: 12245b0d3
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.234075 %
+  Global Horizontal Routing Utilization  = 0.228267 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 7 Route finalize | Checksum: 1af3f3601
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1af3f3601
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 15d59118d
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: 15d59118d
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Fri Apr 09 23:19:20 2021
+# Process ID: 1988
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
+# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
+#-----------------------------------------------------------
+source GPIO_demo.tcl -notrace
+Command: open_checkpoint GPIO_demo_routed.dcp
+
+Starting open_checkpoint Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2016.4
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
+open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
+Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command write_bitstream
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado 12-3199] DRC finished with 0 Errors
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Bitstream compression saved 13383552 bits.
+Writing bitstream ./GPIO_demo.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
+INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
+INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_960.backup.vdi b/proj/GPIO.runs/impl_1/GPIO_demo_960.backup.vdi
new file mode 100644
index 0000000..93adc19
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_960.backup.vdi
@@ -0,0 +1,414 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Fri Apr 09 23:15:32 2021
+# Process ID: 960
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
+# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
+#-----------------------------------------------------------
+source GPIO_demo.tcl -notrace
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2016.4
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
+INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
+Command: opt_design -directive RuntimeOptimized
+INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
+
+Starting Logic Optimization Task
+Implement Debug Cores | Checksum: 11fc7498c
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-2] Deriving generated clocks
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 16f269fca
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-10] Eliminated 6 cells.
+Phase 2 Constant propagation | Checksum: 233a26f9e
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 3 Sweep
+INFO: [Opt 31-12] Eliminated 363 unconnected nets.
+INFO: [Opt 31-11] Eliminated 2 unconnected cells.
+Phase 3 Sweep | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 4 BUFG optimization
+INFO: [Opt 31-12] Eliminated 0 unconnected nets.
+INFO: [Opt 31-11] Eliminated 0 unconnected cells.
+Phase 4 BUFG optimization | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+INFO: [Common 17-83] Releasing license: Implementation
+24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
+INFO: [Chipscope 16-241] No debug cores found in the current design.
+Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
+or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
+Command: place_design -directive RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
+
+Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 1.2 Build Placer Netlist Model
+Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 1.3 Constrain Clocks/Macros
+Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 1 Placer Initialization | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 2 Global Placement
+Phase 2 Global Placement | Checksum: 7e244a0f
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.5 Timing Path Optimizer
+Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 3 Detail Placement | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
+Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.3 Placer Reporting
+Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.4 Final Placement Cleanup
+Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Ending Placer Task | Checksum: dd20239e
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
+INFO: [Common 17-83] Releasing license: Implementation
+41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
+report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
+Command: route_design -directive RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
+
+Phase 1 Build RT Design
+Phase 1 Build RT Design | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2 Router Initialization
+
+Phase 2.1 Create Timer
+Phase 2.1 Create Timer | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2.2 Fix Topology Constraints
+Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2.3 Pre Route Cleanup
+Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+ Number of Nodes with overlaps = 0
+
+Phase 2.4 Update Timing
+Phase 2.4 Update Timing | Checksum: 111c71c3e
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
+
+Phase 2 Router Initialization | Checksum: 1ee683561
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 3 Initial Routing
+Phase 3 Initial Routing | Checksum: 10e02a291
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 107
+ Number of Nodes with overlaps = 0
+
+Phase 4.1.1 Update Timing
+Phase 4.1.1 Update Timing | Checksum: da308246
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 4.2 Global Iteration 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+
+Phase 4.2.1 Update Timing
+Phase 4.2.1 Update Timing | Checksum: 1185cfc05
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 16251cbd9
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
+
+Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 6 Post Hold Fix | Checksum: 12245b0d3
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.234075 %
+  Global Horizontal Routing Utilization  = 0.228267 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 7 Route finalize | Checksum: 1af3f3601
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1af3f3601
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 15d59118d
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: 15d59118d
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_clock_utilization_routed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_clock_utilization_routed.rpt
new file mode 100644
index 0000000..4045340
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_clock_utilization_routed.rpt
@@ -0,0 +1,235 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:39 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_clock_utilization -file GPIO_demo_clock_utilization_routed.rpt
+| Design       : GPIO_demo
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.16 2016-11-09
+---------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Cell Type Counts per Global Clock: Region X0Y0
+7. Cell Type Counts per Global Clock: Region X1Y0
+8. Cell Type Counts per Global Clock: Region X0Y1
+9. Load Cell Placement Summary for Global Clock g0
+10. Load Cell Placement Summary for Global Clock g1
+11. Load Cell Placement Summary for Global Clock g2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type     | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL |    3 |        32 |   0 |            0 |      0 |
+| BUFH     |    0 |        72 |   0 |            0 |      0 |
+| BUFIO    |    0 |        20 |   0 |            0 |      0 |
+| BUFMR    |    0 |        10 |   0 |            0 |      0 |
+| BUFR     |    0 |        20 |   0 |            0 |      0 |
+| MMCM     |    1 |         5 |   0 |            0 |      0 |
+| PLL      |    0 |         5 |   0 |            0 |      0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock              | Driver Pin                                    | Net                                                    |
++-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
+| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |      |                   |                 2 |         336 |               0 |        9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1               |
+| g1        | src1      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |      |                   |                 2 |         243 |               0 |       10.000 | sys_clk_pin        | CLK_IBUF_BUFG_inst/O                          | CLK_IBUF_BUFG                                          |
+| g2        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y2 | n/a          |      |                   |                 1 |           1 |               0 |       10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/O    | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
++-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
+| Source Id | Global Id | Driver Type/Pin     | Constraint | Site            | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock       | Driver Pin                                             | Net                                                |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
+| src0      | g0        | MMCME2_ADV/CLKOUT0  | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |               9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0  | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |
+| src0      | g2        | MMCME2_ADV/CLKFBOUT | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |              10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |
+| src1      | g1        | IBUF/O              | IOB_X1Y26  | IOB_X1Y26       | X1Y0         |           1 |               0 |              10.000 | sys_clk_pin        | CLK_IBUF_inst/O                                        | CLK_IBUF                                           |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  484 |  1200 |  206 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   31 |  1500 |    2 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   63 |  1200 |   21 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1800 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |   950 |    0 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
++----+----+----+
+|    | X0 | X1 |
++----+----+----+
+| Y2 |  0 |  0 |
+| Y1 |  1 |  0 |
+| Y0 |  2 |  2 |
++----+----+----+
+
+
+6. Cell Type Counts per Global Clock: Region X0Y0
+-------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
+| g0        | n/a   | BUFG/O          | None       |         273 |               0 | 273 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
+| g1        | n/a   | BUFG/O          | None       |         211 |               0 | 211 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | CLK_IBUF_BUFG                            |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+7. Cell Type Counts per Global Clock: Region X1Y0
+-------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                                    |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
+| g1        | n/a   | BUFG/O          | None       |          32 |               0 | 31 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | CLK_IBUF_BUFG                                          |
+| g2        | n/a   | BUFG/O          | None       |           1 |               0 |  0 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+8. Cell Type Counts per Global Clock: Region X0Y1
+-------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
+| g0        | n/a   | BUFG/O          | None       |          63 |               0 | 63 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+9. Load Cell Placement Summary for Global Clock g0
+--------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                      |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
+| g0        | BUFG/O          | n/a               | clk_out1_clk_wiz_0 |       9.259 | {0.000 4.630} |          |         336 |        0 |              0 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+------+----+
+|    | X0   | X1 |
++----+------+----+
+| Y2 |    0 |  0 |
+| Y1 |   63 |  0 |
+| Y0 |  273 |  0 |
++----+------+----+
+
+
+10. Load Cell Placement Summary for Global Clock g1
+---------------------------------------------------
+
++-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net           |
++-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
+| g1        | BUFG/O          | n/a               | sys_clk_pin |      10.000 | {0.000 5.000} |          |         242 |        0 |              1 |        0 | CLK_IBUF_BUFG |
++-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+------+-----+
+|    | X0   | X1  |
++----+------+-----+
+| Y2 |    0 |   0 |
+| Y1 |    0 |   0 |
+| Y0 |  211 |  32 |
++----+------+-----+
+
+
+11. Load Cell Placement Summary for Global Clock g2
+---------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                                    |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
+| g2        | BUFG/O          | n/a               | clkfbout_clk_wiz_0 |      10.000 | {0.000 5.000} |          |           0 |        0 |              1 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+
+|    | X0 | X1 |
++----+----+----+
+| Y2 |  0 |  0 |
+| Y1 |  0 |  0 |
+| Y0 |  0 |  1 |
++----+----+----+
+
+
+
+# Location of BUFG Primitives 
+set_property LOC BUFGCTRL_X0Y2 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf]
+set_property LOC BUFGCTRL_X0Y0 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf]
+set_property LOC BUFGCTRL_X0Y1 [get_cells CLK_IBUF_BUFG_inst]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X1Y26 [get_ports CLK]
+
+# Clock net "Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1" driven by instance "Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf" located at site "BUFGCTRL_X0Y0"
+#startgroup
+create_pblock {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}
+add_cells_to_pblock [get_pblocks  {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1"}]]]
+resize_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
+#endgroup
+
+# Clock net "CLK_IBUF_BUFG" driven by instance "CLK_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1"
+#startgroup
+create_pblock {CLKAG_CLK_IBUF_BUFG}
+add_cells_to_pblock [get_pblocks  {CLKAG_CLK_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLK_IBUF_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
+#endgroup
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt
new file mode 100644
index 0000000..03050d5
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt
@@ -0,0 +1,104 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:08 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_control_sets -verbose -file GPIO_demo_control_sets_placed.rpt
+| Design       : GPIO_demo
+| Device       : xc7a35t
+--------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Flip-Flop Distribution
+3. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+|                          Status                          | Count |
++----------------------------------------------------------+-------+
+| Number of unique control sets                            |    36 |
+| Unused register locations in slices containing registers |    94 |
++----------------------------------------------------------+-------+
+
+
+2. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No           | No                    | No                     |             132 |           57 |
+| No           | No                    | Yes                    |               0 |            0 |
+| No           | Yes                   | No                     |             226 |           57 |
+| Yes          | No                    | No                     |             105 |           40 |
+| Yes          | No                    | Yes                    |               0 |            0 |
+| Yes          | Yes                   | No                     |             115 |           32 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+3. Detailed Control Set Information
+-----------------------------------
+
++-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
+|                Clock Signal               |                                Enable Signal                               |                              Set/Reset Signal                              | Slice Load Count | Bel Load Count |
++-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk_inter0                   |                1 |              4 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/data_inter0                  |                1 |              4 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_overflow_i_1_n_0                             |                                                                            |                2 |              4 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/shift_frame                  | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/reset_bit_count              |                1 |              4 |
+|  CLK_IBUF_BUFG                            | eqOp2_in                                                                   | tmrVal[3]_i_1_n_0                                                          |                2 |              4 |
+|  CLK_IBUF_BUFG                            |                                                                            | sendStr[3][0]                                                              |                1 |              5 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_1_n_0 |                2 |              7 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/g0_b0_n_0                                      |                                                                            |                2 |              7 |
+|  CLK_IBUF_BUFG                            | uartSend                                                                   |                                                                            |                2 |              7 |
+|  CLK_IBUF_BUFG                            | uartData                                                                   |                                                                            |                6 |              7 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/load_rx_data_reg_n_0         |                                                                            |                2 |              8 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_inc[7]_i_1_n_0                               |                                                                            |                3 |              8 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_inc[7]_i_1_n_0                               |                                                                            |                4 |              8 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_1_n_0             |                                                                            |                2 |             10 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_new_reg_n_0                                  |                                                                            |                3 |             11 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_1_n_0 |                3 |             11 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/eqOp4_in                                                     | Inst_vga_ctrl/v_cntr_reg0                                                  |                3 |             12 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/vga_red_reg[3]_i_1_n_0                                       |                2 |             12 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/eqOp4_in                                                     |                3 |             12 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_new_reg_n_0                                  |                                                                            |                4 |             12 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_1_n_0 |                4 |             14 |
+|  CLK_IBUF_BUFG                            |                                                                            | Inst_UART_TX_CTRL/bitTmr[0]_i_1_n_0                                        |                4 |             14 |
+|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[4][0]_i_1_n_0                              |                4 |             16 |
+|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[1][0]_i_1_n_0                              |                4 |             16 |
+|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[2][0]_i_1_n_0                              |                4 |             16 |
+|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[3][0]_i_1_n_0                              |                4 |             16 |
+|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[0][0]_i_1_n_0                              |                4 |             16 |
+|  CLK_IBUF_BUFG                            |                                                                            |                                                                            |               10 |             17 |
+|  CLK_IBUF_BUFG                            |                                                                            | reset_cntr0                                                                |                5 |             18 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/v_sync_reg                                                   |                                                                            |               10 |             23 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_timeout_cnt_reg_n_0                      |                7 |             24 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_periodic_check_cnt                       |                6 |             26 |
+|  CLK_IBUF_BUFG                            |                                                                            | tmrCntr0                                                                   |                7 |             27 |
+|  CLK_IBUF_BUFG                            | uartData                                                                   | strIndex0                                                                  |                8 |             31 |
+|  CLK_IBUF_BUFG                            | Inst_UART_TX_CTRL/txBit_i_1_n_0                                            | Inst_UART_TX_CTRL/READY                                                    |                9 |             32 |
+|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            |                                                                            |               47 |            115 |
++-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
+
+
++--------+-----------------------+
+| Fanout | Number of ControlSets |
++--------+-----------------------+
+| 4      |                     5 |
+| 5      |                     1 |
+| 7      |                     4 |
+| 8      |                     3 |
+| 10     |                     1 |
+| 11     |                     2 |
+| 12     |                     4 |
+| 14     |                     2 |
+| 16+    |                    14 |
++--------+-----------------------+
+
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt
new file mode 100644
index 0000000..3fb7206
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt
@@ -0,0 +1,35 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:01 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_drc -file GPIO_demo_drc_opted.rpt
+| Design       : GPIO_demo
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Synthesized
+------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 0
++------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++------+----------+-------------+------------+
++------+----------+-------------+------------+
+
+2. REPORT DETAILS
+-----------------
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.pb b/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.pb
new file mode 100644
index 0000000..8ebaa78
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.pb differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt
new file mode 100644
index 0000000..504505b
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt
@@ -0,0 +1,35 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:37 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_drc -file GPIO_demo_drc_routed.rpt -pb GPIO_demo_drc_routed.pb -rpx GPIO_demo_drc_routed.rpx
+| Design       : GPIO_demo
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 0
++------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++------+----------+-------------+------------+
++------+----------+-------------+------------+
+
+2. REPORT DETAILS
+-----------------
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpx b/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpx
new file mode 100644
index 0000000..0558da2
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpx differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_io_placed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_io_placed.rpt
new file mode 100644
index 0000000..0eebccc
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_io_placed.rpt
@@ -0,0 +1,277 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:08 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_io -file GPIO_demo_io_placed.rpt
+| Design       : GPIO_demo
+| Device       : xc7a35t
+| Speed File   : -1
+| Package      : cpg236
+------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+|            67 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
+| Pin Number | Signal Name  | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
+| A1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| A2         |              |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| A3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| A4         |              |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| A5         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| A6         |              |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| A7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| A8         |              |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| A9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| A10        |              |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| A11        |              | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| A12        |              | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| A13        |              | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| A14        |              | High Range | IO_L6P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| A15        |              | High Range | IO_L6N_T0_VREF_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| A16        |              | High Range | IO_L12P_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| A17        |              | High Range | IO_L12N_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| A18        | UART_TXD     | High Range | IO_L19N_T3_VREF_16           | OUTPUT        | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| A19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| B1         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| B2         |              |            | MGTPTXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| B3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| B4         |              |            | MGTPRXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| B5         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| B6         |              |            | MGTPRXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| B7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| B8         |              |            | MGTREFCLK0P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| B9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| B10        |              |            | MGTREFCLK1P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| B11        |              | Dedicated  | DXN_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| B12        |              | Dedicated  | VREFP_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| B13        |              | Dedicated  | VN_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| B14        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| B15        |              | High Range | IO_L11N_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| B16        |              | High Range | IO_L13N_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| B17        | PS2_DATA     | High Range | IO_L14N_T2_SRCC_16           | BIDIR         | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      | PULLUP    |          |      | NONE             |
+| B18        |              | High Range | IO_L19P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| B19        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| C1         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| C2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| C3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| C4         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| C5         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| C6         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| C7         |              |            | MGTRREF_216                  | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| C8         |              | Dedicated  | TCK_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| C9         |              | Dedicated  | VCCBATT_0                    | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| C10        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| C11        |              | Dedicated  | CCLK_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| C12        |              | Dedicated  | GNDADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| C13        |              | Dedicated  | VCCADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| C14        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| C15        |              | High Range | IO_L11P_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| C16        |              | High Range | IO_L13P_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
+| C17        | PS2_CLK      | High Range | IO_L14P_T2_SRCC_16           | BIDIR         | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      | PULLUP    |          |      | NONE             |
+| C18        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| C19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| D1         |              |            | MGTPTXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| D2         |              |            | MGTPTXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| D3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| D17        | VGA_GREEN[3] | High Range | IO_0_14                      | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| D18        |              | High Range | IO_L1P_T0_D00_MOSI_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| D19        |              | High Range | IO_L1N_T0_D01_DIN_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| E1         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| E2         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| E3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| E17        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| E18        |              | High Range | IO_L3P_T0_DQS_PUDC_B_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| E19        | LED[1]       | High Range | IO_L3N_T0_DQS_EMCCLK_14      | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| F1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| F2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| F3         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| F17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| F18        |              | High Range | IO_L2N_T0_D03_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| F19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| G1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| G2         |              | High Range | IO_L1N_T0_AD4N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| G3         |              | High Range | IO_L1P_T0_AD4P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| G7         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| G8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| G9         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| G10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| G11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| G12        |              | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| G13        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| G17        | VGA_GREEN[2] | High Range | IO_L5N_T0_D07_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| G18        |              | High Range | IO_L2P_T0_D02_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| G19        | VGA_RED[0]   | High Range | IO_L4N_T0_D05_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| H1         |              | High Range | IO_L3P_T0_DQS_AD5P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| H2         |              | High Range | IO_L2P_T0_AD12P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| H3         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| H7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| H8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| H9         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| H10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| H11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| H12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| H13        |              |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |
+| H17        | VGA_GREEN[1] | High Range | IO_L5P_T0_D06_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| H18        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| H19        | VGA_RED[1]   | High Range | IO_L4P_T0_D04_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| J1         |              | High Range | IO_L3N_T0_DQS_AD5N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| J2         |              | High Range | IO_L2N_T0_AD12N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| J3         |              | High Range | IO_L7P_T1_AD6P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| J7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| J8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| J9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| J10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| J11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| J12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| J13        |              |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |
+| J17        | VGA_GREEN[0] | High Range | IO_L7P_T1_D09_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| J18        | VGA_BLUE[3]  | High Range | IO_L7N_T1_D10_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| J19        | VGA_RED[2]   | High Range | IO_L6N_T0_D08_VREF_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| K1         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| K2         |              | High Range | IO_L5P_T0_AD13P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| K3         |              | High Range | IO_L7N_T1_AD6N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| K7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| K8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| K12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| K13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| K17        |              | High Range | IO_L12N_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| K18        | VGA_BLUE[2]  | High Range | IO_L8N_T1_D12_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| K19        |              | High Range | IO_L6P_T0_FCS_B_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| L1         | LED[15]      | High Range | IO_L6N_T0_VREF_35            | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| L2         |              | High Range | IO_L5N_T0_AD13N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| L3         |              | High Range | IO_L8P_T1_AD14P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| L7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| L8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| L9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| L10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| L11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| L12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| L13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| L17        |              | High Range | IO_L12P_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| L18        | VGA_BLUE[1]  | High Range | IO_L8P_T1_D11_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| L19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| M1         |              | High Range | IO_L9N_T1_DQS_AD7N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| M2         |              | High Range | IO_L9P_T1_DQS_AD7P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| M3         |              | High Range | IO_L8N_T1_AD14N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| M7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| M8         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| M9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| M10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| M11        |              |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| M12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| M13        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| M17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| M18        |              | High Range | IO_L11P_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| M19        |              | High Range | IO_L11N_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| N1         |              | High Range | IO_L10N_T1_AD15N_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| N2         |              | High Range | IO_L10P_T1_AD15P_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
+| N3         | LED[13]      | High Range | IO_L12P_T1_MRCC_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| N7         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| N8         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| N9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| N10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| N11        |              |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
+| N12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| N13        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| N17        |              | High Range | IO_L13P_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| N18        | VGA_BLUE[0]  | High Range | IO_L9P_T1_DQS_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| N19        | VGA_RED[3]   | High Range | IO_L9N_T1_DQS_D13_14         | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| P1         | LED[14]      | High Range | IO_L19N_T3_VREF_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| P2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| P3         | LED[12]      | High Range | IO_L12N_T1_MRCC_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| P17        |              | High Range | IO_L13N_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| P18        |              | High Range | IO_L14P_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| P19        | VGA_HS       | High Range | IO_L10P_T1_D14_14            | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| R1         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| R2         | SW[15]       | High Range | IO_L1P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| R3         | SW[11]       | High Range | IO_L2P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| R17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| R18        |              | High Range | IO_L14N_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
+| R19        | VGA_VS       | High Range | IO_L10N_T1_D15_14            | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| T1         | SW[14]       | High Range | IO_L3P_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| T2         | SW[10]       | High Range | IO_L1N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| T3         | SW[9]        | High Range | IO_L2N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| T17        | BTN[2]       | High Range | IO_L17P_T2_A14_D30_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| T18        | BTN[0]       | High Range | IO_L17N_T2_A13_D29_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| T19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| U1         | SW[13]       | High Range | IO_L3N_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| U2         | SSEG_AN[0]   | High Range | IO_L9N_T1_DQS_34             | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U3         | LED[11]      | High Range | IO_L9P_T1_DQS_34             | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U4         | SSEG_AN[1]   | High Range | IO_L11P_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U5         | SSEG_CA[4]   | High Range | IO_L16P_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U6         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| U7         | SSEG_CA[6]   | High Range | IO_L19P_T3_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U8         | SSEG_CA[2]   | High Range | IO_L14P_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| U10        |              | Dedicated  | M2_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| U11        |              | Dedicated  | INIT_B_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| U12        |              | Dedicated  | DONE_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| U13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| U14        | LED[6]       | High Range | IO_25_14                     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U15        | LED[5]       | High Range | IO_L23P_T3_A03_D19_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U16        | LED[0]       | High Range | IO_L23N_T3_A02_D18_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| U17        | BTN[3]       | High Range | IO_L18P_T2_A12_D28_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| U18        | BTN[4]       | High Range | IO_L18N_T2_A11_D27_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| U19        | LED[2]       | High Range | IO_L15P_T2_DQS_RDWR_B_14     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V1         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| V2         | SW[8]        | High Range | IO_L5P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| V3         | LED[9]       | High Range | IO_L6P_T0_34                 | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V4         | SSEG_AN[2]   | High Range | IO_L11N_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V5         | SSEG_CA[5]   | High Range | IO_L16N_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V6         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| V7         | SSEG_CA[7]   | High Range | IO_L19N_T3_VREF_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V8         | SSEG_CA[3]   | High Range | IO_L14N_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V9         |              | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| V10        |              | Dedicated  | PROGRAM_B_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| V11        |              | Dedicated  | CFGBVS_0                     | Config        |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
+| V12        |              | Dedicated  | M0_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| V13        | LED[8]       | High Range | IO_L24P_T3_A01_D17_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V14        | LED[7]       | High Range | IO_L24N_T3_A00_D16_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| V15        | SW[5]        | High Range | IO_L21P_T3_DQS_14            | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| V16        | SW[1]        | High Range | IO_L19P_T3_A10_D26_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| V17        | SW[0]        | High Range | IO_L19N_T3_A09_D25_VREF_14   | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| V18        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| V19        | LED[3]       | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| W1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| W2         | SW[12]       | High Range | IO_L5N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| W3         | LED[10]      | High Range | IO_L6N_T0_VREF_34            | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| W4         | SSEG_AN[3]   | High Range | IO_L12N_T1_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| W5         | CLK          | High Range | IO_L12P_T1_MRCC_34           | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| W6         | SSEG_CA[1]   | High Range | IO_L13N_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| W7         | SSEG_CA[0]   | High Range | IO_L13P_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| W8         |              | Dedicated  | TDO_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| W9         |              | Dedicated  | TMS_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| W10        |              | Dedicated  | TDI_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| W11        |              | Dedicated  | M1_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
+| W12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
+| W13        | SW[7]        | High Range | IO_L22P_T3_A05_D21_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| W14        | SW[6]        | High Range | IO_L22N_T3_A04_D20_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| W15        | SW[4]        | High Range | IO_L21N_T3_DQS_A06_D22_14    | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| W16        | SW[2]        | High Range | IO_L20P_T3_A08_D24_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| W17        | SW[3]        | High Range | IO_L20N_T3_A07_D23_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
+| W18        | LED[4]       | High Range | IO_L16P_T2_CSI_B_14          | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
+| W19        | BTN[1]       | High Range | IO_L16N_T2_A15_D31_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
+* Default value
+
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt
new file mode 100644
index 0000000..e54e19f
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt
@@ -0,0 +1,205 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:38 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_methodology -file GPIO_demo_methodology_drc_routed.rpt -rpx GPIO_demo_methodology_drc_routed.rpx
+| Design       : GPIO_demo
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Routed
+-------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+             Max violations: <unlimited>
+             Violations found: 34
++-----------+----------+-------------------------------+------------+
+| Rule      | Severity | Description                   | Violations |
++-----------+----------+-------------------------------+------------+
+| TIMING-18 | Warning  | Missing input or output delay | 34         |
++-----------+----------+-------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-18#1 Warning
+Missing input or output delay  
+An input delay is missing on BTN[0] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay  
+An input delay is missing on BTN[1] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay  
+An input delay is missing on BTN[2] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay  
+An input delay is missing on BTN[3] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay  
+An input delay is missing on BTN[4] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#6 Warning
+Missing input or output delay  
+An input delay is missing on PS2_CLK relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#7 Warning
+Missing input or output delay  
+An input delay is missing on PS2_DATA relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#8 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_AN[0] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#9 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_AN[1] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#10 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_AN[2] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#11 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_AN[3] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#12 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[0] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#13 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[1] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#14 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[2] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#15 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[3] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#16 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[4] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#17 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[5] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#18 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[6] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#19 Warning
+Missing input or output delay  
+An output delay is missing on SSEG_CA[7] relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#20 Warning
+Missing input or output delay  
+An output delay is missing on UART_TXD relative to clock(s) sys_clk_pin 
+Related violations: <none>
+
+TIMING-18#21 Warning
+Missing input or output delay  
+An output delay is missing on VGA_BLUE[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#22 Warning
+Missing input or output delay  
+An output delay is missing on VGA_BLUE[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#23 Warning
+Missing input or output delay  
+An output delay is missing on VGA_BLUE[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#24 Warning
+Missing input or output delay  
+An output delay is missing on VGA_BLUE[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#25 Warning
+Missing input or output delay  
+An output delay is missing on VGA_GREEN[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#26 Warning
+Missing input or output delay  
+An output delay is missing on VGA_GREEN[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#27 Warning
+Missing input or output delay  
+An output delay is missing on VGA_GREEN[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#28 Warning
+Missing input or output delay  
+An output delay is missing on VGA_GREEN[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#29 Warning
+Missing input or output delay  
+An output delay is missing on VGA_HS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#30 Warning
+Missing input or output delay  
+An output delay is missing on VGA_RED[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#31 Warning
+Missing input or output delay  
+An output delay is missing on VGA_RED[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#32 Warning
+Missing input or output delay  
+An output delay is missing on VGA_RED[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#33 Warning
+Missing input or output delay  
+An output delay is missing on VGA_RED[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+TIMING-18#34 Warning
+Missing input or output delay  
+An output delay is missing on VGA_VS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
+Related violations: <none>
+
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpx b/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpx
new file mode 100644
index 0000000..3f7d9b9
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpx differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp b/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp
new file mode 100644
index 0000000..8979558
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp b/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp
new file mode 100644
index 0000000..313f18e
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpt
new file mode 100644
index 0000000..195bf48
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpt
@@ -0,0 +1,157 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date             : Fri Apr 09 23:16:38 2021
+| Host             : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command          : report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
+| Design           : GPIO_demo
+| Device           : xc7a35tcpg236-1
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+-------+
+| Total On-Chip Power (W)  | 0.223 |
+| Dynamic (W)              | 0.151 |
+| Device Static (W)        | 0.072 |
+| Effective TJA (C/W)      | 5.0   |
+| Max Ambient (C)          | 83.9  |
+| Junction Temperature (C) | 26.1  |
+| Confidence Level         | Low   |
+| Setting File             | ---   |
+| Simulation Activity File | ---   |
+| Design Nets Matched      | NA    |
++--------------------------+-------+
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks         |     0.005 |        5 |       --- |             --- |
+| Slice Logic    |     0.003 |     1426 |       --- |             --- |
+|   LUT as Logic |     0.002 |      564 |     20800 |            2.71 |
+|   CARRY4       |    <0.001 |      132 |      8150 |            1.62 |
+|   Register     |    <0.001 |      578 |     41600 |            1.39 |
+|   F7/F8 Muxes  |    <0.001 |        3 |     32600 |           <0.01 |
+|   Others       |     0.000 |       18 |       --- |             --- |
+| Signals        |     0.002 |     1137 |       --- |             --- |
+| MMCM           |     0.123 |        1 |         5 |           20.00 |
+| I/O            |     0.018 |       67 |       106 |           63.21 |
+| Static Power   |     0.072 |          |           |                 |
+| Total          |     0.223 |          |           |                 |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
++-----------+-------------+-----------+-------------+------------+
+| Vccint    |       1.000 |     0.020 |       0.010 |      0.010 |
+| Vccaux    |       1.800 |     0.081 |       0.069 |      0.013 |
+| Vcco33    |       3.300 |     0.006 |       0.005 |      0.001 |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
+| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
+| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
++-----------+-------------+-----------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                       |                                                                                                            |
+| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
+| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models               | High       | Device models are Production                           |                                                                                                            |
+|                             |            |                                                        |                                                                                                            |
+| Overall confidence level    | Low        |                                                        |                                                                                                            |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C)      | 25.0                     |
+| ThetaJA (C/W)         | 5.0                      |
+| Airflow (LFM)         | 250                      |
+| Heat Sink             | medium (Medium Profile)  |
+| ThetaSA (C/W)         | 4.6                      |
+| Board Selection       | medium (10"x10")         |
+| # of Board Layers     | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0                     |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++--------------------+----------------------------------------------------+-----------------+
+| Clock              | Domain                                             | Constraint (ns) |
++--------------------+----------------------------------------------------+-----------------+
+| clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |             9.3 |
+| clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |            10.0 |
+| sys_clk_pin        | CLK                                                |            10.0 |
++--------------------+----------------------------------------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++-----------------------------+-----------+
+| Name                        | Power (W) |
++-----------------------------+-----------+
+| GPIO_demo                   |     0.151 |
+|   Inst_UART_TX_CTRL         |    <0.001 |
+|   Inst_btn_debounce         |    <0.001 |
+|   Inst_vga_ctrl             |     0.130 |
+|     Inst_MouseCtl           |     0.004 |
+|       Inst_Ps2Interface     |     0.001 |
+|         ps2_clk_IOBUF_inst  |     0.000 |
+|         ps2_data_IOBUF_inst |     0.000 |
+|     Inst_MouseDisplay       |    <0.001 |
+|     clk_wiz_0_inst          |     0.124 |
+|       U0                    |     0.124 |
++-----------------------------+-----------+
+
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpx b/proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpx
new file mode 100644
index 0000000..a304565
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpx differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_power_summary_routed.pb b/proj/GPIO.runs/impl_1/GPIO_demo_power_summary_routed.pb
new file mode 100644
index 0000000..672c450
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_power_summary_routed.pb differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_route_status.pb b/proj/GPIO.runs/impl_1/GPIO_demo_route_status.pb
new file mode 100644
index 0000000..9e6528f
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_route_status.pb differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_route_status.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_route_status.rpt
new file mode 100644
index 0000000..4e16d84
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :        1888 :
+       # of nets not needing routing.......... :         743 :
+           # of internally routed nets........ :         743 :
+       # of routable nets..................... :        1145 :
+           # of fully routed nets............. :        1145 :
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp b/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp
new file mode 100644
index 0000000..340e5f3
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpt
new file mode 100644
index 0000000..416ca9d
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpt
@@ -0,0 +1,2891 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:38 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_timing_summary -warn_on_violation -max_paths 10 -file GPIO_demo_timing_summary_routed.rpt -rpx GPIO_demo_timing_summary_routed.rpx
+| Design       : GPIO_demo
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.16 2016-11-09
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+  Enable Multi Corner Analysis               :  Yes
+  Enable Pessimism Removal                   :  Yes
+  Pessimism Removal Resolution               :  Nearest Common Node
+  Enable Input Delay Default Clock           :  No
+  Enable Preset / Clear Arcs                 :  No
+  Disable Flight Delays                      :  No
+  Ignore I/O Paths                           :  No
+  Timing Early Launch at Borrowing Latches   :  false
+
+  Corner  Analyze    Analyze    
+  Name    Max Paths  Min Paths  
+  ------  ---------  ---------  
+  Slow    Yes        Yes        
+  Fast    Yes        Yes        
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock
+2. checking constant_clock
+3. checking pulse_width_clock
+4. checking unconstrained_internal_endpoints
+5. checking no_input_delay
+6. checking no_output_delay
+7. checking multiple_clock
+8. checking generated_clocks
+9. checking loops
+10. checking partial_input_delay
+11. checking partial_output_delay
+12. checking latch_loops
+
+1. checking no_clock
+--------------------
+ There are 0 register/latch pins with no clock.
+
+
+2. checking constant_clock
+--------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock
+-----------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints
+--------------------------------------------
+ There are 0 pins that are not constrained for maximum delay.
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay
+--------------------------
+ There are 7 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay
+---------------------------
+ There are 29 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock
+--------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks
+----------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops
+-----------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay
+--------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay
+---------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops
+------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+      3.744        0.000                      0                 1137        0.064        0.000                      0                 1137        3.000        0.000                       0                   585  
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock                 Waveform(ns)         Period(ns)      Frequency(MHz)
+-----                 ------------         ----------      --------------
+sys_clk_pin           {0.000 5.000}        10.000          100.000         
+  clk_out1_clk_wiz_0  {0.000 4.630}        9.259           108.000         
+  clkfbout_clk_wiz_0  {0.000 5.000}        10.000          100.000         
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock                     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+-----                     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+sys_clk_pin                 4.802        0.000                      0                  534        0.183        0.000                      0                  534        3.000        0.000                       0                   244  
+  clk_out1_clk_wiz_0        3.744        0.000                      0                  603        0.064        0.000                      0                  603        4.130        0.000                       0                   338  
+  clkfbout_clk_wiz_0                                                                                                                                                    7.845        0.000                       0                     3  
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  sys_clk_pin
+  To Clock:  sys_clk_pin
+
+Setup :            0  Failing Endpoints,  Worst Slack        4.802ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.183ns,  Total Violation        0.000ns
+PW    :            0  Failing Endpoints,  Worst Slack        3.000ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             4.802ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[0]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.711ns  (logic 0.952ns (20.210%)  route 3.759ns (79.790%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.023ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.850ns = ( 14.850 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.867     9.858    tmrCntr0
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[0]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.509    14.850    CLK_IBUF_BUFG
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[0]/C
+                         clock pessimism              0.274    15.124    
+                         clock uncertainty           -0.035    15.089    
+    SLICE_X62Y18         FDRE (Setup_fdre_C_R)       -0.429    14.660    tmrCntr_reg[0]
+  -------------------------------------------------------------------
+                         required time                         14.660    
+                         arrival time                          -9.858    
+  -------------------------------------------------------------------
+                         slack                                  4.802    
+
+Slack (MET) :             4.802ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[1]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.711ns  (logic 0.952ns (20.210%)  route 3.759ns (79.790%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.023ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.850ns = ( 14.850 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.867     9.858    tmrCntr0
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[1]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.509    14.850    CLK_IBUF_BUFG
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[1]/C
+                         clock pessimism              0.274    15.124    
+                         clock uncertainty           -0.035    15.089    
+    SLICE_X62Y18         FDRE (Setup_fdre_C_R)       -0.429    14.660    tmrCntr_reg[1]
+  -------------------------------------------------------------------
+                         required time                         14.660    
+                         arrival time                          -9.858    
+  -------------------------------------------------------------------
+                         slack                                  4.802    
+
+Slack (MET) :             4.802ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[2]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.711ns  (logic 0.952ns (20.210%)  route 3.759ns (79.790%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.023ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.850ns = ( 14.850 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.867     9.858    tmrCntr0
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[2]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.509    14.850    CLK_IBUF_BUFG
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[2]/C
+                         clock pessimism              0.274    15.124    
+                         clock uncertainty           -0.035    15.089    
+    SLICE_X62Y18         FDRE (Setup_fdre_C_R)       -0.429    14.660    tmrCntr_reg[2]
+  -------------------------------------------------------------------
+                         required time                         14.660    
+                         arrival time                          -9.858    
+  -------------------------------------------------------------------
+                         slack                                  4.802    
+
+Slack (MET) :             4.802ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[3]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.711ns  (logic 0.952ns (20.210%)  route 3.759ns (79.790%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.023ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.850ns = ( 14.850 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.867     9.858    tmrCntr0
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[3]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.509    14.850    CLK_IBUF_BUFG
+    SLICE_X62Y18         FDRE                                         r  tmrCntr_reg[3]/C
+                         clock pessimism              0.274    15.124    
+                         clock uncertainty           -0.035    15.089    
+    SLICE_X62Y18         FDRE (Setup_fdre_C_R)       -0.429    14.660    tmrCntr_reg[3]
+  -------------------------------------------------------------------
+                         required time                         14.660    
+                         arrival time                          -9.858    
+  -------------------------------------------------------------------
+                         slack                                  4.802    
+
+Slack (MET) :             4.965ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[4]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.571ns  (logic 0.952ns (20.828%)  route 3.619ns (79.172%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.727     9.718    tmrCntr0
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[4]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.508    14.849    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[4]/C
+                         clock pessimism              0.298    15.147    
+                         clock uncertainty           -0.035    15.112    
+    SLICE_X62Y19         FDRE (Setup_fdre_C_R)       -0.429    14.683    tmrCntr_reg[4]
+  -------------------------------------------------------------------
+                         required time                         14.683    
+                         arrival time                          -9.718    
+  -------------------------------------------------------------------
+                         slack                                  4.965    
+
+Slack (MET) :             4.965ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[5]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.571ns  (logic 0.952ns (20.828%)  route 3.619ns (79.172%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.727     9.718    tmrCntr0
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[5]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.508    14.849    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[5]/C
+                         clock pessimism              0.298    15.147    
+                         clock uncertainty           -0.035    15.112    
+    SLICE_X62Y19         FDRE (Setup_fdre_C_R)       -0.429    14.683    tmrCntr_reg[5]
+  -------------------------------------------------------------------
+                         required time                         14.683    
+                         arrival time                          -9.718    
+  -------------------------------------------------------------------
+                         slack                                  4.965    
+
+Slack (MET) :             4.965ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[6]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.571ns  (logic 0.952ns (20.828%)  route 3.619ns (79.172%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.727     9.718    tmrCntr0
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[6]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.508    14.849    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[6]/C
+                         clock pessimism              0.298    15.147    
+                         clock uncertainty           -0.035    15.112    
+    SLICE_X62Y19         FDRE (Setup_fdre_C_R)       -0.429    14.683    tmrCntr_reg[6]
+  -------------------------------------------------------------------
+                         required time                         14.683    
+                         arrival time                          -9.718    
+  -------------------------------------------------------------------
+                         slack                                  4.965    
+
+Slack (MET) :             4.965ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[7]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.571ns  (logic 0.952ns (20.828%)  route 3.619ns (79.172%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.727     9.718    tmrCntr0
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.508    14.849    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+                         clock pessimism              0.298    15.147    
+                         clock uncertainty           -0.035    15.112    
+    SLICE_X62Y19         FDRE (Setup_fdre_C_R)       -0.429    14.683    tmrCntr_reg[7]
+  -------------------------------------------------------------------
+                         required time                         14.683    
+                         arrival time                          -9.718    
+  -------------------------------------------------------------------
+                         slack                                  4.965    
+
+Slack (MET) :             4.994ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[24]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.511ns  (logic 0.952ns (21.102%)  route 3.559ns (78.898%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.843ns = ( 14.843 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.668     9.659    tmrCntr0
+    SLICE_X62Y24         FDRE                                         r  tmrCntr_reg[24]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.502    14.843    CLK_IBUF_BUFG
+    SLICE_X62Y24         FDRE                                         r  tmrCntr_reg[24]/C
+                         clock pessimism              0.274    15.117    
+                         clock uncertainty           -0.035    15.082    
+    SLICE_X62Y24         FDRE (Setup_fdre_C_R)       -0.429    14.653    tmrCntr_reg[24]
+  -------------------------------------------------------------------
+                         required time                         14.653    
+                         arrival time                          -9.659    
+  -------------------------------------------------------------------
+                         slack                                  4.994    
+
+Slack (MET) :             4.994ns  (required time - arrival time)
+  Source:                 tmrCntr_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            tmrCntr_reg[25]/R
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        4.511ns  (logic 0.952ns (21.102%)  route 3.559ns (78.898%))
+  Logic Levels:           4  (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.843ns = ( 14.843 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.147ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.626     5.147    CLK_IBUF_BUFG
+    SLICE_X62Y19         FDRE                                         r  tmrCntr_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X62Y19         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  tmrCntr_reg[7]/Q
+                         net (fo=2, routed)           0.812     6.415    tmrCntr_reg[7]
+    SLICE_X63Y20         LUT4 (Prop_lut4_I1_O)        0.124     6.539 r  tmrVal[3]_i_7/O
+                         net (fo=1, routed)           0.403     6.942    tmrVal[3]_i_7_n_0
+    SLICE_X63Y22         LUT5 (Prop_lut5_I4_O)        0.124     7.066 r  tmrVal[3]_i_4/O
+                         net (fo=1, routed)           0.941     8.007    tmrVal[3]_i_4_n_0
+    SLICE_X63Y19         LUT6 (Prop_lut6_I0_O)        0.124     8.131 r  tmrVal[3]_i_2/O
+                         net (fo=6, routed)           0.736     8.867    eqOp2_in
+    SLICE_X63Y21         LUT2 (Prop_lut2_I1_O)        0.124     8.991 r  tmrCntr[0]_i_1/O
+                         net (fo=27, routed)          0.668     9.659    tmrCntr0
+    SLICE_X62Y24         FDRE                                         r  tmrCntr_reg[25]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  CLK (IN)
+                         net (fo=0)                   0.000    10.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    13.341 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.502    14.843    CLK_IBUF_BUFG
+    SLICE_X62Y24         FDRE                                         r  tmrCntr_reg[25]/C
+                         clock pessimism              0.274    15.117    
+                         clock uncertainty           -0.035    15.082    
+    SLICE_X62Y24         FDRE (Setup_fdre_C_R)       -0.429    14.653    tmrCntr_reg[25]
+  -------------------------------------------------------------------
+                         required time                         14.653    
+                         arrival time                          -9.659    
+  -------------------------------------------------------------------
+                         slack                                  4.994    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.183ns  (arrival time - required time)
+  Source:                 Inst_UART_TX_CTRL/bitIndex_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_UART_TX_CTRL/txBit_reg/D
+                            (rising edge-triggered cell FDSE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.319ns  (logic 0.186ns (58.233%)  route 0.133ns (41.767%))
+  Logic Levels:           1  (LUT6=1)
+  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.962ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.498ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.565     1.448    Inst_UART_TX_CTRL/CLK
+    SLICE_X9Y8           FDRE                                         r  Inst_UART_TX_CTRL/bitIndex_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X9Y8           FDRE (Prop_fdre_C_Q)         0.141     1.589 r  Inst_UART_TX_CTRL/bitIndex_reg[2]/Q
+                         net (fo=3, routed)           0.133     1.723    Inst_UART_TX_CTRL/bitIndex_reg[2]
+    SLICE_X8Y9           LUT6 (Prop_lut6_I4_O)        0.045     1.768 r  Inst_UART_TX_CTRL/txBit_i_2/O
+                         net (fo=1, routed)           0.000     1.768    Inst_UART_TX_CTRL/txBit_i_2_n_0
+    SLICE_X8Y9           FDSE                                         r  Inst_UART_TX_CTRL/txBit_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.835     1.962    Inst_UART_TX_CTRL/CLK
+    SLICE_X8Y9           FDSE                                         r  Inst_UART_TX_CTRL/txBit_reg/C
+                         clock pessimism             -0.498     1.464    
+    SLICE_X8Y9           FDSE (Hold_fdse_C_D)         0.120     1.584    Inst_UART_TX_CTRL/txBit_reg
+  -------------------------------------------------------------------
+                         required time                         -1.584    
+                         arrival time                           1.768    
+  -------------------------------------------------------------------
+                         slack                                  0.183    
+
+Slack (MET) :             0.197ns  (arrival time - required time)
+  Source:                 uartData_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_UART_TX_CTRL/txData_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.276ns  (logic 0.164ns (59.419%)  route 0.112ns (40.581%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.962ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.498ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.565     1.448    CLK_IBUF_BUFG
+    SLICE_X8Y7           FDRE                                         r  uartData_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X8Y7           FDRE (Prop_fdre_C_Q)         0.164     1.612 r  uartData_reg[3]/Q
+                         net (fo=1, routed)           0.112     1.724    Inst_UART_TX_CTRL/DATA[3]
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.835     1.962    Inst_UART_TX_CTRL/CLK
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[4]/C
+                         clock pessimism             -0.498     1.464    
+    SLICE_X8Y8           FDRE (Hold_fdre_C_D)         0.063     1.527    Inst_UART_TX_CTRL/txData_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -1.527    
+                         arrival time                           1.724    
+  -------------------------------------------------------------------
+                         slack                                  0.197    
+
+Slack (MET) :             0.207ns  (arrival time - required time)
+  Source:                 Inst_btn_debounce/sig_out_reg_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btnReg_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.273ns  (logic 0.141ns (51.608%)  route 0.132ns (48.392%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.955ns
+    Source Clock Delay      (SCD):    1.443ns
+    Clock Pessimism Removal (CPR):    0.498ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.560     1.443    Inst_btn_debounce/CLK_I
+    SLICE_X13Y17         FDRE                                         r  Inst_btn_debounce/sig_out_reg_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X13Y17         FDRE (Prop_fdre_C_Q)         0.141     1.584 r  Inst_btn_debounce/sig_out_reg_reg[1]/Q
+                         net (fo=5, routed)           0.132     1.716    btnDeBnc[1]
+    SLICE_X14Y17         FDRE                                         r  btnReg_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.828     1.955    CLK_IBUF_BUFG
+    SLICE_X14Y17         FDRE                                         r  btnReg_reg[1]/C
+                         clock pessimism             -0.498     1.457    
+    SLICE_X14Y17         FDRE (Hold_fdre_C_D)         0.052     1.509    btnReg_reg[1]
+  -------------------------------------------------------------------
+                         required time                         -1.509    
+                         arrival time                           1.716    
+  -------------------------------------------------------------------
+                         slack                                  0.207    
+
+Slack (MET) :             0.221ns  (arrival time - required time)
+  Source:                 Inst_btn_debounce/sig_out_reg_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_btn_debounce/sig_out_reg_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.312ns  (logic 0.186ns (59.538%)  route 0.126ns (40.462%))
+  Logic Levels:           1  (LUT5=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.957ns
+    Source Clock Delay      (SCD):    1.445ns
+    Clock Pessimism Removal (CPR):    0.512ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.562     1.445    Inst_btn_debounce/CLK_I
+    SLICE_X11Y15         FDRE                                         r  Inst_btn_debounce/sig_out_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X11Y15         FDRE (Prop_fdre_C_Q)         0.141     1.586 r  Inst_btn_debounce/sig_out_reg_reg[3]/Q
+                         net (fo=5, routed)           0.126     1.713    Inst_btn_debounce/SIGNAL_O[3]
+    SLICE_X11Y15         LUT5 (Prop_lut5_I4_O)        0.045     1.758 r  Inst_btn_debounce/sig_out_reg[3]_i_1/O
+                         net (fo=1, routed)           0.000     1.758    Inst_btn_debounce/sig_out_reg[3]_i_1_n_0
+    SLICE_X11Y15         FDRE                                         r  Inst_btn_debounce/sig_out_reg_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.830     1.957    Inst_btn_debounce/CLK_I
+    SLICE_X11Y15         FDRE                                         r  Inst_btn_debounce/sig_out_reg_reg[3]/C
+                         clock pessimism             -0.512     1.445    
+    SLICE_X11Y15         FDRE (Hold_fdre_C_D)         0.091     1.536    Inst_btn_debounce/sig_out_reg_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -1.536    
+                         arrival time                           1.758    
+  -------------------------------------------------------------------
+                         slack                                  0.221    
+
+Slack (MET) :             0.223ns  (arrival time - required time)
+  Source:                 uartData_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_UART_TX_CTRL/txData_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.318ns  (logic 0.141ns (44.389%)  route 0.177ns (55.611%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.035ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.962ns
+    Source Clock Delay      (SCD):    1.449ns
+    Clock Pessimism Removal (CPR):    0.478ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.566     1.449    CLK_IBUF_BUFG
+    SLICE_X11Y6          FDRE                                         r  uartData_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X11Y6          FDRE (Prop_fdre_C_Q)         0.141     1.590 r  uartData_reg[5]/Q
+                         net (fo=1, routed)           0.177     1.767    Inst_UART_TX_CTRL/DATA[5]
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.835     1.962    Inst_UART_TX_CTRL/CLK
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[6]/C
+                         clock pessimism             -0.478     1.484    
+    SLICE_X8Y8           FDRE (Hold_fdre_C_D)         0.060     1.544    Inst_UART_TX_CTRL/txData_reg[6]
+  -------------------------------------------------------------------
+                         required time                         -1.544    
+                         arrival time                           1.767    
+  -------------------------------------------------------------------
+                         slack                                  0.223    
+
+Slack (MET) :             0.235ns  (arrival time - required time)
+  Source:                 Inst_btn_debounce/sig_out_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            uartState_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.343ns  (logic 0.209ns (60.852%)  route 0.134ns (39.148%))
+  Logic Levels:           1  (LUT6=1)
+  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.961ns
+    Source Clock Delay      (SCD):    1.447ns
+    Clock Pessimism Removal (CPR):    0.498ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.564     1.447    Inst_btn_debounce/CLK_I
+    SLICE_X14Y11         FDRE                                         r  Inst_btn_debounce/sig_out_reg_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X14Y11         FDRE (Prop_fdre_C_Q)         0.164     1.611 f  Inst_btn_debounce/sig_out_reg_reg[4]/Q
+                         net (fo=5, routed)           0.134     1.746    btnDeBnc[4]
+    SLICE_X13Y11         LUT6 (Prop_lut6_I5_O)        0.045     1.791 r  uartState[2]_i_1/O
+                         net (fo=1, routed)           0.000     1.791    uartState[2]_i_1_n_0
+    SLICE_X13Y11         FDRE                                         r  uartState_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.834     1.961    CLK_IBUF_BUFG
+    SLICE_X13Y11         FDRE                                         r  uartState_reg[2]/C
+                         clock pessimism             -0.498     1.463    
+    SLICE_X13Y11         FDRE (Hold_fdre_C_D)         0.092     1.555    uartState_reg[2]
+  -------------------------------------------------------------------
+                         required time                         -1.555    
+                         arrival time                           1.791    
+  -------------------------------------------------------------------
+                         slack                                  0.235    
+
+Slack (MET) :             0.244ns  (arrival time - required time)
+  Source:                 uartData_reg[6]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_UART_TX_CTRL/txData_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.313ns  (logic 0.141ns (45.028%)  route 0.172ns (54.972%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.962ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.498ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.565     1.448    CLK_IBUF_BUFG
+    SLICE_X9Y7           FDRE                                         r  uartData_reg[6]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X9Y7           FDRE (Prop_fdre_C_Q)         0.141     1.589 r  uartData_reg[6]/Q
+                         net (fo=1, routed)           0.172     1.761    Inst_UART_TX_CTRL/DATA[6]
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.835     1.962    Inst_UART_TX_CTRL/CLK
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[7]/C
+                         clock pessimism             -0.498     1.464    
+    SLICE_X8Y8           FDRE (Hold_fdre_C_D)         0.053     1.517    Inst_UART_TX_CTRL/txData_reg[7]
+  -------------------------------------------------------------------
+                         required time                         -1.517    
+                         arrival time                           1.761    
+  -------------------------------------------------------------------
+                         slack                                  0.244    
+
+Slack (MET) :             0.249ns  (arrival time - required time)
+  Source:                 uartSend_reg/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_UART_TX_CTRL/txData_reg[1]/CE
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.269ns  (logic 0.141ns (52.505%)  route 0.128ns (47.495%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.962ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.478ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.565     1.448    CLK_IBUF_BUFG
+    SLICE_X11Y8          FDRE                                         r  uartSend_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X11Y8          FDRE (Prop_fdre_C_Q)         0.141     1.589 r  uartSend_reg/Q
+                         net (fo=8, routed)           0.128     1.717    Inst_UART_TX_CTRL/SEND
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[1]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.835     1.962    Inst_UART_TX_CTRL/CLK
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[1]/C
+                         clock pessimism             -0.478     1.484    
+    SLICE_X8Y8           FDRE (Hold_fdre_C_CE)       -0.016     1.468    Inst_UART_TX_CTRL/txData_reg[1]
+  -------------------------------------------------------------------
+                         required time                         -1.468    
+                         arrival time                           1.717    
+  -------------------------------------------------------------------
+                         slack                                  0.249    
+
+Slack (MET) :             0.249ns  (arrival time - required time)
+  Source:                 uartSend_reg/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_UART_TX_CTRL/txData_reg[3]/CE
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.269ns  (logic 0.141ns (52.505%)  route 0.128ns (47.495%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.962ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.478ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.565     1.448    CLK_IBUF_BUFG
+    SLICE_X11Y8          FDRE                                         r  uartSend_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X11Y8          FDRE (Prop_fdre_C_Q)         0.141     1.589 r  uartSend_reg/Q
+                         net (fo=8, routed)           0.128     1.717    Inst_UART_TX_CTRL/SEND
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[3]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.835     1.962    Inst_UART_TX_CTRL/CLK
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[3]/C
+                         clock pessimism             -0.478     1.484    
+    SLICE_X8Y8           FDRE (Hold_fdre_C_CE)       -0.016     1.468    Inst_UART_TX_CTRL/txData_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -1.468    
+                         arrival time                           1.717    
+  -------------------------------------------------------------------
+                         slack                                  0.249    
+
+Slack (MET) :             0.249ns  (arrival time - required time)
+  Source:                 uartSend_reg/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            Inst_UART_TX_CTRL/txData_reg[4]/CE
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.269ns  (logic 0.141ns (52.505%)  route 0.128ns (47.495%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.962ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.478ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.565     1.448    CLK_IBUF_BUFG
+    SLICE_X11Y8          FDRE                                         r  uartSend_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X11Y8          FDRE (Prop_fdre_C_Q)         0.141     1.589 r  uartSend_reg/Q
+                         net (fo=8, routed)           0.128     1.717    Inst_UART_TX_CTRL/SEND
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[4]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.835     1.962    Inst_UART_TX_CTRL/CLK
+    SLICE_X8Y8           FDRE                                         r  Inst_UART_TX_CTRL/txData_reg[4]/C
+                         clock pessimism             -0.478     1.484    
+    SLICE_X8Y8           FDRE (Hold_fdre_C_CE)       -0.016     1.468    Inst_UART_TX_CTRL/txData_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -1.468    
+                         arrival time                           1.717    
+  -------------------------------------------------------------------
+                         slack                                  0.249    
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         sys_clk_pin
+Waveform(ns):       { 0.000 5.000 }
+Period(ns):         10.000
+Sources:            { CLK }
+
+Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period        n/a     BUFG/I             n/a            2.155         10.000      7.845      BUFGCTRL_X0Y1    CLK_IBUF_BUFG_inst/I
+Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y8       Inst_UART_TX_CTRL/bitIndex_reg[0]/C
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y10      Inst_UART_TX_CTRL/bitIndex_reg[10]/C
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y10      Inst_UART_TX_CTRL/bitIndex_reg[11]/C
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[12]/C
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[13]/C
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[14]/C
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[15]/C
+Min Period        n/a     FDRE/C             n/a            1.000         10.000      9.000      SLICE_X9Y12      Inst_UART_TX_CTRL/bitIndex_reg[16]/C
+Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
+Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
+Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[12]/C
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[13]/C
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[14]/C
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X9Y11      Inst_UART_TX_CTRL/bitIndex_reg[15]/C
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X9Y12      Inst_UART_TX_CTRL/bitIndex_reg[16]/C
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y14      Inst_btn_debounce/sig_cntrs_ary_reg[2][0]/C
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y14      Inst_btn_debounce/sig_cntrs_ary_reg[2][1]/C
+Low Pulse Width   Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y14      Inst_btn_debounce/sig_cntrs_ary_reg[2][2]/C
+High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
+High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
+High Pulse Width  Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X9Y8       Inst_UART_TX_CTRL/bitIndex_reg[0]/C
+High Pulse Width  Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y8       Inst_UART_TX_CTRL/txData_reg[1]/C
+High Pulse Width  Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y8       Inst_UART_TX_CTRL/txData_reg[3]/C
+High Pulse Width  Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y8       Inst_UART_TX_CTRL/txData_reg[4]/C
+High Pulse Width  Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y8       Inst_UART_TX_CTRL/txData_reg[5]/C
+High Pulse Width  Slow    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y8       Inst_UART_TX_CTRL/txData_reg[6]/C
+High Pulse Width  Fast    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y16      Inst_btn_debounce/sig_cntrs_ary_reg[2][10]/C
+High Pulse Width  Fast    FDRE/C             n/a            0.500         5.000       4.500      SLICE_X8Y16      Inst_btn_debounce/sig_cntrs_ary_reg[2][11]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clk_out1_clk_wiz_0
+  To Clock:  clk_out1_clk_wiz_0
+
+Setup :            0  Failing Endpoints,  Worst Slack        3.744ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.064ns,  Total Violation        0.000ns
+PW    :            0  Failing Endpoints,  Worst Slack        4.130ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             3.744ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        5.474ns  (logic 2.609ns (47.666%)  route 2.865ns (52.334%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.858ns = ( 14.118 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          1.047    10.298    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X5Y43          LUT5 (Prop_lut5_I3_O)        0.332    10.630 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[2]_i_1/O
+                         net (fo=1, routed)           0.000    10.630    Inst_vga_ctrl/Inst_MouseCtl/x_pos[2]_i_1_n_0
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.517    14.118    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/C
+                         clock pessimism              0.298    14.416    
+                         clock uncertainty           -0.072    14.343    
+    SLICE_X5Y43          FDRE (Setup_fdre_C_D)        0.031    14.374    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]
+  -------------------------------------------------------------------
+                         required time                         14.374    
+                         arrival time                         -10.630    
+  -------------------------------------------------------------------
+                         slack                                  3.744    
+
+Slack (MET) :             3.938ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        5.252ns  (logic 2.569ns (48.913%)  route 2.683ns (51.087%))
+  Logic Levels:           5  (CARRY4=3 LUT4=1 LUT5=1)
+  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.858ns = ( 14.118 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.158ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.637     5.158    Inst_vga_ctrl/pxl_clk
+    SLICE_X1Y42          FDRE                                         r  Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y42          FDRE (Prop_fdre_C_Q)         0.456     5.614 r  Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/Q
+                         net (fo=2, routed)           0.875     6.489    Inst_vga_ctrl/Inst_MouseDisplay/xpos[5]
+    SLICE_X4Y44          CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.656     7.145 r  Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_35/CO[3]
+                         net (fo=1, routed)           0.000     7.145    Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_35_n_0
+    SLICE_X4Y45          CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     7.479 r  Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_34/O[1]
+                         net (fo=2, routed)           0.872     8.351    Inst_vga_ctrl/Inst_MouseDisplay/plusOp26[10]
+    SLICE_X7Y45          LUT4 (Prop_lut4_I1_O)        0.303     8.654 r  Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_9/O
+                         net (fo=1, routed)           0.000     8.654    Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_9_n_0
+    SLICE_X7Y45          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.491     9.145 r  Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_2/CO[1]
+                         net (fo=1, routed)           0.936    10.081    Inst_vga_ctrl/Inst_MouseDisplay/geqOp
+    SLICE_X3Y39          LUT5 (Prop_lut5_I0_O)        0.329    10.410 r  Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_1/O
+                         net (fo=1, routed)           0.000    10.410    Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_1_n_0
+    SLICE_X3Y39          FDRE                                         r  Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.517    14.118    Inst_vga_ctrl/Inst_MouseDisplay/pixel_clk
+    SLICE_X3Y39          FDRE                                         r  Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/C
+                         clock pessimism              0.274    14.392    
+                         clock uncertainty           -0.072    14.319    
+    SLICE_X3Y39          FDRE (Setup_fdre_C_D)        0.029    14.348    Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg
+  -------------------------------------------------------------------
+                         required time                         14.348    
+                         arrival time                         -10.410    
+  -------------------------------------------------------------------
+                         slack                                  3.938    
+
+Slack (MET) :             4.066ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        5.150ns  (logic 2.609ns (50.660%)  route 2.541ns (49.340%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.858ns = ( 14.118 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.723     9.974    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X5Y43          LUT5 (Prop_lut5_I3_O)        0.332    10.306 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]_i_1/O
+                         net (fo=1, routed)           0.000    10.306    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]_i_1_n_0
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.517    14.118    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                         clock pessimism              0.298    14.416    
+                         clock uncertainty           -0.072    14.343    
+    SLICE_X5Y43          FDRE (Setup_fdre_C_D)        0.029    14.372    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]
+  -------------------------------------------------------------------
+                         required time                         14.372    
+                         arrival time                         -10.306    
+  -------------------------------------------------------------------
+                         slack                                  4.066    
+
+Slack (MET) :             4.148ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        5.070ns  (logic 2.609ns (51.464%)  route 2.461ns (48.536%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.858ns = ( 14.118 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.643     9.894    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X5Y43          LUT5 (Prop_lut5_I3_O)        0.332    10.226 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_1/O
+                         net (fo=1, routed)           0.000    10.226    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_1_n_0
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.517    14.118    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/C
+                         clock pessimism              0.298    14.416    
+                         clock uncertainty           -0.072    14.343    
+    SLICE_X5Y43          FDRE (Setup_fdre_C_D)        0.031    14.374    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]
+  -------------------------------------------------------------------
+                         required time                         14.374    
+                         arrival time                         -10.226    
+  -------------------------------------------------------------------
+                         slack                                  4.148    
+
+Slack (MET) :             4.150ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        5.069ns  (logic 2.609ns (51.474%)  route 2.460ns (48.526%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.858ns = ( 14.118 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.298ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.642     9.893    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X5Y43          LUT5 (Prop_lut5_I3_O)        0.332    10.225 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[4]_i_1/O
+                         net (fo=1, routed)           0.000    10.225    Inst_vga_ctrl/Inst_MouseCtl/x_pos[4]_i_1_n_0
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.517    14.118    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/C
+                         clock pessimism              0.298    14.416    
+                         clock uncertainty           -0.072    14.343    
+    SLICE_X5Y43          FDRE (Setup_fdre_C_D)        0.032    14.375    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]
+  -------------------------------------------------------------------
+                         required time                         14.375    
+                         arrival time                         -10.225    
+  -------------------------------------------------------------------
+                         slack                                  4.150    
+
+Slack (MET) :             4.278ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        4.902ns  (logic 2.609ns (53.218%)  route 2.293ns (46.782%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.860ns = ( 14.120 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.260ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.476     9.727    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X1Y44          LUT5 (Prop_lut5_I3_O)        0.332    10.059 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[0]_i_1/O
+                         net (fo=1, routed)           0.000    10.059    Inst_vga_ctrl/Inst_MouseCtl/x_pos[0]_i_1_n_0
+    SLICE_X1Y44          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.519    14.120    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X1Y44          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/C
+                         clock pessimism              0.260    14.380    
+                         clock uncertainty           -0.072    14.307    
+    SLICE_X1Y44          FDRE (Setup_fdre_C_D)        0.029    14.336    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]
+  -------------------------------------------------------------------
+                         required time                         14.336    
+                         arrival time                         -10.059    
+  -------------------------------------------------------------------
+                         slack                                  4.278    
+
+Slack (MET) :             4.294ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        4.888ns  (logic 2.609ns (53.372%)  route 2.279ns (46.628%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.860ns = ( 14.120 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.260ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 f  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.462     9.713    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X3Y46          LUT5 (Prop_lut5_I4_O)        0.332    10.045 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[9]_i_1/O
+                         net (fo=1, routed)           0.000    10.045    Inst_vga_ctrl/Inst_MouseCtl/x_pos[9]_i_1_n_0
+    SLICE_X3Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.519    14.120    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X3Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/C
+                         clock pessimism              0.260    14.380    
+                         clock uncertainty           -0.072    14.307    
+    SLICE_X3Y46          FDRE (Setup_fdre_C_D)        0.031    14.338    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]
+  -------------------------------------------------------------------
+                         required time                         14.338    
+                         arrival time                         -10.045    
+  -------------------------------------------------------------------
+                         slack                                  4.294    
+
+Slack (MET) :             4.296ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        4.884ns  (logic 2.609ns (53.416%)  route 2.275ns (46.584%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.860ns = ( 14.120 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.260ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 f  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.458     9.709    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X3Y46          LUT5 (Prop_lut5_I4_O)        0.332    10.041 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[8]_i_1/O
+                         net (fo=1, routed)           0.000    10.041    Inst_vga_ctrl/Inst_MouseCtl/x_pos[8]_i_1_n_0
+    SLICE_X3Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.519    14.120    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X3Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/C
+                         clock pessimism              0.260    14.380    
+                         clock uncertainty           -0.072    14.307    
+    SLICE_X3Y46          FDRE (Setup_fdre_C_D)        0.029    14.336    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]
+  -------------------------------------------------------------------
+                         required time                         14.336    
+                         arrival time                         -10.041    
+  -------------------------------------------------------------------
+                         slack                                  4.296    
+
+Slack (MET) :             4.393ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        4.798ns  (logic 2.609ns (54.374%)  route 2.189ns (45.626%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.858ns = ( 14.118 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.273ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.371     9.623    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X4Y46          LUT5 (Prop_lut5_I3_O)        0.332     9.955 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[10]_i_1/O
+                         net (fo=1, routed)           0.000     9.955    Inst_vga_ctrl/Inst_MouseCtl/x_pos[10]_i_1_n_0
+    SLICE_X4Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.517    14.118    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X4Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/C
+                         clock pessimism              0.273    14.391    
+                         clock uncertainty           -0.072    14.318    
+    SLICE_X4Y46          FDRE (Setup_fdre_C_D)        0.029    14.347    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]
+  -------------------------------------------------------------------
+                         required time                         14.347    
+                         arrival time                          -9.955    
+  -------------------------------------------------------------------
+                         slack                                  4.393    
+
+Slack (MET) :             4.396ns  (required time - arrival time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            9.259ns  (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        4.798ns  (logic 2.609ns (54.374%)  route 2.189ns (45.626%))
+  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.858ns = ( 14.118 - 9.259 ) 
+    Source Clock Delay      (SCD):    5.156ns
+    Clock Pessimism Removal (CPR):    0.273ns
+  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.126ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096     3.521 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.575     5.096    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.333     1.763 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.661     3.425    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.635     5.156    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X5Y43          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y43          FDRE (Prop_fdre_C_Q)         0.456     5.612 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
+                         net (fo=5, routed)           0.967     6.579    Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
+    SLICE_X5Y44          LUT3 (Prop_lut3_I0_O)        0.124     6.703 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
+                         net (fo=1, routed)           0.000     6.703    Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
+    SLICE_X5Y44          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.550     7.253 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.253    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
+    SLICE_X5Y45          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.367 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.367    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
+    SLICE_X5Y46          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.606 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
+                         net (fo=2, routed)           0.851     8.457    Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
+    SLICE_X2Y46          LUT2 (Prop_lut2_I0_O)        0.302     8.759 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
+                         net (fo=1, routed)           0.000     8.759    Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
+    SLICE_X2Y46          CARRY4 (Prop_carry4_S[1]_CO[1])
+                                                      0.492     9.251 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
+                         net (fo=12, routed)          0.371     9.623    Inst_vga_ctrl/Inst_MouseCtl/gtOp
+    SLICE_X4Y46          LUT5 (Prop_lut5_I3_O)        0.332     9.955 r  Inst_vga_ctrl/Inst_MouseCtl/x_pos[7]_i_1/O
+                         net (fo=1, routed)           0.000     9.955    Inst_vga_ctrl/Inst_MouseCtl/x_pos[7]_i_1_n_0
+    SLICE_X4Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      9.259     9.259 r  
+    W5                                                0.000     9.259 r  CLK (IN)
+                         net (fo=0)                   0.000     9.259    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    10.647 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           1.862    12.509    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    12.600 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         1.457    14.058    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -3.129    10.928 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           1.581    12.509    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    12.600 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         1.517    14.118    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X4Y46          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/C
+                         clock pessimism              0.273    14.391    
+                         clock uncertainty           -0.072    14.318    
+    SLICE_X4Y46          FDRE (Setup_fdre_C_D)        0.032    14.350    Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]
+  -------------------------------------------------------------------
+                         required time                         14.350    
+                         arrival time                          -9.955    
+  -------------------------------------------------------------------
+                         slack                                  4.396    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.064ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.354ns  (logic 0.148ns (41.815%)  route 0.206ns (58.185%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.992ns
+    Source Clock Delay      (SCD):    1.475ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.592     1.475    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y50          FDRE (Prop_fdre_C_Q)         0.148     1.623 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/Q
+                         net (fo=3, routed)           0.206     1.829    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[6]
+    SLICE_X7Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.865     1.992    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X7Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/C
+                         clock pessimism             -0.244     1.748    
+    SLICE_X7Y49          FDRE (Hold_fdre_C_D)         0.017     1.765    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]
+  -------------------------------------------------------------------
+                         required time                         -1.765    
+                         arrival time                           1.829    
+  -------------------------------------------------------------------
+                         slack                                  0.064    
+
+Slack (MET) :             0.068ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.488ns  (logic 0.209ns (42.827%)  route 0.279ns (57.173%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.300ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.992ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.565     1.448    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X8Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X8Y50          FDRE (Prop_fdre_C_Q)         0.164     1.612 r  Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/Q
+                         net (fo=2, routed)           0.279     1.891    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_data[0]
+    SLICE_X6Y49          LUT3 (Prop_lut3_I1_O)        0.045     1.936 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[1]_i_1/O
+                         net (fo=1, routed)           0.000     1.936    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[1]_i_1_n_0
+    SLICE_X6Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.865     1.992    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/C
+                         clock pessimism             -0.244     1.748    
+    SLICE_X6Y49          FDRE (Hold_fdre_C_D)         0.120     1.868    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]
+  -------------------------------------------------------------------
+                         required time                         -1.868    
+                         arrival time                           1.936    
+  -------------------------------------------------------------------
+                         slack                                  0.068    
+
+Slack (MET) :             0.090ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.448ns  (logic 0.209ns (46.656%)  route 0.239ns (53.344%))
+  Logic Levels:           1  (LUT6=1)
+  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.990ns
+    Source Clock Delay      (SCD):    1.479ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.596     1.479    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X2Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X2Y49          FDRE (Prop_fdre_C_Q)         0.164     1.643 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/Q
+                         net (fo=28, routed)          0.239     1.882    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg_n_0_[2]
+    SLICE_X5Y50          LUT6 (Prop_lut6_I1_O)        0.045     1.927 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_inv_i_2/O
+                         net (fo=1, routed)           0.000     1.927    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_inv_i_1_n_0
+    SLICE_X5Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.863     1.990    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X5Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/C
+                         clock pessimism             -0.244     1.746    
+    SLICE_X5Y50          FDRE (Hold_fdre_C_D)         0.091     1.837    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv
+  -------------------------------------------------------------------
+                         required time                         -1.837    
+                         arrival time                           1.927    
+  -------------------------------------------------------------------
+                         slack                                  0.090    
+
+Slack (MET) :             0.091ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.485ns  (logic 0.246ns (50.728%)  route 0.239ns (49.272%))
+  Logic Levels:           1  (LUT5=1)
+  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.992ns
+    Source Clock Delay      (SCD):    1.475ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.592     1.475    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y50          FDRE (Prop_fdre_C_Q)         0.148     1.623 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/Q
+                         net (fo=3, routed)           0.239     1.862    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[6]
+    SLICE_X6Y48          LUT5 (Prop_lut5_I3_O)        0.098     1.960 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_i_1/O
+                         net (fo=1, routed)           0.000     1.960    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_i_1_n_0
+    SLICE_X6Y48          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.865     1.992    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y48          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/C
+                         clock pessimism             -0.244     1.748    
+    SLICE_X6Y48          FDRE (Hold_fdre_C_D)         0.121     1.869    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg
+  -------------------------------------------------------------------
+                         required time                         -1.869    
+                         arrival time                           1.960    
+  -------------------------------------------------------------------
+                         slack                                  0.091    
+
+Slack (MET) :             0.102ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.506ns  (logic 0.185ns (36.583%)  route 0.321ns (63.417%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.992ns
+    Source Clock Delay      (SCD):    1.475ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.592     1.475    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X7Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y50          FDRE (Prop_fdre_C_Q)         0.141     1.616 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/Q
+                         net (fo=1, routed)           0.321     1.937    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/p_1_in[9]
+    SLICE_X6Y49          LUT3 (Prop_lut3_I0_O)        0.044     1.981 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_2/O
+                         net (fo=1, routed)           0.000     1.981    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_2_n_0
+    SLICE_X6Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.865     1.992    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/C
+                         clock pessimism             -0.244     1.748    
+    SLICE_X6Y49          FDRE (Hold_fdre_C_D)         0.131     1.879    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]
+  -------------------------------------------------------------------
+                         required time                         -1.879    
+                         arrival time                           1.981    
+  -------------------------------------------------------------------
+                         slack                                  0.102    
+
+Slack (MET) :             0.104ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.534ns  (logic 0.250ns (46.773%)  route 0.284ns (53.227%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.300ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.992ns
+    Source Clock Delay      (SCD):    1.448ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.565     1.448    Inst_vga_ctrl/Inst_MouseCtl/clk
+    SLICE_X8Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X8Y50          FDRE (Prop_fdre_C_Q)         0.148     1.596 r  Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/Q
+                         net (fo=2, routed)           0.284     1.881    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_data[7]
+    SLICE_X6Y49          LUT3 (Prop_lut3_I0_O)        0.102     1.983 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[8]_i_1/O
+                         net (fo=1, routed)           0.000     1.983    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[8]_i_1_n_0
+    SLICE_X6Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.865     1.992    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
+                         clock pessimism             -0.244     1.748    
+    SLICE_X6Y49          FDRE (Hold_fdre_C_D)         0.131     1.879    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]
+  -------------------------------------------------------------------
+                         required time                         -1.879    
+                         arrival time                           1.983    
+  -------------------------------------------------------------------
+                         slack                                  0.104    
+
+Slack (MET) :             0.114ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.488ns  (logic 0.355ns (72.708%)  route 0.133ns (27.292%))
+  Logic Levels:           2  (CARRY4=2)
+  Clock Path Skew:        0.269ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.990ns
+    Source Clock Delay      (SCD):    1.477ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.594     1.477    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X4Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y49          FDRE (Prop_fdre_C_Q)         0.141     1.618 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/Q
+                         net (fo=2, routed)           0.133     1.751    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]
+    SLICE_X4Y49          CARRY4 (Prop_carry4_S[2]_CO[3])
+                                                      0.160     1.911 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3/CO[3]
+                         net (fo=1, routed)           0.001     1.911    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3_n_0
+    SLICE_X4Y50          CARRY4 (Prop_carry4_CI_O[0])
+                                                      0.054     1.965 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1/O[0]
+                         net (fo=1, routed)           0.000     1.965    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1_n_7
+    SLICE_X4Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.863     1.990    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X4Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/C
+                         clock pessimism             -0.244     1.746    
+    SLICE_X4Y50          FDRE (Hold_fdre_C_D)         0.105     1.851    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -1.851    
+                         arrival time                           1.965    
+  -------------------------------------------------------------------
+                         slack                                  0.114    
+
+Slack (MET) :             0.122ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/h_sync_reg_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/h_sync_reg_dly_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.990ns
+    Source Clock Delay      (SCD):    1.475ns
+    Clock Pessimism Removal (CPR):    0.515ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.592     1.475    Inst_vga_ctrl/pxl_clk
+    SLICE_X7Y40          FDRE                                         r  Inst_vga_ctrl/h_sync_reg_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y40          FDRE (Prop_fdre_C_Q)         0.141     1.616 r  Inst_vga_ctrl/h_sync_reg_reg/Q
+                         net (fo=1, routed)           0.056     1.672    Inst_vga_ctrl/h_sync_reg
+    SLICE_X7Y40          FDRE                                         r  Inst_vga_ctrl/h_sync_reg_dly_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.863     1.990    Inst_vga_ctrl/pxl_clk
+    SLICE_X7Y40          FDRE                                         r  Inst_vga_ctrl/h_sync_reg_dly_reg/C
+                         clock pessimism             -0.515     1.475    
+    SLICE_X7Y40          FDRE (Hold_fdre_C_D)         0.075     1.550    Inst_vga_ctrl/h_sync_reg_dly_reg
+  -------------------------------------------------------------------
+                         required time                         -1.550    
+                         arrival time                           1.672    
+  -------------------------------------------------------------------
+                         slack                                  0.122    
+
+Slack (MET) :             0.125ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.499ns  (logic 0.366ns (73.309%)  route 0.133ns (26.691%))
+  Logic Levels:           2  (CARRY4=2)
+  Clock Path Skew:        0.269ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.990ns
+    Source Clock Delay      (SCD):    1.477ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.594     1.477    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X4Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y49          FDRE (Prop_fdre_C_Q)         0.141     1.618 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/Q
+                         net (fo=2, routed)           0.133     1.751    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]
+    SLICE_X4Y49          CARRY4 (Prop_carry4_S[2]_CO[3])
+                                                      0.160     1.911 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3/CO[3]
+                         net (fo=1, routed)           0.001     1.911    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3_n_0
+    SLICE_X4Y50          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.065     1.976 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1/O[2]
+                         net (fo=1, routed)           0.000     1.976    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1_n_5
+    SLICE_X4Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.863     1.990    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X4Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/C
+                         clock pessimism             -0.244     1.746    
+    SLICE_X4Y50          FDRE (Hold_fdre_C_D)         0.105     1.851    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]
+  -------------------------------------------------------------------
+                         required time                         -1.851    
+                         arrival time                           1.976    
+  -------------------------------------------------------------------
+                         slack                                  0.125    
+
+Slack (MET) :             0.144ns  (arrival time - required time)
+  Source:                 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Destination:            Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@4.630ns period=9.259ns})
+  Path Group:             clk_out1_clk_wiz_0
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+  Data Path Delay:        0.544ns  (logic 0.249ns (45.767%)  route 0.295ns (54.233%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.269ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.990ns
+    Source Clock Delay      (SCD):    1.477ns
+    Clock Pessimism Removal (CPR):    0.244ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.884 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.549     1.432    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.061     0.372 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.486     0.858    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.594     1.477    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y49          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y49          FDRE (Prop_fdre_C_Q)         0.148     1.625 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/Q
+                         net (fo=3, routed)           0.295     1.920    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[7]
+    SLICE_X6Y50          LUT3 (Prop_lut3_I2_O)        0.101     2.021 r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[7]_i_1/O
+                         net (fo=1, routed)           0.000     2.021    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[7]_i_1_n_0
+    SLICE_X6Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_out1_clk_wiz_0 rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  CLK (IN)
+                         net (fo=0)                   0.000     0.000    CLK
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  CLK_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    CLK_IBUF
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.128 r  CLK_IBUF_BUFG_inst/O
+                         net (fo=243, routed)         0.817     1.944    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
+    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                     -1.375     0.569 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+                         net (fo=1, routed)           0.530     1.099    Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
+                         net (fo=336, routed)         0.863     1.990    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
+    SLICE_X6Y50          FDRE                                         r  Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
+                         clock pessimism             -0.244     1.746    
+    SLICE_X6Y50          FDRE (Hold_fdre_C_D)         0.131     1.877    Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]
+  -------------------------------------------------------------------
+                         required time                         -1.877    
+                         arrival time                           2.021    
+  -------------------------------------------------------------------
+                         slack                                  0.144    
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         clk_out1_clk_wiz_0
+Waveform(ns):       { 0.000 4.630 }
+Period(ns):         9.259
+Sources:            { Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0 }
+
+Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period        n/a     BUFG/I              n/a            2.155         9.259       7.104      BUFGCTRL_X0Y0    Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/I
+Min Period        n/a     MMCME2_ADV/CLKOUT0  n/a            1.249         9.259       8.010      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X12Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[10]/C
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X14Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[1]/C
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X14Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[2]/C
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X13Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[3]/C
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X13Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[4]/C
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X13Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[5]/C
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X12Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[6]/C
+Min Period        n/a     FDRE/C              n/a            1.000         9.259       8.259      SLICE_X13Y50     Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[7]/C
+Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       9.259       204.101    MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X1Y31      Inst_vga_ctrl/cntDyn_reg[0]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X1Y31      Inst_vga_ctrl/cntDyn_reg[1]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X1Y31      Inst_vga_ctrl/cntDyn_reg[2]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X1Y31      Inst_vga_ctrl/cntDyn_reg[3]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X4Y46      Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X5Y42      Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[1]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X5Y42      Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[2]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X5Y42      Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[5]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X5Y42      Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[7]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X6Y45      Inst_vga_ctrl/MOUSE_X_POS_REG_reg[10]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X7Y50      Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_done_reg/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X11Y45     Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[13]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X9Y44      Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[14]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X11Y45     Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[15]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X11Y45     Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[16]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X11Y45     Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[17]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X9Y44      Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[18]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X11Y45     Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[19]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X11Y42     Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[1]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         4.630       4.130      SLICE_X11Y42     Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[1]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clkfbout_clk_wiz_0
+  To Clock:  clkfbout_clk_wiz_0
+
+Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+PW    :            0  Failing Endpoints,  Worst Slack        7.845ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         clkfbout_clk_wiz_0
+Waveform(ns):       { 0.000 5.000 }
+Period(ns):         10.000
+Sources:            { Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT }
+
+Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period  n/a     BUFG/I               n/a            2.155         10.000      7.845      BUFGCTRL_X0Y2    Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/I
+Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT
+Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBIN
+Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBIN
+Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       10.000      203.360    MMCME2_ADV_X1Y0  Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT
+
+
+
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpx b/proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpx
new file mode 100644
index 0000000..e6c599a
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpx differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.pb b/proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.pb
new file mode 100644
index 0000000..ef5eb84
Binary files /dev/null and b/proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.pb differ
diff --git a/proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.rpt b/proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.rpt
new file mode 100644
index 0000000..86b2ce7
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.rpt
@@ -0,0 +1,212 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:16:08 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_utilization -file GPIO_demo_utilization_placed.rpt -pb GPIO_demo_utilization_placed.pb
+| Design       : GPIO_demo
+| Device       : 7a35tcpg236-1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+-----------+-------+
+|        Site Type        | Used | Fixed | Available | Util% |
++-------------------------+------+-------+-----------+-------+
+| Slice LUTs              |  564 |     0 |     20800 |  2.71 |
+|   LUT as Logic          |  564 |     0 |     20800 |  2.71 |
+|   LUT as Memory         |    0 |     0 |      9600 |  0.00 |
+| Slice Registers         |  578 |     0 |     41600 |  1.39 |
+|   Register as Flip Flop |  578 |     0 |     41600 |  1.39 |
+|   Register as Latch     |    0 |     0 |     41600 |  0.00 |
+| F7 Muxes                |    3 |     0 |     16300 |  0.02 |
+| F8 Muxes                |    0 |     0 |      8150 |  0.00 |
++-------------------------+------+-------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 2     |          Yes |         Set |            - |
+| 576   |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++-------------------------------------------+------+-------+-----------+-------+
+|                 Site Type                 | Used | Fixed | Available | Util% |
++-------------------------------------------+------+-------+-----------+-------+
+| Slice                                     |  282 |     0 |      8150 |  3.46 |
+|   SLICEL                                  |  182 |     0 |           |       |
+|   SLICEM                                  |  100 |     0 |           |       |
+| LUT as Logic                              |  564 |     0 |     20800 |  2.71 |
+|   using O5 output only                    |    0 |       |           |       |
+|   using O6 output only                    |  433 |       |           |       |
+|   using O5 and O6                         |  131 |       |           |       |
+| LUT as Memory                             |    0 |     0 |      9600 |  0.00 |
+|   LUT as Distributed RAM                  |    0 |     0 |           |       |
+|   LUT as Shift Register                   |    0 |     0 |           |       |
+| LUT Flip Flop Pairs                       |  171 |     0 |     20800 |  0.82 |
+|   fully used LUT-FF pairs                 |   54 |       |           |       |
+|   LUT-FF pairs with one unused LUT output |  110 |       |           |       |
+|   LUT-FF pairs with one unused Flip Flop  |  111 |       |           |       |
+| Unique Control Sets                       |   36 |       |           |       |
++-------------------------------------------+------+-------+-----------+-------+
+* Note: Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile |    0 |     0 |        50 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |        50 |  0.00 |
+|   RAMB18       |    0 |     0 |       100 |  0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs      |    0 |     0 |        90 |  0.00 |
++-----------+------+-------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+|          Site Type          | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB                  |   67 |    67 |       106 | 63.21 |
+|   IOB Master Pads           |   30 |       |           |       |
+|   IOB Slave Pads            |   35 |       |           |       |
+| Bonded IPADs                |    0 |     0 |        10 |  0.00 |
+| Bonded OPADs                |    0 |     0 |         4 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |         5 |  0.00 |
+| PHASER_REF                  |    0 |     0 |         5 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |        20 |  0.00 |
+| IN_FIFO                     |    0 |     0 |        20 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |         5 |  0.00 |
+| IBUFDS                      |    0 |     0 |       104 |  0.00 |
+| GTPE2_CHANNEL               |    0 |     0 |         2 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        20 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        20 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       250 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |         2 |  0.00 |
+| ILOGIC                      |    0 |     0 |       106 |  0.00 |
+| OLOGIC                      |    0 |     0 |       106 |  0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL   |    3 |     0 |        32 |  9.38 |
+| BUFIO      |    0 |     0 |        20 |  0.00 |
+| MMCME2_ADV |    1 |     0 |         5 | 20.00 |
+| PLLE2_ADV  |    0 |     0 |         5 |  0.00 |
+| BUFMRCE    |    0 |     0 |        10 |  0.00 |
+| BUFHCE     |    0 |     0 |        72 |  0.00 |
+| BUFR       |    0 |     0 |        20 |  0.00 |
++------------+------+-------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |         1 |  0.00 |
+| XADC        |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+|  Ref Name  | Used | Functional Category |
++------------+------+---------------------+
+| FDRE       |  576 |        Flop & Latch |
+| LUT2       |  207 |                 LUT |
+| LUT6       |  157 |                 LUT |
+| LUT4       |  136 |                 LUT |
+| CARRY4     |  132 |          CarryLogic |
+| LUT3       |   93 |                 LUT |
+| LUT5       |   72 |                 LUT |
+| OBUF       |   43 |                  IO |
+| LUT1       |   30 |                 LUT |
+| IBUF       |   24 |                  IO |
+| MUXF7      |    3 |               MuxFx |
+| BUFG       |    3 |               Clock |
+| OBUFT      |    2 |                  IO |
+| FDSE       |    2 |        Flop & Latch |
+| MMCME2_ADV |    1 |               Clock |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/GPIO.runs/impl_1/ISEWrap.js b/proj/GPIO.runs/impl_1/ISEWrap.js
new file mode 100644
index 0000000..898ddd7
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/ISEWrap.js
@@ -0,0 +1,244 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/proj/GPIO.runs/impl_1/ISEWrap.sh b/proj/GPIO.runs/impl_1/ISEWrap.sh
new file mode 100644
index 0000000..e1a8f5d
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/GPIO.runs/impl_1/gen_run.xml b/proj/GPIO.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000..9c64ea1
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/gen_run.xml
@@ -0,0 +1,157 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1618002924">
+  <File Type="PWROPT-DRC" Name="GPIO_demo_drc_pwropted.rpt"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="GPIO_demo_methodology_drc_opted.rpt"/>
+  <File Type="INIT-TIMING" Name="GPIO_demo_timing_summary_init.rpt"/>
+  <File Type="ROUTE-PWR-RPX" Name="GPIO_demo_power_routed.rpx"/>
+  <File Type="PA-TCL" Name="GPIO_demo.tcl"/>
+  <File Type="OPT-HWDEF" Name="GPIO_demo.hwdef"/>
+  <File Type="RDI-RDI" Name="GPIO_demo.vdi"/>
+  <File Type="OPT-DCP" Name="GPIO_demo_opt.dcp"/>
+  <File Type="OPT-DRC" Name="GPIO_demo_drc_opted.rpt"/>
+  <File Type="OPT-TIMING" Name="GPIO_demo_timing_summary_opted.rpt"/>
+  <File Type="PWROPT-DCP" Name="GPIO_demo_pwropt.dcp"/>
+  <File Type="PWROPT-TIMING" Name="GPIO_demo_timing_summary_pwropted.rpt"/>
+  <File Type="PLACE-DCP" Name="GPIO_demo_placed.dcp"/>
+  <File Type="PLACE-IO" Name="GPIO_demo_io_placed.rpt"/>
+  <File Type="PLACE-CLK" Name="GPIO_demo_clock_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL" Name="GPIO_demo_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL-PB" Name="GPIO_demo_utilization_placed.pb"/>
+  <File Type="PLACE-CTRL" Name="GPIO_demo_control_sets_placed.rpt"/>
+  <File Type="PLACE-SIMILARITY" Name="GPIO_demo_incremental_reuse_placed.rpt"/>
+  <File Type="PLACE-PRE-SIMILARITY" Name="GPIO_demo_incremental_reuse_pre_placed.rpt"/>
+  <File Type="PLACE-TIMING" Name="GPIO_demo_timing_summary_placed.rpt"/>
+  <File Type="POSTPLACE-PWROPT-DCP" Name="GPIO_demo_postplace_pwropt.dcp"/>
+  <File Type="POSTPLACE-PWROPT-TIMING" Name="GPIO_demo_timing_summary_postplace_pwropted.rpt"/>
+  <File Type="PHYSOPT-DCP" Name="GPIO_demo_physopt.dcp"/>
+  <File Type="PHYSOPT-DRC" Name="GPIO_demo_drc_physopted.rpt"/>
+  <File Type="PHYSOPT-TIMING" Name="GPIO_demo_timing_summary_physopted.rpt"/>
+  <File Type="ROUTE-ERROR-DCP" Name="GPIO_demo_routed_error.dcp"/>
+  <File Type="ROUTE-DCP" Name="GPIO_demo_routed.dcp"/>
+  <File Type="ROUTE-BLACKBOX-DCP" Name="GPIO_demo_routed_bb.dcp"/>
+  <File Type="ROUTE-DRC" Name="GPIO_demo_drc_routed.rpt"/>
+  <File Type="ROUTE-DRC-PB" Name="GPIO_demo_drc_routed.pb"/>
+  <File Type="BG-BIN" Name="GPIO_demo.bin"/>
+  <File Type="ROUTE-DRC-RPX" Name="GPIO_demo_drc_routed.rpx"/>
+  <File Type="BG-DRC" Name="GPIO_demo.drc"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="GPIO_demo_methodology_drc_routed.rpt"/>
+  <File Type="BITSTR-MSK" Name="GPIO_demo.msk"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="GPIO_demo_methodology_drc_routed.rpx"/>
+  <File Type="BG-BGN" Name="GPIO_demo.bgn"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="GPIO_demo_methodology_drc_routed.pb"/>
+  <File Type="ROUTE-PWR" Name="GPIO_demo_power_routed.rpt"/>
+  <File Type="ROUTE-PWR-SUM" Name="GPIO_demo_power_summary_routed.pb"/>
+  <File Type="ROUTE-STATUS" Name="GPIO_demo_route_status.rpt"/>
+  <File Type="ROUTE-STATUS-PB" Name="GPIO_demo_route_status.pb"/>
+  <File Type="ROUTE-TIMINGSUMMARY" Name="GPIO_demo_timing_summary_routed.rpt"/>
+  <File Type="ROUTE-TIMING-PB" Name="GPIO_demo_timing_summary_routed.pb"/>
+  <File Type="ROUTE-TIMING-RPX" Name="GPIO_demo_timing_summary_routed.rpx"/>
+  <File Type="ROUTE-SIMILARITY" Name="GPIO_demo_incremental_reuse_routed.rpt"/>
+  <File Type="ROUTE-CLK" Name="GPIO_demo_clock_utilization_routed.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="GPIO_demo_postroute_physopt.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="GPIO_demo_postroute_physopt_bb.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="GPIO_demo_timing_summary_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="GPIO_demo_timing_summary_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="GPIO_demo_timing_summary_postroute_physopted.rpx"/>
+  <File Type="BG-BIT" Name="GPIO_demo.bit"/>
+  <File Type="BITSTR-RBT" Name="GPIO_demo.rbt"/>
+  <File Type="BITSTR-NKY" Name="GPIO_demo.nky"/>
+  <File Type="BITSTR-BMM" Name="GPIO_demo_bd.bmm"/>
+  <File Type="BITSTR-MMI" Name="GPIO_demo.mmi"/>
+  <File Type="BITSTR-SYSDEF" Name="GPIO_demo.sysdef"/>
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/debouncer.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="GPIO_demo"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015">
+      <Desc>Vivado Implementation Defaults</Desc>
+    </StratHandle>
+    <Step Id="init_design"/>
+    <Step Id="opt_design">
+      <Option Id="Directive">4</Option>
+    </Step>
+    <Step Id="power_opt_design"/>
+    <Step Id="place_design">
+      <Option Id="Directive">14</Option>
+    </Step>
+    <Step Id="post_place_power_opt_design"/>
+    <Step Id="phys_opt_design"/>
+    <Step Id="route_design">
+      <Option Id="Directive">5</Option>
+    </Step>
+    <Step Id="post_route_phys_opt_design"/>
+    <Step Id="write_bitstream"/>
+  </Strategy>
+</GenRun>
diff --git a/proj/GPIO.runs/impl_1/htr.txt b/proj/GPIO.runs/impl_1/htr.txt
new file mode 100644
index 0000000..e885e85
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
diff --git a/proj/GPIO.runs/impl_1/init_design.pb b/proj/GPIO.runs/impl_1/init_design.pb
new file mode 100644
index 0000000..ceb3aad
Binary files /dev/null and b/proj/GPIO.runs/impl_1/init_design.pb differ
diff --git a/proj/GPIO.runs/impl_1/opt_design.pb b/proj/GPIO.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000..f6a3bbc
Binary files /dev/null and b/proj/GPIO.runs/impl_1/opt_design.pb differ
diff --git a/proj/GPIO.runs/impl_1/place_design.pb b/proj/GPIO.runs/impl_1/place_design.pb
new file mode 100644
index 0000000..6f081d6
Binary files /dev/null and b/proj/GPIO.runs/impl_1/place_design.pb differ
diff --git a/proj/GPIO.runs/impl_1/project.wdf b/proj/GPIO.runs/impl_1/project.wdf
new file mode 100644
index 0000000..68b2b16
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:39:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3031333866366637386234623465663361303338333762383461653364333333:506172656e742050412070726f6a656374204944:00
+eof:1785114370
diff --git a/proj/GPIO.runs/impl_1/route_design.pb b/proj/GPIO.runs/impl_1/route_design.pb
new file mode 100644
index 0000000..bc67885
Binary files /dev/null and b/proj/GPIO.runs/impl_1/route_design.pb differ
diff --git a/proj/GPIO.runs/impl_1/rundef.js b/proj/GPIO.runs/impl_1/rundef.js
new file mode 100644
index 0000000..4076c64
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/rundef.js
@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;";
+} else {
+  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "write_bitstream", "begin" );
+ISEStep( "vivado",
+         "-log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/proj/GPIO.runs/impl_1/runme.bat b/proj/GPIO.runs/impl_1/runme.bat
new file mode 100644
index 0000000..660c945
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/GPIO.runs/impl_1/runme.log b/proj/GPIO.runs/impl_1/runme.log
new file mode 100644
index 0000000..a88efbb
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/runme.log
@@ -0,0 +1,473 @@
+
+*** Running vivado
+    with args -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+
+
+****** Vivado v2016.4 (64-bit)
+  **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+
+source GPIO_demo.tcl -notrace
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2016.4
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
+INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
+Command: opt_design -directive RuntimeOptimized
+INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
+
+Starting Logic Optimization Task
+Implement Debug Cores | Checksum: 11fc7498c
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-2] Deriving generated clocks
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 16f269fca
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-10] Eliminated 6 cells.
+Phase 2 Constant propagation | Checksum: 233a26f9e
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 3 Sweep
+INFO: [Opt 31-12] Eliminated 363 unconnected nets.
+INFO: [Opt 31-11] Eliminated 2 unconnected cells.
+Phase 3 Sweep | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Phase 4 BUFG optimization
+INFO: [Opt 31-12] Eliminated 0 unconnected nets.
+INFO: [Opt 31-11] Eliminated 0 unconnected cells.
+Phase 4 BUFG optimization | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: 1bb596469
+
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
+INFO: [Common 17-83] Releasing license: Implementation
+24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
+INFO: [Chipscope 16-241] No debug cores found in the current design.
+Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
+or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
+Command: place_design -directive RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
+
+Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 1.2 Build Placer Netlist Model
+Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 1.3 Constrain Clocks/Macros
+Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 1 Placer Initialization | Checksum: f331096b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 2 Global Placement
+Phase 2 Global Placement | Checksum: 7e244a0f
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.5 Timing Path Optimizer
+Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 3 Detail Placement | Checksum: 1c30709cd
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
+Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.3 Placer Reporting
+Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+
+Phase 4.4 Final Placement Cleanup
+Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Ending Placer Task | Checksum: dd20239e
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
+INFO: [Common 17-83] Releasing license: Implementation
+41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
+report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
+Command: route_design -directive RuntimeOptimized
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
+
+Phase 1 Build RT Design
+Phase 1 Build RT Design | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2 Router Initialization
+
+Phase 2.1 Create Timer
+Phase 2.1 Create Timer | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2.2 Fix Topology Constraints
+Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 2.3 Pre Route Cleanup
+Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
+ Number of Nodes with overlaps = 0
+
+Phase 2.4 Update Timing
+Phase 2.4 Update Timing | Checksum: 111c71c3e
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
+
+Phase 2 Router Initialization | Checksum: 1ee683561
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 3 Initial Routing
+Phase 3 Initial Routing | Checksum: 10e02a291
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 107
+ Number of Nodes with overlaps = 0
+
+Phase 4.1.1 Update Timing
+Phase 4.1.1 Update Timing | Checksum: da308246
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 4.2 Global Iteration 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+
+Phase 4.2.1 Update Timing
+Phase 4.2.1 Update Timing | Checksum: 1185cfc05
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 16251cbd9
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
+
+Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Phase 6 Post Hold Fix | Checksum: 12245b0d3
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.234075 %
+  Global Horizontal Routing Utilization  = 0.228267 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 7 Route finalize | Checksum: 1af3f3601
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1af3f3601
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 15d59118d
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: 15d59118d
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
+
+*** Running vivado
+    with args -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+
+
+****** Vivado v2016.4 (64-bit)
+  **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+
+source GPIO_demo.tcl -notrace
+Command: open_checkpoint GPIO_demo_routed.dcp
+
+Starting open_checkpoint Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2016.4
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
+Reading XDEF placement.
+Reading placer database...
+Reading XDEF routing.
+Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
+Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
+open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
+Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command write_bitstream
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado 12-3199] DRC finished with 0 Errors
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Bitstream compression saved 13383552 bits.
+Writing bitstream ./GPIO_demo.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
+INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
+INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...
diff --git a/proj/GPIO.runs/impl_1/runme.sh b/proj/GPIO.runs/impl_1/runme.sh
new file mode 100644
index 0000000..192dd80
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/runme.sh
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin
+else
+  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+# pre-commands:
+/bin/touch .write_bitstream.begin.rst
+EAStep vivado -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+
+
diff --git a/proj/GPIO.runs/impl_1/usage_statistics_webtalk.html b/proj/GPIO.runs/impl_1/usage_statistics_webtalk.html
new file mode 100644
index 0000000..32c71a8
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/usage_statistics_webtalk.html
@@ -0,0 +1,506 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
+  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>1756540</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Fri Apr 09 23:19:55 2021</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2016.4 (64-bit)</TD>
+  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>0138f6f78b4b4ef3a03837b84ae3d333</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
+  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
+  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>cpg236</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz</TD>
+  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2592 MHz</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
+  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
+<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
+<TR ALIGN='LEFT'>   <TD>runbitgen=1</TD>
+   <TD>runimplementation=1</TD>
+   <TD>runsynthesis=1</TD>
+</TR>  </TABLE>
+  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
+<TR ALIGN='LEFT'>   <TD>guimode=1</TD>
+</TR>  </TABLE>
+</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
+<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
+   <TD>core_container=false</TD>
+   <TD>currentimplrun=impl_1</TD>
+   <TD>currentsynthesisrun=synth_1</TD>
+</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
+   <TD>designmode=RTL</TD>
+   <TD>export_simulation_activehdl=0</TD>
+   <TD>export_simulation_ies=0</TD>
+</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=0</TD>
+   <TD>export_simulation_questa=0</TD>
+   <TD>export_simulation_riviera=0</TD>
+   <TD>export_simulation_vcs=0</TD>
+</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=0</TD>
+   <TD>implstrategy=Vivado Implementation Defaults</TD>
+   <TD>launch_simulation_activehdl=0</TD>
+   <TD>launch_simulation_ies=0</TD>
+</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
+   <TD>launch_simulation_questa=0</TD>
+   <TD>launch_simulation_riviera=0</TD>
+   <TD>launch_simulation_vcs=0</TD>
+</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
+   <TD>simulator_language=Mixed</TD>
+   <TD>srcsetcount=9</TD>
+   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
+</TR><TR ALIGN='LEFT'>   <TD>target_language=VHDL</TD>
+   <TD>target_simulator=XSim</TD>
+   <TD>totalimplruns=1</TD>
+   <TD>totalsynthesisruns=1</TD>
+</TR>  </TABLE>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
+    <TD>carry4=132</TD>
+    <TD>fdre=579</TD>
+    <TD>fdse=2</TD>
+</TR><TR ALIGN='LEFT'>    <TD>gnd=8</TD>
+    <TD>ibuf=24</TD>
+    <TD>lut1=368</TD>
+    <TD>lut2=207</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut3=91</TD>
+    <TD>lut4=138</TD>
+    <TD>lut5=73</TD>
+    <TD>lut6=157</TD>
+</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv=1</TD>
+    <TD>muxf7=3</TD>
+    <TD>obuf=43</TD>
+    <TD>obuft=2</TD>
+</TR><TR ALIGN='LEFT'>    <TD>vcc=8</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
+    <TD>carry4=132</TD>
+    <TD>fdre=579</TD>
+    <TD>fdse=2</TD>
+</TR><TR ALIGN='LEFT'>    <TD>gnd=8</TD>
+    <TD>ibuf=22</TD>
+    <TD>iobuf=2</TD>
+    <TD>lut1=368</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut2=207</TD>
+    <TD>lut3=91</TD>
+    <TD>lut4=138</TD>
+    <TD>lut5=73</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut6=157</TD>
+    <TD>mmcme2_adv=1</TD>
+    <TD>muxf7=3</TD>
+    <TD>obuf=43</TD>
+</TR><TR ALIGN='LEFT'>    <TD>vcc=8</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v5_1/1</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>clkin1_period=10.0</TD>
+    <TD>clkin2_period=10.0</TD>
+    <TD>clock_mgr_type=NA</TD>
+    <TD>component_name=clk_wiz_0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
+    <TD>enable_axi=0</TD>
+    <TD>feedback_source=FDBK_AUTO</TD>
+    <TD>feedback_type=SINGLE</TD>
+</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
+    <TD>manual_override=false</TD>
+    <TD>num_out_clk=1</TD>
+    <TD>primitive=MMCM</TD>
+</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
+    <TD>use_dyn_reconfig=false</TD>
+    <TD>use_inclk_stopped=false</TD>
+    <TD>use_inclk_switchover=false</TD>
+</TR><TR ALIGN='LEFT'>    <TD>use_locked=false</TD>
+    <TD>use_max_i_jitter=false</TD>
+    <TD>use_min_o_jitter=false</TD>
+    <TD>use_phase_alignment=true</TD>
+</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
+    <TD>use_reset=false</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
+    <TD>-checks=default::[not_specified]</TD>
+    <TD>-fail_on=default::[not_specified]</TD>
+    <TD>-force=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
+    <TD>-messages=default::[not_specified]</TD>
+    <TD>-name=default::[not_specified]</TD>
+    <TD>-return_string=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
+    <TD>-upgrade_cw=default::[not_specified]</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
+    <TD>bufgctrl_fixed=0</TD>
+    <TD>bufgctrl_used=3</TD>
+    <TD>bufgctrl_util_percentage=9.38</TD>
+</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=72</TD>
+    <TD>bufhce_fixed=0</TD>
+    <TD>bufhce_used=0</TD>
+    <TD>bufhce_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>bufio_available=20</TD>
+    <TD>bufio_fixed=0</TD>
+    <TD>bufio_used=0</TD>
+    <TD>bufio_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=10</TD>
+    <TD>bufmrce_fixed=0</TD>
+    <TD>bufmrce_used=0</TD>
+    <TD>bufmrce_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>bufr_available=20</TD>
+    <TD>bufr_fixed=0</TD>
+    <TD>bufr_used=0</TD>
+    <TD>bufr_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=5</TD>
+    <TD>mmcme2_adv_fixed=0</TD>
+    <TD>mmcme2_adv_used=1</TD>
+    <TD>mmcme2_adv_util_percentage=20.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=5</TD>
+    <TD>plle2_adv_fixed=0</TD>
+    <TD>plle2_adv_used=0</TD>
+    <TD>plle2_adv_util_percentage=0.00</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>dsps_available=90</TD>
+    <TD>dsps_fixed=0</TD>
+    <TD>dsps_used=0</TD>
+    <TD>dsps_util_percentage=0.00</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
+    <TD>diff_hstl_i=0</TD>
+    <TD>diff_hstl_i_18=0</TD>
+    <TD>diff_hstl_ii=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
+    <TD>diff_hsul_12=0</TD>
+    <TD>diff_mobile_ddr=0</TD>
+    <TD>diff_sstl135=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
+    <TD>diff_sstl15=0</TD>
+    <TD>diff_sstl15_r=0</TD>
+    <TD>diff_sstl18_i=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
+    <TD>hstl_i=0</TD>
+    <TD>hstl_i_18=0</TD>
+    <TD>hstl_ii=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
+    <TD>hsul_12=0</TD>
+    <TD>lvcmos12=0</TD>
+    <TD>lvcmos15=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
+    <TD>lvcmos25=0</TD>
+    <TD>lvcmos33=1</TD>
+    <TD>lvds_25=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
+    <TD>mini_lvds_25=0</TD>
+    <TD>mobile_ddr=0</TD>
+    <TD>pci33_3=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
+    <TD>rsds_25=0</TD>
+    <TD>sstl135=0</TD>
+    <TD>sstl135_r=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
+    <TD>sstl15_r=0</TD>
+    <TD>sstl18_i=0</TD>
+    <TD>sstl18_ii=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=50</TD>
+    <TD>block_ram_tile_fixed=0</TD>
+    <TD>block_ram_tile_used=0</TD>
+    <TD>block_ram_tile_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=100</TD>
+    <TD>ramb18_fixed=0</TD>
+    <TD>ramb18_used=0</TD>
+    <TD>ramb18_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=50</TD>
+    <TD>ramb36_fifo_fixed=0</TD>
+    <TD>ramb36_fifo_used=0</TD>
+    <TD>ramb36_fifo_util_percentage=0.00</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
+    <TD>bufg_used=3</TD>
+    <TD>carry4_functional_category=CarryLogic</TD>
+    <TD>carry4_used=132</TD>
+</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
+    <TD>fdre_used=576</TD>
+    <TD>fdse_functional_category=Flop &amp; Latch</TD>
+    <TD>fdse_used=2</TD>
+</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
+    <TD>ibuf_used=24</TD>
+    <TD>lut1_functional_category=LUT</TD>
+    <TD>lut1_used=30</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
+    <TD>lut2_used=207</TD>
+    <TD>lut3_functional_category=LUT</TD>
+    <TD>lut3_used=93</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
+    <TD>lut4_used=136</TD>
+    <TD>lut5_functional_category=LUT</TD>
+    <TD>lut5_used=72</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
+    <TD>lut6_used=157</TD>
+    <TD>mmcme2_adv_functional_category=Clock</TD>
+    <TD>mmcme2_adv_used=1</TD>
+</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
+    <TD>muxf7_used=3</TD>
+    <TD>obuf_functional_category=IO</TD>
+    <TD>obuf_used=43</TD>
+</TR><TR ALIGN='LEFT'>    <TD>obuft_functional_category=IO</TD>
+    <TD>obuft_used=2</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>f7_muxes_available=16300</TD>
+    <TD>f7_muxes_fixed=0</TD>
+    <TD>f7_muxes_used=3</TD>
+    <TD>f7_muxes_util_percentage=0.02</TD>
+</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=8150</TD>
+    <TD>f8_muxes_fixed=0</TD>
+    <TD>f8_muxes_used=0</TD>
+    <TD>f8_muxes_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=20800</TD>
+    <TD>lut_as_logic_fixed=0</TD>
+    <TD>lut_as_logic_used=564</TD>
+    <TD>lut_as_logic_util_percentage=2.71</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=9600</TD>
+    <TD>lut_as_memory_fixed=0</TD>
+    <TD>lut_as_memory_used=0</TD>
+    <TD>lut_as_memory_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=41600</TD>
+    <TD>register_as_flip_flop_fixed=0</TD>
+    <TD>register_as_flip_flop_used=578</TD>
+    <TD>register_as_flip_flop_util_percentage=1.39</TD>
+</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=41600</TD>
+    <TD>register_as_latch_fixed=0</TD>
+    <TD>register_as_latch_used=0</TD>
+    <TD>register_as_latch_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=20800</TD>
+    <TD>slice_luts_fixed=0</TD>
+    <TD>slice_luts_used=564</TD>
+    <TD>slice_luts_util_percentage=2.71</TD>
+</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=41600</TD>
+    <TD>slice_registers_fixed=0</TD>
+    <TD>slice_registers_used=578</TD>
+    <TD>slice_registers_util_percentage=1.39</TD>
+</TR><TR ALIGN='LEFT'>    <TD>fully_used_lut_ff_pairs_fixed=1.39</TD>
+    <TD>fully_used_lut_ff_pairs_used=54</TD>
+    <TD>lut_as_distributed_ram_fixed=0</TD>
+    <TD>lut_as_distributed_ram_used=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=20800</TD>
+    <TD>lut_as_logic_fixed=0</TD>
+    <TD>lut_as_logic_used=564</TD>
+    <TD>lut_as_logic_util_percentage=2.71</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=9600</TD>
+    <TD>lut_as_memory_fixed=0</TD>
+    <TD>lut_as_memory_used=0</TD>
+    <TD>lut_as_memory_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
+    <TD>lut_as_shift_register_used=0</TD>
+    <TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=0</TD>
+    <TD>lut_ff_pairs_with_one_unused_flip_flop_used=111</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=111</TD>
+    <TD>lut_ff_pairs_with_one_unused_lut_output_used=110</TD>
+    <TD>lut_flip_flop_pairs_available=20800</TD>
+    <TD>lut_flip_flop_pairs_fixed=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_used=171</TD>
+    <TD>lut_flip_flop_pairs_util_percentage=0.82</TD>
+    <TD>slice_available=8150</TD>
+    <TD>slice_fixed=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>slice_used=282</TD>
+    <TD>slice_util_percentage=3.46</TD>
+    <TD>slicel_fixed=0</TD>
+    <TD>slicel_used=182</TD>
+</TR><TR ALIGN='LEFT'>    <TD>slicem_fixed=0</TD>
+    <TD>slicem_used=100</TD>
+    <TD>unique_control_sets_used=36</TD>
+    <TD>using_o5_and_o6_fixed=36</TD>
+</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=131</TD>
+    <TD>using_o5_output_only_fixed=131</TD>
+    <TD>using_o5_output_only_used=0</TD>
+    <TD>using_o6_output_only_fixed=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=433</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
+    <TD>bscane2_fixed=0</TD>
+    <TD>bscane2_used=0</TD>
+    <TD>bscane2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
+    <TD>capturee2_fixed=0</TD>
+    <TD>capturee2_used=0</TD>
+    <TD>capturee2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
+    <TD>dna_port_fixed=0</TD>
+    <TD>dna_port_used=0</TD>
+    <TD>dna_port_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
+    <TD>efuse_usr_fixed=0</TD>
+    <TD>efuse_usr_used=0</TD>
+    <TD>efuse_usr_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
+    <TD>frame_ecce2_fixed=0</TD>
+    <TD>frame_ecce2_used=0</TD>
+    <TD>frame_ecce2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
+    <TD>icape2_fixed=0</TD>
+    <TD>icape2_used=0</TD>
+    <TD>icape2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
+    <TD>pcie_2_1_fixed=0</TD>
+    <TD>pcie_2_1_used=0</TD>
+    <TD>pcie_2_1_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
+    <TD>startupe2_fixed=0</TD>
+    <TD>startupe2_used=0</TD>
+    <TD>startupe2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
+    <TD>xadc_fixed=0</TD>
+    <TD>xadc_used=0</TD>
+    <TD>xadc_util_percentage=0.00</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>actual_expansions=695075</TD>
+    <TD>bogomips=0</TD>
+    <TD>bram18=0</TD>
+    <TD>bram36=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
+    <TD>bufr=0</TD>
+    <TD>congestion_level=0</TD>
+    <TD>ctrls=36</TD>
+</TR><TR ALIGN='LEFT'>    <TD>dsp=0</TD>
+    <TD>effort=2</TD>
+    <TD>estimated_expansions=723384</TD>
+    <TD>ff=578</TD>
+</TR><TR ALIGN='LEFT'>    <TD>global_clocks=3</TD>
+    <TD>high_fanout_nets=0</TD>
+    <TD>iob=67</TD>
+    <TD>lut=609</TD>
+</TR><TR ALIGN='LEFT'>    <TD>movable_instances=1499</TD>
+    <TD>nets=1904</TD>
+    <TD>pins=8775</TD>
+    <TD>pll=0</TD>
+</TR><TR ALIGN='LEFT'>    <TD>router_runtime=0.000000</TD>
+    <TD>router_timing_driven=1</TD>
+    <TD>threads=2</TD>
+    <TD>timing_constraints_exist=1</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
+    <TD>-bufg=default::12</TD>
+    <TD>-cascade_dsp=default::auto</TD>
+    <TD>-constrset=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
+    <TD>-directive=RuntimeOptimized</TD>
+    <TD>-fanout_limit=default::10000</TD>
+    <TD>-flatten_hierarchy=none</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=off</TD>
+    <TD>-gated_clock_conversion=default::off</TD>
+    <TD>-generic=default::[not_specified]</TD>
+    <TD>-include_dirs=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
+    <TD>-max_bram=default::-1</TD>
+    <TD>-max_bram_cascade_height=default::-1</TD>
+    <TD>-max_dsp=default::-1</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
+    <TD>-max_uram_cascade_height=default::-1</TD>
+    <TD>-mode=default::default</TD>
+    <TD>-name=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
+    <TD>-no_srlextract=default::[not_specified]</TD>
+    <TD>-no_timing_driven=default::[not_specified]</TD>
+    <TD>-part=xc7a35tcpg236-1</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
+    <TD>-retiming=default::[not_specified]</TD>
+    <TD>-rtl=default::[not_specified]</TD>
+    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
+    <TD>-seu_protect=default::none</TD>
+    <TD>-shreg_min_size=default::3</TD>
+    <TD>-top=GPIO_demo</TD>
+</TR><TR ALIGN='LEFT'>    <TD>-verilog_define=default::[not_specified]</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>elapsed=00:00:34s</TD>
+    <TD>hls_ip=0</TD>
+    <TD>memory_gain=424.176MB</TD>
+    <TD>memory_peak=692.656MB</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+</BODY>
+</HTML>
diff --git a/proj/GPIO.runs/impl_1/usage_statistics_webtalk.xml b/proj/GPIO.runs/impl_1/usage_statistics_webtalk.xml
new file mode 100644
index 0000000..514a2ab
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/usage_statistics_webtalk.xml
@@ -0,0 +1,453 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<webTalkData  fileName='usage_statistics_webtalk.xml'  majorVersion='1' minorVersion='0' timeStamp='Fri Apr 09 23:19:55 2021'>
+<section name="__ROOT__" level="0" order="1" description="">
+ <section name="software_version_and_target_device" level="1" order="1" description="">
+  <keyValuePair key="beta" value="FALSE" description="" />
+  <keyValuePair key="build_version" value="1756540" description="" />
+  <keyValuePair key="date_generated" value="Fri Apr 09 23:19:55 2021" description="" />
+  <keyValuePair key="os_platform" value="WIN64" description="" />
+  <keyValuePair key="product_version" value="Vivado v2016.4 (64-bit)" description="" />
+  <keyValuePair key="project_id" value="0138f6f78b4b4ef3a03837b84ae3d333" description="" />
+  <keyValuePair key="project_iteration" value="1" description="" />
+  <keyValuePair key="random_id" value="89e526329a235cb691995f8457477284" description="" />
+  <keyValuePair key="registration_id" value="89e526329a235cb691995f8457477284" description="" />
+  <keyValuePair key="route_design" value="TRUE" description="" />
+  <keyValuePair key="target_device" value="xc7a35t" description="" />
+  <keyValuePair key="target_family" value="artix7" description="" />
+  <keyValuePair key="target_package" value="cpg236" description="" />
+  <keyValuePair key="target_speed" value="-1" description="" />
+  <keyValuePair key="tool_flow" value="Vivado" description="" />
+ </section>
+ <section name="user_environment" level="1" order="2" description="">
+  <keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz" description="" />
+  <keyValuePair key="cpu_speed" value="2592 MHz" description="" />
+  <keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
+  <keyValuePair key="os_release" value="major release  (build 9200)" description="" />
+  <keyValuePair key="system_ram" value="8.000 GB" description="" />
+  <keyValuePair key="total_processors" value="1" description="" />
+ </section>
+ <section name="ip_statistics" level="1" order="3" description="">
+  <section name="clk_wiz_v5_1/1" level="2" order="1" description="">
+   <keyValuePair key="clkin1_period" value="10.0" description="" />
+   <keyValuePair key="clkin2_period" value="10.0" description="" />
+   <keyValuePair key="clock_mgr_type" value="NA" description="" />
+   <keyValuePair key="component_name" value="clk_wiz_0" description="" />
+   <keyValuePair key="core_container" value="NA" description="" />
+   <keyValuePair key="enable_axi" value="0" description="" />
+   <keyValuePair key="feedback_source" value="FDBK_AUTO" description="" />
+   <keyValuePair key="feedback_type" value="SINGLE" description="" />
+   <keyValuePair key="iptotal" value="1" description="" />
+   <keyValuePair key="manual_override" value="false" description="" />
+   <keyValuePair key="num_out_clk" value="1" description="" />
+   <keyValuePair key="primitive" value="MMCM" description="" />
+   <keyValuePair key="use_dyn_phase_shift" value="false" description="" />
+   <keyValuePair key="use_dyn_reconfig" value="false" description="" />
+   <keyValuePair key="use_inclk_stopped" value="false" description="" />
+   <keyValuePair key="use_inclk_switchover" value="false" description="" />
+   <keyValuePair key="use_locked" value="false" description="" />
+   <keyValuePair key="use_max_i_jitter" value="false" description="" />
+   <keyValuePair key="use_min_o_jitter" value="false" description="" />
+   <keyValuePair key="use_phase_alignment" value="true" description="" />
+   <keyValuePair key="use_power_down" value="false" description="" />
+   <keyValuePair key="use_reset" value="false" description="" />
+  </section>
+ </section>
+ <section name="report_drc" level="1" order="4" description="">
+  <section name="command_line_options" level="2" order="1" description="">
+   <keyValuePair key="-append" value="default::[not_specified]" description="" />
+   <keyValuePair key="-checks" value="default::[not_specified]" description="" />
+   <keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
+   <keyValuePair key="-force" value="default::[not_specified]" description="" />
+   <keyValuePair key="-format" value="default::[not_specified]" description="" />
+   <keyValuePair key="-messages" value="default::[not_specified]" description="" />
+   <keyValuePair key="-name" value="default::[not_specified]" description="" />
+   <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
+   <keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
+   <keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
+  </section>
+ </section>
+ <section name="report_utilization" level="1" order="5" description="">
+  <section name="clocking" level="2" order="1" description="">
+   <keyValuePair key="bufgctrl_available" value="32" description="" />
+   <keyValuePair key="bufgctrl_fixed" value="0" description="" />
+   <keyValuePair key="bufgctrl_used" value="3" description="" />
+   <keyValuePair key="bufgctrl_util_percentage" value="9.38" description="" />
+   <keyValuePair key="bufhce_available" value="72" description="" />
+   <keyValuePair key="bufhce_fixed" value="0" description="" />
+   <keyValuePair key="bufhce_used" value="0" description="" />
+   <keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
+   <keyValuePair key="bufio_available" value="20" description="" />
+   <keyValuePair key="bufio_fixed" value="0" description="" />
+   <keyValuePair key="bufio_used" value="0" description="" />
+   <keyValuePair key="bufio_util_percentage" value="0.00" description="" />
+   <keyValuePair key="bufmrce_available" value="10" description="" />
+   <keyValuePair key="bufmrce_fixed" value="0" description="" />
+   <keyValuePair key="bufmrce_used" value="0" description="" />
+   <keyValuePair key="bufmrce_util_percentage" value="0.00" description="" />
+   <keyValuePair key="bufr_available" value="20" description="" />
+   <keyValuePair key="bufr_fixed" value="0" description="" />
+   <keyValuePair key="bufr_used" value="0" description="" />
+   <keyValuePair key="bufr_util_percentage" value="0.00" description="" />
+   <keyValuePair key="mmcme2_adv_available" value="5" description="" />
+   <keyValuePair key="mmcme2_adv_fixed" value="0" description="" />
+   <keyValuePair key="mmcme2_adv_used" value="1" description="" />
+   <keyValuePair key="mmcme2_adv_util_percentage" value="20.00" description="" />
+   <keyValuePair key="plle2_adv_available" value="5" description="" />
+   <keyValuePair key="plle2_adv_fixed" value="0" description="" />
+   <keyValuePair key="plle2_adv_used" value="0" description="" />
+   <keyValuePair key="plle2_adv_util_percentage" value="0.00" description="" />
+  </section>
+  <section name="dsp" level="2" order="2" description="">
+   <keyValuePair key="dsps_available" value="90" description="" />
+   <keyValuePair key="dsps_fixed" value="0" description="" />
+   <keyValuePair key="dsps_used" value="0" description="" />
+   <keyValuePair key="dsps_util_percentage" value="0.00" description="" />
+  </section>
+  <section name="io_standard" level="2" order="3" description="">
+   <keyValuePair key="blvds_25" value="0" description="" />
+   <keyValuePair key="diff_hstl_i" value="0" description="" />
+   <keyValuePair key="diff_hstl_i_18" value="0" description="" />
+   <keyValuePair key="diff_hstl_ii" value="0" description="" />
+   <keyValuePair key="diff_hstl_ii_18" value="0" description="" />
+   <keyValuePair key="diff_hsul_12" value="0" description="" />
+   <keyValuePair key="diff_mobile_ddr" value="0" description="" />
+   <keyValuePair key="diff_sstl135" value="0" description="" />
+   <keyValuePair key="diff_sstl135_r" value="0" description="" />
+   <keyValuePair key="diff_sstl15" value="0" description="" />
+   <keyValuePair key="diff_sstl15_r" value="0" description="" />
+   <keyValuePair key="diff_sstl18_i" value="0" description="" />
+   <keyValuePair key="diff_sstl18_ii" value="0" description="" />
+   <keyValuePair key="hstl_i" value="0" description="" />
+   <keyValuePair key="hstl_i_18" value="0" description="" />
+   <keyValuePair key="hstl_ii" value="0" description="" />
+   <keyValuePair key="hstl_ii_18" value="0" description="" />
+   <keyValuePair key="hsul_12" value="0" description="" />
+   <keyValuePair key="lvcmos12" value="0" description="" />
+   <keyValuePair key="lvcmos15" value="0" description="" />
+   <keyValuePair key="lvcmos18" value="0" description="" />
+   <keyValuePair key="lvcmos25" value="0" description="" />
+   <keyValuePair key="lvcmos33" value="1" description="" />
+   <keyValuePair key="lvds_25" value="0" description="" />
+   <keyValuePair key="lvttl" value="0" description="" />
+   <keyValuePair key="mini_lvds_25" value="0" description="" />
+   <keyValuePair key="mobile_ddr" value="0" description="" />
+   <keyValuePair key="pci33_3" value="0" description="" />
+   <keyValuePair key="ppds_25" value="0" description="" />
+   <keyValuePair key="rsds_25" value="0" description="" />
+   <keyValuePair key="sstl135" value="0" description="" />
+   <keyValuePair key="sstl135_r" value="0" description="" />
+   <keyValuePair key="sstl15" value="0" description="" />
+   <keyValuePair key="sstl15_r" value="0" description="" />
+   <keyValuePair key="sstl18_i" value="0" description="" />
+   <keyValuePair key="sstl18_ii" value="0" description="" />
+   <keyValuePair key="tmds_33" value="0" description="" />
+  </section>
+  <section name="memory" level="2" order="4" description="">
+   <keyValuePair key="block_ram_tile_available" value="50" description="" />
+   <keyValuePair key="block_ram_tile_fixed" value="0" description="" />
+   <keyValuePair key="block_ram_tile_used" value="0" description="" />
+   <keyValuePair key="block_ram_tile_util_percentage" value="0.00" description="" />
+   <keyValuePair key="ramb18_available" value="100" description="" />
+   <keyValuePair key="ramb18_fixed" value="0" description="" />
+   <keyValuePair key="ramb18_used" value="0" description="" />
+   <keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
+   <keyValuePair key="ramb36_fifo_available" value="50" description="" />
+   <keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
+   <keyValuePair key="ramb36_fifo_used" value="0" description="" />
+   <keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
+  </section>
+  <section name="primitives" level="2" order="5" description="">
+   <keyValuePair key="bufg_functional_category" value="Clock" description="" />
+   <keyValuePair key="bufg_used" value="3" description="" />
+   <keyValuePair key="carry4_functional_category" value="CarryLogic" description="" />
+   <keyValuePair key="carry4_used" value="132" description="" />
+   <keyValuePair key="fdre_functional_category" value="Flop &amp; Latch" description="" />
+   <keyValuePair key="fdre_used" value="576" description="" />
+   <keyValuePair key="fdse_functional_category" value="Flop &amp; Latch" description="" />
+   <keyValuePair key="fdse_used" value="2" description="" />
+   <keyValuePair key="ibuf_functional_category" value="IO" description="" />
+   <keyValuePair key="ibuf_used" value="24" description="" />
+   <keyValuePair key="lut1_functional_category" value="LUT" description="" />
+   <keyValuePair key="lut1_used" value="30" description="" />
+   <keyValuePair key="lut2_functional_category" value="LUT" description="" />
+   <keyValuePair key="lut2_used" value="207" description="" />
+   <keyValuePair key="lut3_functional_category" value="LUT" description="" />
+   <keyValuePair key="lut3_used" value="93" description="" />
+   <keyValuePair key="lut4_functional_category" value="LUT" description="" />
+   <keyValuePair key="lut4_used" value="136" description="" />
+   <keyValuePair key="lut5_functional_category" value="LUT" description="" />
+   <keyValuePair key="lut5_used" value="72" description="" />
+   <keyValuePair key="lut6_functional_category" value="LUT" description="" />
+   <keyValuePair key="lut6_used" value="157" description="" />
+   <keyValuePair key="mmcme2_adv_functional_category" value="Clock" description="" />
+   <keyValuePair key="mmcme2_adv_used" value="1" description="" />
+   <keyValuePair key="muxf7_functional_category" value="MuxFx" description="" />
+   <keyValuePair key="muxf7_used" value="3" description="" />
+   <keyValuePair key="obuf_functional_category" value="IO" description="" />
+   <keyValuePair key="obuf_used" value="43" description="" />
+   <keyValuePair key="obuft_functional_category" value="IO" description="" />
+   <keyValuePair key="obuft_used" value="2" description="" />
+  </section>
+  <section name="slice_logic" level="2" order="6" description="">
+   <keyValuePair key="f7_muxes_available" value="16300" description="" />
+   <keyValuePair key="f7_muxes_fixed" value="0" description="" />
+   <keyValuePair key="f7_muxes_used" value="3" description="" />
+   <keyValuePair key="f7_muxes_util_percentage" value="0.02" description="" />
+   <keyValuePair key="f8_muxes_available" value="8150" description="" />
+   <keyValuePair key="f8_muxes_fixed" value="0" description="" />
+   <keyValuePair key="f8_muxes_used" value="0" description="" />
+   <keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
+   <keyValuePair key="fully_used_lut_ff_pairs_fixed" value="1.39" description="" />
+   <keyValuePair key="fully_used_lut_ff_pairs_used" value="54" description="" />
+   <keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
+   <keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
+   <keyValuePair key="lut_as_logic_available" value="20800" description="" />
+   <keyValuePair key="lut_as_logic_available" value="20800" description="" />
+   <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
+   <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
+   <keyValuePair key="lut_as_logic_used" value="564" description="" />
+   <keyValuePair key="lut_as_logic_used" value="564" description="" />
+   <keyValuePair key="lut_as_logic_util_percentage" value="2.71" description="" />
+   <keyValuePair key="lut_as_logic_util_percentage" value="2.71" description="" />
+   <keyValuePair key="lut_as_memory_available" value="9600" description="" />
+   <keyValuePair key="lut_as_memory_available" value="9600" description="" />
+   <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
+   <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
+   <keyValuePair key="lut_as_memory_used" value="0" description="" />
+   <keyValuePair key="lut_as_memory_used" value="0" description="" />
+   <keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
+   <keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
+   <keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
+   <keyValuePair key="lut_as_shift_register_used" value="0" description="" />
+   <keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_fixed" value="0" description="" />
+   <keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_used" value="111" description="" />
+   <keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_fixed" value="111" description="" />
+   <keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_used" value="110" description="" />
+   <keyValuePair key="lut_flip_flop_pairs_available" value="20800" description="" />
+   <keyValuePair key="lut_flip_flop_pairs_fixed" value="0" description="" />
+   <keyValuePair key="lut_flip_flop_pairs_used" value="171" description="" />
+   <keyValuePair key="lut_flip_flop_pairs_util_percentage" value="0.82" description="" />
+   <keyValuePair key="register_as_flip_flop_available" value="41600" description="" />
+   <keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
+   <keyValuePair key="register_as_flip_flop_used" value="578" description="" />
+   <keyValuePair key="register_as_flip_flop_util_percentage" value="1.39" description="" />
+   <keyValuePair key="register_as_latch_available" value="41600" description="" />
+   <keyValuePair key="register_as_latch_fixed" value="0" description="" />
+   <keyValuePair key="register_as_latch_used" value="0" description="" />
+   <keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
+   <keyValuePair key="slice_available" value="8150" description="" />
+   <keyValuePair key="slice_fixed" value="0" description="" />
+   <keyValuePair key="slice_luts_available" value="20800" description="" />
+   <keyValuePair key="slice_luts_fixed" value="0" description="" />
+   <keyValuePair key="slice_luts_used" value="564" description="" />
+   <keyValuePair key="slice_luts_util_percentage" value="2.71" description="" />
+   <keyValuePair key="slice_registers_available" value="41600" description="" />
+   <keyValuePair key="slice_registers_fixed" value="0" description="" />
+   <keyValuePair key="slice_registers_used" value="578" description="" />
+   <keyValuePair key="slice_registers_util_percentage" value="1.39" description="" />
+   <keyValuePair key="slice_used" value="282" description="" />
+   <keyValuePair key="slice_util_percentage" value="3.46" description="" />
+   <keyValuePair key="slicel_fixed" value="0" description="" />
+   <keyValuePair key="slicel_used" value="182" description="" />
+   <keyValuePair key="slicem_fixed" value="0" description="" />
+   <keyValuePair key="slicem_used" value="100" description="" />
+   <keyValuePair key="unique_control_sets_used" value="36" description="" />
+   <keyValuePair key="using_o5_and_o6_fixed" value="36" description="" />
+   <keyValuePair key="using_o5_and_o6_used" value="131" description="" />
+   <keyValuePair key="using_o5_output_only_fixed" value="131" description="" />
+   <keyValuePair key="using_o5_output_only_used" value="0" description="" />
+   <keyValuePair key="using_o6_output_only_fixed" value="0" description="" />
+   <keyValuePair key="using_o6_output_only_used" value="433" description="" />
+  </section>
+  <section name="specific_feature" level="2" order="7" description="">
+   <keyValuePair key="bscane2_available" value="4" description="" />
+   <keyValuePair key="bscane2_fixed" value="0" description="" />
+   <keyValuePair key="bscane2_used" value="0" description="" />
+   <keyValuePair key="bscane2_util_percentage" value="0.00" description="" />
+   <keyValuePair key="capturee2_available" value="1" description="" />
+   <keyValuePair key="capturee2_fixed" value="0" description="" />
+   <keyValuePair key="capturee2_used" value="0" description="" />
+   <keyValuePair key="capturee2_util_percentage" value="0.00" description="" />
+   <keyValuePair key="dna_port_available" value="1" description="" />
+   <keyValuePair key="dna_port_fixed" value="0" description="" />
+   <keyValuePair key="dna_port_used" value="0" description="" />
+   <keyValuePair key="dna_port_util_percentage" value="0.00" description="" />
+   <keyValuePair key="efuse_usr_available" value="1" description="" />
+   <keyValuePair key="efuse_usr_fixed" value="0" description="" />
+   <keyValuePair key="efuse_usr_used" value="0" description="" />
+   <keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
+   <keyValuePair key="frame_ecce2_available" value="1" description="" />
+   <keyValuePair key="frame_ecce2_fixed" value="0" description="" />
+   <keyValuePair key="frame_ecce2_used" value="0" description="" />
+   <keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
+   <keyValuePair key="icape2_available" value="2" description="" />
+   <keyValuePair key="icape2_fixed" value="0" description="" />
+   <keyValuePair key="icape2_used" value="0" description="" />
+   <keyValuePair key="icape2_util_percentage" value="0.00" description="" />
+   <keyValuePair key="pcie_2_1_available" value="1" description="" />
+   <keyValuePair key="pcie_2_1_fixed" value="0" description="" />
+   <keyValuePair key="pcie_2_1_used" value="0" description="" />
+   <keyValuePair key="pcie_2_1_util_percentage" value="0.00" description="" />
+   <keyValuePair key="startupe2_available" value="1" description="" />
+   <keyValuePair key="startupe2_fixed" value="0" description="" />
+   <keyValuePair key="startupe2_used" value="0" description="" />
+   <keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
+   <keyValuePair key="xadc_available" value="1" description="" />
+   <keyValuePair key="xadc_fixed" value="0" description="" />
+   <keyValuePair key="xadc_used" value="0" description="" />
+   <keyValuePair key="xadc_util_percentage" value="0.00" description="" />
+  </section>
+ </section>
+ <section name="router" level="1" order="6" description="">
+  <section name="usage" level="2" order="1" description="">
+   <keyValuePair key="actual_expansions" value="695075" description="" />
+   <keyValuePair key="bogomips" value="0" description="" />
+   <keyValuePair key="bram18" value="0" description="" />
+   <keyValuePair key="bram36" value="0" description="" />
+   <keyValuePair key="bufg" value="0" description="" />
+   <keyValuePair key="bufr" value="0" description="" />
+   <keyValuePair key="congestion_level" value="0" description="" />
+   <keyValuePair key="ctrls" value="36" description="" />
+   <keyValuePair key="dsp" value="0" description="" />
+   <keyValuePair key="effort" value="2" description="" />
+   <keyValuePair key="estimated_expansions" value="723384" description="" />
+   <keyValuePair key="ff" value="578" description="" />
+   <keyValuePair key="global_clocks" value="3" description="" />
+   <keyValuePair key="high_fanout_nets" value="0" description="" />
+   <keyValuePair key="iob" value="67" description="" />
+   <keyValuePair key="lut" value="609" description="" />
+   <keyValuePair key="movable_instances" value="1499" description="" />
+   <keyValuePair key="nets" value="1904" description="" />
+   <keyValuePair key="pins" value="8775" description="" />
+   <keyValuePair key="pll" value="0" description="" />
+   <keyValuePair key="router_runtime" value="0.000000" description="" />
+   <keyValuePair key="router_timing_driven" value="1" description="" />
+   <keyValuePair key="threads" value="2" description="" />
+   <keyValuePair key="timing_constraints_exist" value="1" description="" />
+  </section>
+ </section>
+ <section name="synthesis" level="1" order="7" description="">
+  <section name="command_line_options" level="2" order="1" description="">
+   <keyValuePair key="-assert" value="default::[not_specified]" description="" />
+   <keyValuePair key="-bufg" value="default::12" description="" />
+   <keyValuePair key="-cascade_dsp" value="default::auto" description="" />
+   <keyValuePair key="-constrset" value="default::[not_specified]" description="" />
+   <keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
+   <keyValuePair key="-directive" value="RuntimeOptimized" description="" />
+   <keyValuePair key="-fanout_limit" value="default::10000" description="" />
+   <keyValuePair key="-flatten_hierarchy" value="none" description="" />
+   <keyValuePair key="-fsm_extraction" value="off" description="" />
+   <keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
+   <keyValuePair key="-generic" value="default::[not_specified]" description="" />
+   <keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
+   <keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
+   <keyValuePair key="-max_bram" value="default::-1" description="" />
+   <keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
+   <keyValuePair key="-max_dsp" value="default::-1" description="" />
+   <keyValuePair key="-max_uram" value="default::-1" description="" />
+   <keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
+   <keyValuePair key="-mode" value="default::default" description="" />
+   <keyValuePair key="-name" value="default::[not_specified]" description="" />
+   <keyValuePair key="-no_lc" value="default::[not_specified]" description="" />
+   <keyValuePair key="-no_srlextract" value="default::[not_specified]" description="" />
+   <keyValuePair key="-no_timing_driven" value="default::[not_specified]" description="" />
+   <keyValuePair key="-part" value="xc7a35tcpg236-1" description="" />
+   <keyValuePair key="-resource_sharing" value="default::auto" description="" />
+   <keyValuePair key="-retiming" value="default::[not_specified]" description="" />
+   <keyValuePair key="-rtl" value="default::[not_specified]" description="" />
+   <keyValuePair key="-rtl_skip_constraints" value="default::[not_specified]" description="" />
+   <keyValuePair key="-rtl_skip_ip" value="default::[not_specified]" description="" />
+   <keyValuePair key="-seu_protect" value="default::none" description="" />
+   <keyValuePair key="-shreg_min_size" value="default::3" description="" />
+   <keyValuePair key="-top" value="GPIO_demo" description="" />
+   <keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
+  </section>
+  <section name="usage" level="2" order="2" description="">
+   <keyValuePair key="elapsed" value="00:00:34s" description="" />
+   <keyValuePair key="hls_ip" value="0" description="" />
+   <keyValuePair key="memory_gain" value="424.176MB" description="" />
+   <keyValuePair key="memory_peak" value="692.656MB" description="" />
+  </section>
+ </section>
+ <section name="unisim_transformation" level="1" order="8" description="">
+  <section name="post_unisim_transformation" level="2" order="1" description="">
+   <keyValuePair key="bufg" value="3" description="" />
+   <keyValuePair key="carry4" value="132" description="" />
+   <keyValuePair key="fdre" value="579" description="" />
+   <keyValuePair key="fdse" value="2" description="" />
+   <keyValuePair key="gnd" value="8" description="" />
+   <keyValuePair key="ibuf" value="24" description="" />
+   <keyValuePair key="lut1" value="368" description="" />
+   <keyValuePair key="lut2" value="207" description="" />
+   <keyValuePair key="lut3" value="91" description="" />
+   <keyValuePair key="lut4" value="138" description="" />
+   <keyValuePair key="lut5" value="73" description="" />
+   <keyValuePair key="lut6" value="157" description="" />
+   <keyValuePair key="mmcme2_adv" value="1" description="" />
+   <keyValuePair key="muxf7" value="3" description="" />
+   <keyValuePair key="obuf" value="43" description="" />
+   <keyValuePair key="obuft" value="2" description="" />
+   <keyValuePair key="vcc" value="8" description="" />
+  </section>
+  <section name="pre_unisim_transformation" level="2" order="2" description="">
+   <keyValuePair key="bufg" value="3" description="" />
+   <keyValuePair key="carry4" value="132" description="" />
+   <keyValuePair key="fdre" value="579" description="" />
+   <keyValuePair key="fdse" value="2" description="" />
+   <keyValuePair key="gnd" value="8" description="" />
+   <keyValuePair key="ibuf" value="22" description="" />
+   <keyValuePair key="iobuf" value="2" description="" />
+   <keyValuePair key="lut1" value="368" description="" />
+   <keyValuePair key="lut2" value="207" description="" />
+   <keyValuePair key="lut3" value="91" description="" />
+   <keyValuePair key="lut4" value="138" description="" />
+   <keyValuePair key="lut5" value="73" description="" />
+   <keyValuePair key="lut6" value="157" description="" />
+   <keyValuePair key="mmcme2_adv" value="1" description="" />
+   <keyValuePair key="muxf7" value="3" description="" />
+   <keyValuePair key="obuf" value="43" description="" />
+   <keyValuePair key="vcc" value="8" description="" />
+  </section>
+ </section>
+ <section name="vivado_usage" level="1" order="9" description="">
+  <section name="java_command_handlers" level="2" order="1" description="">
+   <keyValuePair key="runbitgen" value="1" description="" />
+   <keyValuePair key="runimplementation" value="1" description="" />
+   <keyValuePair key="runsynthesis" value="1" description="" />
+  </section>
+  <section name="other_data" level="2" order="2" description="">
+   <keyValuePair key="guimode" value="1" description="" />
+  </section>
+  <section name="project_data" level="2" order="3" description="">
+   <keyValuePair key="constraintsetcount" value="1" description="" />
+   <keyValuePair key="core_container" value="false" description="" />
+   <keyValuePair key="currentimplrun" value="impl_1" description="" />
+   <keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
+   <keyValuePair key="default_library" value="xil_defaultlib" description="" />
+   <keyValuePair key="designmode" value="RTL" description="" />
+   <keyValuePair key="export_simulation_activehdl" value="0" description="" />
+   <keyValuePair key="export_simulation_ies" value="0" description="" />
+   <keyValuePair key="export_simulation_modelsim" value="0" description="" />
+   <keyValuePair key="export_simulation_questa" value="0" description="" />
+   <keyValuePair key="export_simulation_riviera" value="0" description="" />
+   <keyValuePair key="export_simulation_vcs" value="0" description="" />
+   <keyValuePair key="export_simulation_xsim" value="0" description="" />
+   <keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
+   <keyValuePair key="launch_simulation_activehdl" value="0" description="" />
+   <keyValuePair key="launch_simulation_ies" value="0" description="" />
+   <keyValuePair key="launch_simulation_modelsim" value="0" description="" />
+   <keyValuePair key="launch_simulation_questa" value="0" description="" />
+   <keyValuePair key="launch_simulation_riviera" value="0" description="" />
+   <keyValuePair key="launch_simulation_vcs" value="0" description="" />
+   <keyValuePair key="launch_simulation_xsim" value="0" description="" />
+   <keyValuePair key="simulator_language" value="Mixed" description="" />
+   <keyValuePair key="srcsetcount" value="9" description="" />
+   <keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
+   <keyValuePair key="target_language" value="VHDL" description="" />
+   <keyValuePair key="target_simulator" value="XSim" description="" />
+   <keyValuePair key="totalimplruns" value="1" description="" />
+   <keyValuePair key="totalsynthesisruns" value="1" description="" />
+  </section>
+ </section>
+</section>
+</webTalkData>
diff --git a/proj/GPIO.runs/impl_1/vivado.jou b/proj/GPIO.runs/impl_1/vivado.jou
new file mode 100644
index 0000000..c112451
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Fri Apr 09 23:19:20 2021
+# Process ID: 1988
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
+# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
+#-----------------------------------------------------------
+source GPIO_demo.tcl -notrace
diff --git a/proj/GPIO.runs/impl_1/vivado.pb b/proj/GPIO.runs/impl_1/vivado.pb
new file mode 100644
index 0000000..ceb824c
Binary files /dev/null and b/proj/GPIO.runs/impl_1/vivado.pb differ
diff --git a/proj/GPIO.runs/impl_1/vivado_960.backup.jou b/proj/GPIO.runs/impl_1/vivado_960.backup.jou
new file mode 100644
index 0000000..81bbe49
--- /dev/null
+++ b/proj/GPIO.runs/impl_1/vivado_960.backup.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Fri Apr 09 23:15:32 2021
+# Process ID: 960
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
+# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
+#-----------------------------------------------------------
+source GPIO_demo.tcl -notrace
diff --git a/proj/GPIO.runs/impl_1/write_bitstream.pb b/proj/GPIO.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000..28bf6a6
Binary files /dev/null and b/proj/GPIO.runs/impl_1/write_bitstream.pb differ
diff --git a/proj/GPIO.runs/synth_1/.Vivado_Synthesis.queue.rst b/proj/GPIO.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/synth_1/.Xil/GPIO_demo_propImpl.xdc b/proj/GPIO.runs/synth_1/.Xil/GPIO_demo_propImpl.xdc
new file mode 100644
index 0000000..4357eb7
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/.Xil/GPIO_demo_propImpl.xdc
@@ -0,0 +1,135 @@
+set_property SRC_FILE_INFO {cfile:C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc rfile:../../../../src/constraints/Basys3_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W5 [get_ports CLK]
+set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
+set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
+set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
+set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
+set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
+set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
+set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
+set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V2 [get_ports {SW[8]}]
+set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T3 [get_ports {SW[9]}]
+set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T2 [get_ports {SW[10]}]
+set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R3 [get_ports {SW[11]}]
+set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W2 [get_ports {SW[12]}]
+set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U1 [get_ports {SW[13]}]
+set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T1 [get_ports {SW[14]}]
+set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R2 [get_ports {SW[15]}]
+set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
+set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
+set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
+set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
+set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
+set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
+set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
+set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
+set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V13 [get_ports {LED[8]}]
+set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V3 [get_ports {LED[9]}]
+set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W3 [get_ports {LED[10]}]
+set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U3 [get_ports {LED[11]}]
+set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P3 [get_ports {LED[12]}]
+set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N3 [get_ports {LED[13]}]
+set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P1 [get_ports {LED[14]}]
+set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L1 [get_ports {LED[15]}]
+set_property src_info {type:XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W7 [get_ports {SSEG_CA[0]}]
+set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W6 [get_ports {SSEG_CA[1]}]
+set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U8 [get_ports {SSEG_CA[2]}]
+set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V8 [get_ports {SSEG_CA[3]}]
+set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U5 [get_ports {SSEG_CA[4]}]
+set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V5 [get_ports {SSEG_CA[5]}]
+set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U7 [get_ports {SSEG_CA[6]}]
+set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V7 [get_ports {SSEG_CA[7]}]
+set_property src_info {type:XDC file:1 line:110 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U2 [get_ports {SSEG_AN[0]}]
+set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U4 [get_ports {SSEG_AN[1]}]
+set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V4 [get_ports {SSEG_AN[2]}]
+set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W4 [get_ports {SSEG_AN[3]}]
+set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U18 [get_ports {BTN[4]}]
+set_property src_info {type:XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T18 [get_ports {BTN[0]}]
+set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W19 [get_ports {BTN[1]}]
+set_property src_info {type:XDC file:1 line:134 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T17 [get_ports {BTN[2]}]
+set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U17 [get_ports {BTN[3]}]
+set_property src_info {type:XDC file:1 line:255 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN G19 [get_ports {VGA_RED[0]}]
+set_property src_info {type:XDC file:1 line:258 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN H19 [get_ports {VGA_RED[1]}]
+set_property src_info {type:XDC file:1 line:261 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN J19 [get_ports {VGA_RED[2]}]
+set_property src_info {type:XDC file:1 line:264 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N19 [get_ports {VGA_RED[3]}]
+set_property src_info {type:XDC file:1 line:267 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N18 [get_ports {VGA_BLUE[0]}]
+set_property src_info {type:XDC file:1 line:270 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L18 [get_ports {VGA_BLUE[1]}]
+set_property src_info {type:XDC file:1 line:273 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN K18 [get_ports {VGA_BLUE[2]}]
+set_property src_info {type:XDC file:1 line:276 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN J18 [get_ports {VGA_BLUE[3]}]
+set_property src_info {type:XDC file:1 line:279 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN J17 [get_ports {VGA_GREEN[0]}]
+set_property src_info {type:XDC file:1 line:282 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN H17 [get_ports {VGA_GREEN[1]}]
+set_property src_info {type:XDC file:1 line:285 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN G17 [get_ports {VGA_GREEN[2]}]
+set_property src_info {type:XDC file:1 line:288 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN D17 [get_ports {VGA_GREEN[3]}]
+set_property src_info {type:XDC file:1 line:291 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P19 [get_ports VGA_HS]
+set_property src_info {type:XDC file:1 line:294 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R19 [get_ports VGA_VS]
+set_property src_info {type:XDC file:1 line:303 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN A18 [get_ports UART_TXD]
+set_property src_info {type:XDC file:1 line:310 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN C17 [get_ports PS2_CLK]
+set_property src_info {type:XDC file:1 line:314 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN B17 [get_ports PS2_DATA]
diff --git a/proj/GPIO.runs/synth_1/.vivado.begin.rst b/proj/GPIO.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000..6ca6eef
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="7440">
+    </Process>
+</ProcessHandle>
diff --git a/proj/GPIO.runs/synth_1/.vivado.end.rst b/proj/GPIO.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/GPIO.runs/synth_1/GPIO_demo.dcp b/proj/GPIO.runs/synth_1/GPIO_demo.dcp
new file mode 100644
index 0000000..5a48d19
Binary files /dev/null and b/proj/GPIO.runs/synth_1/GPIO_demo.dcp differ
diff --git a/proj/GPIO.runs/synth_1/GPIO_demo.tcl b/proj/GPIO.runs/synth_1/GPIO_demo.tcl
new file mode 100644
index 0000000..ec58495
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/GPIO_demo.tcl
@@ -0,0 +1,43 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set_msg_config -id {HDL 9-1061} -limit 100000
+set_msg_config -id {HDL 9-1654} -limit 100000
+create_project -in_memory -part xc7a35tcpg236-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.cache/wt [current_project]
+set_property parent.project_path C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property board_part digilentinc.com:basys3:part0:1.1 [current_project]
+set_property ip_repo_paths c:/Users/Hp/Documents/Compteur8BitsBasys3/repo [current_project]
+set_property ip_output_repo c:/Users/Hp/Documents/Compteur8BitsBasys3/repo/cache [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_vhdl -library xil_defaultlib {
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd
+  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd
+}
+foreach dcp [get_files -quiet -all *.dcp] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc
+set_property used_in_implementation false [get_files C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+
+
+synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy none -directive RuntimeOptimized -fsm_extraction off
+
+
+write_checkpoint -force -noxdef GPIO_demo.dcp
+
+catch { report_utilization -file GPIO_demo_utilization_synth.rpt -pb GPIO_demo_utilization_synth.pb }
diff --git a/proj/GPIO.runs/synth_1/GPIO_demo.vds b/proj/GPIO.runs/synth_1/GPIO_demo.vds
new file mode 100644
index 0000000..78ad6d4
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/GPIO_demo.vds
@@ -0,0 +1,803 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Fri Apr 09 23:10:44 2021
+# Process ID: 9840
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1
+# Command line: vivado.exe -log GPIO_demo.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.vds
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source GPIO_demo.tcl -notrace
+Command: synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy none -directive RuntimeOptimized -fsm_extraction off
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 3172 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 350.121 ; gain = 140.289
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'GPIO_demo' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
+	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
+	Parameter PORT_WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-3491] module 'debouncer' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:42' bound to instance 'Inst_btn_debounce' of component 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:320]
+INFO: [Synth 8-638] synthesizing module 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
+	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
+	Parameter PORT_WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-256] done synthesizing module 'debouncer' (1#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
+INFO: [Synth 8-3491] module 'UART_TX_CTRL' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:42' bound to instance 'Inst_UART_TX_CTRL' of component 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:450]
+INFO: [Synth 8-638] synthesizing module 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'UART_TX_CTRL' (2#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
+INFO: [Synth 8-3491] module 'vga_ctrl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:38' bound to instance 'Inst_vga_ctrl' of component 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:465]
+INFO: [Synth 8-638] synthesizing module 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
+INFO: [Synth 8-3491] module 'clk_wiz_0' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:74' bound to instance 'clk_wiz_0_inst' of component 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:197]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
+INFO: [Synth 8-3491] module 'clk_wiz_0_clk_wiz' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:74' bound to instance 'U0' of component 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:98]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
+	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
+	Parameter CLKFBOUT_MULT_F bound to: 10.125000 - type: float 
+	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
+	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
+	Parameter CLKOUT0_DIVIDE_F bound to: 9.375000 - type: float 
+	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
+	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter COMPENSATION bound to: ZHOLD - type: string 
+	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
+	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
+	Parameter IS_PSEN_INVERTED bound to: 1'b0 
+	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
+	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
+	Parameter IS_RST_INVERTED bound to: 1'b0 
+	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
+	Parameter REF_JITTER2 bound to: 0.000000 - type: float 
+	Parameter SS_EN bound to: FALSE - type: string 
+	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
+	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
+	Parameter STARTUP_WAIT bound to: 0 - type: bool 
+INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:125]
+INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:187]
+INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:194]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (3#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (4#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
+	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
+	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
+	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
+INFO: [Synth 8-3491] module 'MouseCtl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:179' bound to instance 'Inst_MouseCtl' of component 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:207]
+INFO: [Synth 8-638] synthesizing module 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
+	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
+	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
+	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
+INFO: [Synth 8-3491] module 'Ps2Interface' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:152' bound to instance 'Inst_Ps2Interface' of component 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:370]
+INFO: [Synth 8-638] synthesizing module 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
+INFO: [Synth 8-256] done synthesizing module 'Ps2Interface' (5#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
+INFO: [Synth 8-256] done synthesizing module 'MouseCtl' (6#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
+INFO: [Synth 8-3491] module 'MouseDisplay' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:99' bound to instance 'Inst_MouseDisplay' of component 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:334]
+INFO: [Synth 8-638] synthesizing module 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
+WARNING: [Synth 8-614] signal 'ypos' is read in the process but is not in the sensitivity list [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:197]
+INFO: [Synth 8-256] done synthesizing module 'MouseDisplay' (7#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
+INFO: [Synth 8-256] done synthesizing module 'vga_ctrl' (8#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'GPIO_demo' (9#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 391.957 ; gain = 182.125
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 391.957 ; gain = 182.125
+---------------------------------------------------------------------------------
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/GPIO_demo_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/GPIO_demo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Completed Processing XDC Constraints
+
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 692.656 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a35tcpg236-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5544] ROM "READY" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
+INFO: [Synth 8-5545] ROM "txState" won't be mapped to RAM because address size (31) is larger than maximum supported(25)
+INFO: [Synth 8-5544] ROM "bitIndex" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
+INFO: [Synth 8-5546] ROM "busy" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "delay_100us_counter_enable" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "delay_20us_counter_enable" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "delay_63clk_counter_enable" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "reset_bit_count" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5545] ROM "periodic_check_tick" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
+INFO: [Synth 8-5546] ROM "timeout" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-4471] merging register 'green_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:238]
+INFO: [Synth 8-4471] merging register 'blue_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:239]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
+INFO: [Synth 8-4471] merging register 'sendStr_reg[15][7:0]' into 'sendStr_reg[3][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
+INFO: [Synth 8-4471] merging register 'sendStr_reg[25][7:0]' into 'sendStr_reg[24][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
+INFO: [Synth 8-5544] ROM "sendStr[0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[1]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[2]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[3]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[4]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[5]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[6]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[7]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[8]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[9]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[10]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[11]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[12]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[13]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[14]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[18]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[19]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[21]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[22]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[23]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[24]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "strEnd" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "strIndex" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     26 Bit       Adders := 1     
+	   2 Input     24 Bit       Adders := 1     
+	   3 Input     13 Bit       Adders := 2     
+	   2 Input     12 Bit       Adders := 7     
+	   2 Input     11 Bit       Adders := 1     
+	   2 Input      8 Bit       Adders := 1     
+	   4 Input      8 Bit       Adders := 1     
+	   3 Input      8 Bit       Adders := 2     
+	   2 Input      7 Bit       Adders := 1     
+	   2 Input      4 Bit       Adders := 4     
+	   3 Input      4 Bit       Adders := 2     
++---XORs : 
+	   2 Input      1 Bit         XORs := 5     
++---Registers : 
+	               31 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	               24 Bit    Registers := 1     
+	               12 Bit    Registers := 10    
+	               11 Bit    Registers := 2     
+	               10 Bit    Registers := 1     
+	                8 Bit    Registers := 30    
+	                7 Bit    Registers := 1     
+	                6 Bit    Registers := 1     
+	                5 Bit    Registers := 2     
+	                4 Bit    Registers := 16    
+	                3 Bit    Registers := 1     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 42    
++---Muxes : 
+	   3 Input     31 Bit        Muxes := 1     
+	   2 Input     26 Bit        Muxes := 1     
+	   2 Input     24 Bit        Muxes := 1     
+	   2 Input     16 Bit        Muxes := 1     
+	   2 Input     12 Bit        Muxes := 10    
+	   2 Input     11 Bit        Muxes := 1     
+	   2 Input      9 Bit        Muxes := 2     
+	  38 Input      8 Bit        Muxes := 1     
+	   3 Input      8 Bit        Muxes := 20    
+	   2 Input      7 Bit        Muxes := 10    
+	   3 Input      6 Bit        Muxes := 2     
+	   2 Input      6 Bit        Muxes := 13    
+	   4 Input      6 Bit        Muxes := 2     
+	   5 Input      6 Bit        Muxes := 1     
+	   3 Input      5 Bit        Muxes := 2     
+	   2 Input      5 Bit        Muxes := 4     
+	   4 Input      5 Bit        Muxes := 6     
+	   5 Input      5 Bit        Muxes := 1     
+	   2 Input      4 Bit        Muxes := 9     
+	   3 Input      4 Bit        Muxes := 3     
+	   4 Input      4 Bit        Muxes := 3     
+	   3 Input      3 Bit        Muxes := 3     
+	   4 Input      3 Bit        Muxes := 1     
+	   2 Input      3 Bit        Muxes := 1     
+	   9 Input      3 Bit        Muxes := 1     
+	   4 Input      2 Bit        Muxes := 1     
+	   2 Input      2 Bit        Muxes := 4     
+	  18 Input      2 Bit        Muxes := 1     
+	   3 Input      2 Bit        Muxes := 2     
+	  38 Input      2 Bit        Muxes := 6     
+	   2 Input      1 Bit        Muxes := 24    
+	   4 Input      1 Bit        Muxes := 2     
+	  18 Input      1 Bit        Muxes := 5     
+	  38 Input      1 Bit        Muxes := 5     
+	   3 Input      1 Bit        Muxes := 6     
+	   8 Input      1 Bit        Muxes := 1     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module GPIO_demo 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input      4 Bit       Adders := 1     
++---Registers : 
+	               31 Bit    Registers := 1     
+	                8 Bit    Registers := 26    
+	                4 Bit    Registers := 2     
+	                3 Bit    Registers := 1     
+	                1 Bit    Registers := 1     
++---Muxes : 
+	   3 Input     31 Bit        Muxes := 1     
+	   2 Input     16 Bit        Muxes := 1     
+	   3 Input      8 Bit        Muxes := 20    
+	   2 Input      7 Bit        Muxes := 10    
+	   2 Input      6 Bit        Muxes := 10    
+	   2 Input      4 Bit        Muxes := 1     
+	   9 Input      3 Bit        Muxes := 1     
+	   2 Input      2 Bit        Muxes := 1     
+	   2 Input      1 Bit        Muxes := 3     
+	   8 Input      1 Bit        Muxes := 1     
+Module debouncer 
+Detailed RTL Component Info : 
++---XORs : 
+	   2 Input      1 Bit         XORs := 5     
++---Registers : 
+	                5 Bit    Registers := 1     
++---Muxes : 
+	   2 Input      1 Bit        Muxes := 5     
+Module UART_TX_CTRL 
+Detailed RTL Component Info : 
++---Registers : 
+	               10 Bit    Registers := 1     
+	                2 Bit    Registers := 1     
+	                1 Bit    Registers := 1     
++---Muxes : 
+	   4 Input      2 Bit        Muxes := 1     
+	   2 Input      1 Bit        Muxes := 4     
+	   4 Input      1 Bit        Muxes := 1     
+Module Ps2Interface 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     11 Bit       Adders := 1     
+	   2 Input      7 Bit       Adders := 1     
+	   2 Input      4 Bit       Adders := 3     
++---Registers : 
+	               11 Bit    Registers := 2     
+	                8 Bit    Registers := 1     
+	                7 Bit    Registers := 1     
+	                5 Bit    Registers := 1     
+	                4 Bit    Registers := 3     
+	                1 Bit    Registers := 17    
++---Muxes : 
+	   2 Input     11 Bit        Muxes := 1     
+	   3 Input      5 Bit        Muxes := 1     
+	   2 Input      5 Bit        Muxes := 1     
+	   2 Input      4 Bit        Muxes := 4     
+	   3 Input      4 Bit        Muxes := 2     
+	   3 Input      3 Bit        Muxes := 2     
+	   2 Input      2 Bit        Muxes := 2     
+	  18 Input      2 Bit        Muxes := 1     
+	  18 Input      1 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 7     
+	   4 Input      1 Bit        Muxes := 1     
+Module MouseCtl 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     26 Bit       Adders := 1     
+	   2 Input     24 Bit       Adders := 1     
+	   2 Input     12 Bit       Adders := 4     
+	   2 Input      8 Bit       Adders := 1     
++---Registers : 
+	               26 Bit    Registers := 1     
+	               24 Bit    Registers := 1     
+	               12 Bit    Registers := 6     
+	                8 Bit    Registers := 3     
+	                6 Bit    Registers := 1     
+	                4 Bit    Registers := 1     
+	                1 Bit    Registers := 17    
++---Muxes : 
+	   2 Input     26 Bit        Muxes := 1     
+	   2 Input     24 Bit        Muxes := 1     
+	   2 Input     12 Bit        Muxes := 10    
+	   2 Input      9 Bit        Muxes := 2     
+	  38 Input      8 Bit        Muxes := 1     
+	   3 Input      6 Bit        Muxes := 2     
+	   2 Input      6 Bit        Muxes := 3     
+	   4 Input      6 Bit        Muxes := 2     
+	   5 Input      6 Bit        Muxes := 1     
+	   3 Input      5 Bit        Muxes := 1     
+	   4 Input      5 Bit        Muxes := 6     
+	   5 Input      5 Bit        Muxes := 1     
+	   2 Input      5 Bit        Muxes := 3     
+	   3 Input      4 Bit        Muxes := 1     
+	   4 Input      4 Bit        Muxes := 3     
+	   2 Input      4 Bit        Muxes := 1     
+	   3 Input      3 Bit        Muxes := 1     
+	   4 Input      3 Bit        Muxes := 1     
+	   2 Input      3 Bit        Muxes := 1     
+	   3 Input      2 Bit        Muxes := 2     
+	   2 Input      2 Bit        Muxes := 1     
+	  38 Input      2 Bit        Muxes := 6     
+	  38 Input      1 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+	   3 Input      1 Bit        Muxes := 6     
+Module MouseDisplay 
+Detailed RTL Component Info : 
++---Adders : 
+	   3 Input     13 Bit       Adders := 2     
+	   2 Input     12 Bit       Adders := 3     
+	   3 Input      4 Bit       Adders := 2     
++---Registers : 
+	                4 Bit    Registers := 1     
+	                2 Bit    Registers := 1     
+	                1 Bit    Registers := 1     
+Module vga_ctrl 
+Detailed RTL Component Info : 
++---Adders : 
+	   4 Input      8 Bit       Adders := 1     
+	   3 Input      8 Bit       Adders := 2     
++---Registers : 
+	               12 Bit    Registers := 4     
+	                4 Bit    Registers := 9     
+	                1 Bit    Registers := 5     
++---Muxes : 
+	   2 Input      4 Bit        Muxes := 3     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 90 (col length:60)
+BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[8]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[9]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[10]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[11]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[8]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[10]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_vga_ctrl/Inst_MouseCtl/\y_max_reg[11] )
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[0]' (FDSE) to 'strEnd_reg[1]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[2]' (FDRE) to 'strEnd_reg[5]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[3]' (FDSE) to 'strEnd_reg[4]'
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\strEnd_reg[4] )
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[5]' (FDRE) to 'strEnd_reg[6]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[6]' (FDRE) to 'strEnd_reg[7]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[7]' (FDRE) to 'strEnd_reg[8]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[8]' (FDRE) to 'strEnd_reg[9]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[9]' (FDRE) to 'strEnd_reg[10]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[10]' (FDRE) to 'strEnd_reg[11]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[11]' (FDRE) to 'strEnd_reg[12]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[12]' (FDRE) to 'strEnd_reg[13]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[13]' (FDRE) to 'strEnd_reg[14]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[14]' (FDRE) to 'strEnd_reg[15]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[15]' (FDRE) to 'strEnd_reg[16]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[16]' (FDRE) to 'strEnd_reg[17]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[17]' (FDRE) to 'strEnd_reg[18]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[18]' (FDRE) to 'strEnd_reg[19]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[19]' (FDRE) to 'strEnd_reg[20]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[20]' (FDRE) to 'strEnd_reg[21]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[21]' (FDRE) to 'strEnd_reg[22]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[22]' (FDRE) to 'strEnd_reg[23]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[23]' (FDRE) to 'strEnd_reg[24]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[24]' (FDRE) to 'strEnd_reg[25]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[25]' (FDRE) to 'strEnd_reg[26]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[26]' (FDRE) to 'strEnd_reg[27]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[27]' (FDRE) to 'strEnd_reg[28]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[28]' (FDRE) to 'strEnd_reg[29]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[29]' (FDRE) to 'strEnd_reg[30]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\strEnd_reg[30] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][7]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][7]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][7]' (FDRE) to 'sendStr_reg[23][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][7]' (FDRE) to 'sendStr_reg[22][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][7]' (FDRE) to 'sendStr_reg[21][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][7]' (FDRE) to 'sendStr_reg[19][7]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][7]' (FDRE) to 'sendStr_reg[19][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][7]' (FDRE) to 'sendStr_reg[18][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][7]' (FDRE) to 'sendStr_reg[5][7]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][7]' (FDRE) to 'sendStr_reg[5][7]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][7]' (FDRE) to 'sendStr_reg[14][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[13][7]' (FDRE) to 'sendStr_reg[13][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][7]' (FDRE) to 'sendStr_reg[12][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][7]' (FDRE) to 'sendStr_reg[11][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][7]' (FDRE) to 'sendStr_reg[10][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][7]' (FDRE) to 'sendStr_reg[9][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][7]' (FDRE) to 'sendStr_reg[8][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[7][7]' (FDRE) to 'sendStr_reg[7][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][7]' (FDRE) to 'sendStr_reg[6][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][7]' (FDRE) to 'sendStr_reg[17][3]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[4][7] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[3][7]' (FDRE) to 'sendStr_reg[3][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[2][7]' (FDRE) to 'sendStr_reg[2][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][7]' (FDRE) to 'sendStr_reg[1][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[0][7]' (FDRE) to 'sendStr_reg[0][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][6]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][6]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][6]' (FDRE) to 'sendStr_reg[23][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][6]' (FDSE) to 'sendStr_reg[22][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][6]' (FDSE) to 'sendStr_reg[21][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][6]' (FDSE) to 'sendStr_reg[19][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][6]' (FDSE) to 'sendStr_reg[19][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][6]' (FDRE) to 'sendStr_reg[18][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][6]' (FDSE) to 'sendStr_reg[5][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][6]' (FDSE) to 'sendStr_reg[5][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][6]' (FDSE) to 'sendStr_reg[14][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][6]' (FDSE) to 'sendStr_reg[12][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][6]' (FDSE) to 'sendStr_reg[11][0]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][6]' (FDSE) to 'sendStr_reg[10][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][6]' (FDSE) to 'sendStr_reg[9][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][6]' (FDRE) to 'sendStr_reg[8][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][6]' (FDSE) to 'sendStr_reg[6][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][6]' (FDSE) to 'sendStr_reg[5][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[4][6]' (FDSE) to 'sendStr_reg[4][1]'
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[3][6] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[2][6] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][6]' (FDRE) to 'sendStr_reg[1][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][5]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][5]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][5]' (FDRE) to 'sendStr_reg[22][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][5]' (FDRE) to 'sendStr_reg[19][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][5]' (FDRE) to 'sendStr_reg[19][0]'
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[18][5] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][5]' (FDRE) to 'sendStr_reg[5][5]'
+INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[8][5] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[22][4] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[13][4] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[12][4] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[10][4] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[7][4] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[16][3] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[9][3] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[5][3] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[19][2] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[13][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[11][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[10][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[7][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[6][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[23][1] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[22][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[21][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[19][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[14][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[3][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[1][1] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[0][1] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[26][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[24][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[23][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[21][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[18][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[14][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[11][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[9][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[8][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[4][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[2][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[1][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[0][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (Inst_UART_TX_CTRL/\txData_reg[9] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uartData_reg[7] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[8] )
+WARNING: [Synth 8-3332] Sequential element (txData_reg[9]) is unused and will be removed from module UART_TX_CTRL.
+WARNING: [Synth 8-3332] Sequential element (txData_reg[8]) is unused and will be removed from module UART_TX_CTRL.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[3]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[2]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[1]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[0]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (left_down_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (left_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (middle_down_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (middle_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (right_down_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (right_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (new_event_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (y_max_reg[11]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[9]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[8]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (strEnd_reg[30]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (strEnd_reg[4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][6]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][6]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][7]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[6][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][5]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][3]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[12][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][5]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (uartData_reg[7]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[5][3]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[26][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[16][3]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[24][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (y_max_reg[9]) is unused and will be removed from module MouseCtl.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+ROM:
++-------------+-------------+---------------+----------------+
+|Module Name  | RTL Object  | Depth x Width | Implemented As | 
++-------------+-------------+---------------+----------------+
+|MouseCtl     | write_data  | 64x1          | LUT            | 
+|MouseDisplay | mouserom[0] | 256x2         | LUT            | 
++-------------+-------------+---------------+----------------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5365] Flop ps2_data_h_reg is being inverted and renamed to ps2_data_h_reg_inv.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-----------+------+
+|      |Cell       |Count |
++------+-----------+------+
+|1     |BUFG       |     3|
+|2     |CARRY4     |   132|
+|3     |LUT1       |   368|
+|4     |LUT2       |   207|
+|5     |LUT3       |    91|
+|6     |LUT4       |   138|
+|7     |LUT5       |    73|
+|8     |LUT6       |   157|
+|9     |MMCME2_ADV |     1|
+|10    |MUXF7      |     3|
+|11    |FDRE       |   579|
+|12    |FDSE       |     2|
+|13    |IBUF       |    22|
+|14    |IOBUF      |     2|
+|15    |OBUF       |    43|
++------+-----------+------+
+
+Report Instance Areas: 
++------+------------------------+------------------+------+
+|      |Instance                |Module            |Cells |
++------+------------------------+------------------+------+
+|1     |top                     |                  |  1821|
+|2     |  Inst_btn_debounce     |debouncer         |   215|
+|3     |  Inst_UART_TX_CTRL     |UART_TX_CTRL      |   133|
+|4     |  Inst_vga_ctrl         |vga_ctrl          |  1100|
+|5     |    clk_wiz_0_inst      |clk_wiz_0         |     3|
+|6     |      U0                |clk_wiz_0_clk_wiz |     3|
+|7     |    Inst_MouseCtl       |MouseCtl          |   680|
+|8     |      Inst_Ps2Interface |Ps2Interface      |   211|
+|9     |    Inst_MouseDisplay   |MouseDisplay      |   124|
++------+------------------------+------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 76 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 692.656 ; gain = 116.863
+Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 692.656 ; gain = 482.824
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 157 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+245 Infos, 77 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 692.656 ; gain = 424.176
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.dcp' has been generated.
+report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 692.656 ; gain = 0.000
+INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:11:26 2021...
diff --git a/proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.pb b/proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.pb
new file mode 100644
index 0000000..dcc22bf
Binary files /dev/null and b/proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.pb differ
diff --git a/proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.rpt b/proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.rpt
new file mode 100644
index 0000000..7ef0f8e
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.rpt
@@ -0,0 +1,185 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
+| Date         : Fri Apr 09 23:11:26 2021
+| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
+| Command      : report_utilization -file GPIO_demo_utilization_synth.rpt -pb GPIO_demo_utilization_synth.pb
+| Design       : GPIO_demo
+| Device       : 7a35tcpg236-1
+| Design State : Synthesized
+-------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+-----------+-------+
+|        Site Type        | Used | Fixed | Available | Util% |
++-------------------------+------+-------+-----------+-------+
+| Slice LUTs*             |  903 |     0 |     20800 |  4.34 |
+|   LUT as Logic          |  903 |     0 |     20800 |  4.34 |
+|   LUT as Memory         |    0 |     0 |      9600 |  0.00 |
+| Slice Registers         |  581 |     0 |     41600 |  1.40 |
+|   Register as Flip Flop |  581 |     0 |     41600 |  1.40 |
+|   Register as Latch     |    0 |     0 |     41600 |  0.00 |
+| F7 Muxes                |    3 |     0 |     16300 |  0.02 |
+| F8 Muxes                |    0 |     0 |      8150 |  0.00 |
++-------------------------+------+-------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 2     |          Yes |         Set |            - |
+| 579   |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile |    0 |     0 |        50 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |        50 |  0.00 |
+|   RAMB18       |    0 |     0 |       100 |  0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs      |    0 |     0 |        90 |  0.00 |
++-----------+------+-------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+|          Site Type          | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB                  |   67 |     0 |       106 | 63.21 |
+| Bonded IPADs                |    0 |     0 |        10 |  0.00 |
+| Bonded OPADs                |    0 |     0 |         4 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |         5 |  0.00 |
+| PHASER_REF                  |    0 |     0 |         5 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |        20 |  0.00 |
+| IN_FIFO                     |    0 |     0 |        20 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |         5 |  0.00 |
+| IBUFDS                      |    0 |     0 |       104 |  0.00 |
+| GTPE2_CHANNEL               |    0 |     0 |         2 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        20 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        20 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       250 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |         2 |  0.00 |
+| ILOGIC                      |    0 |     0 |       106 |  0.00 |
+| OLOGIC                      |    0 |     0 |       106 |  0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL   |    3 |     0 |        32 |  9.38 |
+| BUFIO      |    0 |     0 |        20 |  0.00 |
+| MMCME2_ADV |    1 |     0 |         5 | 20.00 |
+| PLLE2_ADV  |    0 |     0 |         5 |  0.00 |
+| BUFMRCE    |    0 |     0 |        10 |  0.00 |
+| BUFHCE     |    0 |     0 |        72 |  0.00 |
+| BUFR       |    0 |     0 |        20 |  0.00 |
++------------+------+-------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |         1 |  0.00 |
+| XADC        |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++------------+------+---------------------+
+|  Ref Name  | Used | Functional Category |
++------------+------+---------------------+
+| FDRE       |  579 |        Flop & Latch |
+| LUT1       |  368 |                 LUT |
+| LUT2       |  207 |                 LUT |
+| LUT6       |  157 |                 LUT |
+| LUT4       |  138 |                 LUT |
+| CARRY4     |  132 |          CarryLogic |
+| LUT3       |   91 |                 LUT |
+| LUT5       |   73 |                 LUT |
+| OBUF       |   43 |                  IO |
+| IBUF       |   24 |                  IO |
+| MUXF7      |    3 |               MuxFx |
+| BUFG       |    3 |               Clock |
+| OBUFT      |    2 |                  IO |
+| FDSE       |    2 |        Flop & Latch |
+| MMCME2_ADV |    1 |               Clock |
++------------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/GPIO.runs/synth_1/ISEWrap.js b/proj/GPIO.runs/synth_1/ISEWrap.js
new file mode 100644
index 0000000..898ddd7
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/ISEWrap.js
@@ -0,0 +1,244 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/proj/GPIO.runs/synth_1/ISEWrap.sh b/proj/GPIO.runs/synth_1/ISEWrap.sh
new file mode 100644
index 0000000..e1a8f5d
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/GPIO.runs/synth_1/gen_run.xml b/proj/GPIO.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000..09360a3
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/gen_run.xml
@@ -0,0 +1,95 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1618002642">
+  <File Type="RDS-PROPCONSTRS" Name="GPIO_demo_drc_synth.rpt"/>
+  <File Type="PA-TCL" Name="GPIO_demo.tcl"/>
+  <File Type="RDS-RDS" Name="GPIO_demo.vds"/>
+  <File Type="RDS-UTIL" Name="GPIO_demo_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="GPIO_demo_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="GPIO_demo.dcp"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="GPIO_demo_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="GPIO_demo_timing_summary_synth.pb"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/debouncer.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="GPIO_demo"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015">
+      <Desc>Vivado Synthesis Defaults</Desc>
+    </StratHandle>
+    <Step Id="synth_design">
+      <Option Id="FlattenHierarchy">1</Option>
+      <Option Id="Directive">0</Option>
+      <Option Id="FsmExtraction">0</Option>
+    </Step>
+  </Strategy>
+</GenRun>
diff --git a/proj/GPIO.runs/synth_1/htr.txt b/proj/GPIO.runs/synth_1/htr.txt
new file mode 100644
index 0000000..0d258e1
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/htr.txt
@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
diff --git a/proj/GPIO.runs/synth_1/project.wdf b/proj/GPIO.runs/synth_1/project.wdf
new file mode 100644
index 0000000..68b2b16
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:39:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3031333866366637386234623465663361303338333762383461653364333333:506172656e742050412070726f6a656374204944:00
+eof:1785114370
diff --git a/proj/GPIO.runs/synth_1/rundef.js b/proj/GPIO.runs/synth_1/rundef.js
new file mode 100644
index 0000000..faeaa00
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/rundef.js
@@ -0,0 +1,36 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;";
+} else {
+  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/proj/GPIO.runs/synth_1/runme.bat b/proj/GPIO.runs/synth_1/runme.bat
new file mode 100644
index 0000000..660c945
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/GPIO.runs/synth_1/runme.log b/proj/GPIO.runs/synth_1/runme.log
new file mode 100644
index 0000000..f80a173
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/runme.log
@@ -0,0 +1,802 @@
+
+*** Running vivado
+    with args -log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
+
+
+****** Vivado v2016.4 (64-bit)
+  **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+
+source GPIO_demo.tcl -notrace
+Command: synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy none -directive RuntimeOptimized -fsm_extraction off
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 3172 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 350.121 ; gain = 140.289
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'GPIO_demo' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
+	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
+	Parameter PORT_WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-3491] module 'debouncer' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:42' bound to instance 'Inst_btn_debounce' of component 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:320]
+INFO: [Synth 8-638] synthesizing module 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
+	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
+	Parameter PORT_WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-256] done synthesizing module 'debouncer' (1#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
+INFO: [Synth 8-3491] module 'UART_TX_CTRL' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:42' bound to instance 'Inst_UART_TX_CTRL' of component 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:450]
+INFO: [Synth 8-638] synthesizing module 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'UART_TX_CTRL' (2#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
+INFO: [Synth 8-3491] module 'vga_ctrl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:38' bound to instance 'Inst_vga_ctrl' of component 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:465]
+INFO: [Synth 8-638] synthesizing module 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
+INFO: [Synth 8-3491] module 'clk_wiz_0' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:74' bound to instance 'clk_wiz_0_inst' of component 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:197]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
+INFO: [Synth 8-3491] module 'clk_wiz_0_clk_wiz' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:74' bound to instance 'U0' of component 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:98]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
+	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
+	Parameter CLKFBOUT_MULT_F bound to: 10.125000 - type: float 
+	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
+	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
+	Parameter CLKOUT0_DIVIDE_F bound to: 9.375000 - type: float 
+	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
+	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
+	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
+	Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 
+	Parameter COMPENSATION bound to: ZHOLD - type: string 
+	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
+	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
+	Parameter IS_PSEN_INVERTED bound to: 1'b0 
+	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
+	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
+	Parameter IS_RST_INVERTED bound to: 1'b0 
+	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
+	Parameter REF_JITTER2 bound to: 0.000000 - type: float 
+	Parameter SS_EN bound to: FALSE - type: string 
+	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
+	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
+	Parameter STARTUP_WAIT bound to: 0 - type: bool 
+INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:125]
+INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:187]
+INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:194]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (3#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (4#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
+	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
+	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
+	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
+INFO: [Synth 8-3491] module 'MouseCtl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:179' bound to instance 'Inst_MouseCtl' of component 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:207]
+INFO: [Synth 8-638] synthesizing module 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
+	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
+	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
+	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
+INFO: [Synth 8-3491] module 'Ps2Interface' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:152' bound to instance 'Inst_Ps2Interface' of component 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:370]
+INFO: [Synth 8-638] synthesizing module 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
+INFO: [Synth 8-256] done synthesizing module 'Ps2Interface' (5#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
+INFO: [Synth 8-256] done synthesizing module 'MouseCtl' (6#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
+INFO: [Synth 8-3491] module 'MouseDisplay' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:99' bound to instance 'Inst_MouseDisplay' of component 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:334]
+INFO: [Synth 8-638] synthesizing module 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
+WARNING: [Synth 8-614] signal 'ypos' is read in the process but is not in the sensitivity list [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:197]
+INFO: [Synth 8-256] done synthesizing module 'MouseDisplay' (7#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
+INFO: [Synth 8-256] done synthesizing module 'vga_ctrl' (8#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'GPIO_demo' (9#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 391.957 ; gain = 182.125
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 391.957 ; gain = 182.125
+---------------------------------------------------------------------------------
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/GPIO_demo_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/GPIO_demo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Completed Processing XDC Constraints
+
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 692.656 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a35tcpg236-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5544] ROM "READY" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
+INFO: [Synth 8-5545] ROM "txState" won't be mapped to RAM because address size (31) is larger than maximum supported(25)
+INFO: [Synth 8-5544] ROM "bitIndex" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
+INFO: [Synth 8-5546] ROM "busy" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "delay_100us_counter_enable" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "delay_20us_counter_enable" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "delay_63clk_counter_enable" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "reset_bit_count" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5545] ROM "periodic_check_tick" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
+INFO: [Synth 8-5546] ROM "timeout" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-4471] merging register 'green_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:238]
+INFO: [Synth 8-4471] merging register 'blue_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:239]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
+INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
+INFO: [Synth 8-4471] merging register 'sendStr_reg[15][7:0]' into 'sendStr_reg[3][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
+INFO: [Synth 8-4471] merging register 'sendStr_reg[25][7:0]' into 'sendStr_reg[24][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
+INFO: [Synth 8-5544] ROM "sendStr[0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[1]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[2]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[3]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[4]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[5]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[6]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[7]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[8]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[9]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[10]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[11]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[12]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[13]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[14]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[18]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[19]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[21]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[22]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[23]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "sendStr[24]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "strEnd" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+INFO: [Synth 8-5544] ROM "strIndex" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     26 Bit       Adders := 1     
+	   2 Input     24 Bit       Adders := 1     
+	   3 Input     13 Bit       Adders := 2     
+	   2 Input     12 Bit       Adders := 7     
+	   2 Input     11 Bit       Adders := 1     
+	   2 Input      8 Bit       Adders := 1     
+	   4 Input      8 Bit       Adders := 1     
+	   3 Input      8 Bit       Adders := 2     
+	   2 Input      7 Bit       Adders := 1     
+	   2 Input      4 Bit       Adders := 4     
+	   3 Input      4 Bit       Adders := 2     
++---XORs : 
+	   2 Input      1 Bit         XORs := 5     
++---Registers : 
+	               31 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	               24 Bit    Registers := 1     
+	               12 Bit    Registers := 10    
+	               11 Bit    Registers := 2     
+	               10 Bit    Registers := 1     
+	                8 Bit    Registers := 30    
+	                7 Bit    Registers := 1     
+	                6 Bit    Registers := 1     
+	                5 Bit    Registers := 2     
+	                4 Bit    Registers := 16    
+	                3 Bit    Registers := 1     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 42    
++---Muxes : 
+	   3 Input     31 Bit        Muxes := 1     
+	   2 Input     26 Bit        Muxes := 1     
+	   2 Input     24 Bit        Muxes := 1     
+	   2 Input     16 Bit        Muxes := 1     
+	   2 Input     12 Bit        Muxes := 10    
+	   2 Input     11 Bit        Muxes := 1     
+	   2 Input      9 Bit        Muxes := 2     
+	  38 Input      8 Bit        Muxes := 1     
+	   3 Input      8 Bit        Muxes := 20    
+	   2 Input      7 Bit        Muxes := 10    
+	   3 Input      6 Bit        Muxes := 2     
+	   2 Input      6 Bit        Muxes := 13    
+	   4 Input      6 Bit        Muxes := 2     
+	   5 Input      6 Bit        Muxes := 1     
+	   3 Input      5 Bit        Muxes := 2     
+	   2 Input      5 Bit        Muxes := 4     
+	   4 Input      5 Bit        Muxes := 6     
+	   5 Input      5 Bit        Muxes := 1     
+	   2 Input      4 Bit        Muxes := 9     
+	   3 Input      4 Bit        Muxes := 3     
+	   4 Input      4 Bit        Muxes := 3     
+	   3 Input      3 Bit        Muxes := 3     
+	   4 Input      3 Bit        Muxes := 1     
+	   2 Input      3 Bit        Muxes := 1     
+	   9 Input      3 Bit        Muxes := 1     
+	   4 Input      2 Bit        Muxes := 1     
+	   2 Input      2 Bit        Muxes := 4     
+	  18 Input      2 Bit        Muxes := 1     
+	   3 Input      2 Bit        Muxes := 2     
+	  38 Input      2 Bit        Muxes := 6     
+	   2 Input      1 Bit        Muxes := 24    
+	   4 Input      1 Bit        Muxes := 2     
+	  18 Input      1 Bit        Muxes := 5     
+	  38 Input      1 Bit        Muxes := 5     
+	   3 Input      1 Bit        Muxes := 6     
+	   8 Input      1 Bit        Muxes := 1     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module GPIO_demo 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input      4 Bit       Adders := 1     
++---Registers : 
+	               31 Bit    Registers := 1     
+	                8 Bit    Registers := 26    
+	                4 Bit    Registers := 2     
+	                3 Bit    Registers := 1     
+	                1 Bit    Registers := 1     
++---Muxes : 
+	   3 Input     31 Bit        Muxes := 1     
+	   2 Input     16 Bit        Muxes := 1     
+	   3 Input      8 Bit        Muxes := 20    
+	   2 Input      7 Bit        Muxes := 10    
+	   2 Input      6 Bit        Muxes := 10    
+	   2 Input      4 Bit        Muxes := 1     
+	   9 Input      3 Bit        Muxes := 1     
+	   2 Input      2 Bit        Muxes := 1     
+	   2 Input      1 Bit        Muxes := 3     
+	   8 Input      1 Bit        Muxes := 1     
+Module debouncer 
+Detailed RTL Component Info : 
++---XORs : 
+	   2 Input      1 Bit         XORs := 5     
++---Registers : 
+	                5 Bit    Registers := 1     
++---Muxes : 
+	   2 Input      1 Bit        Muxes := 5     
+Module UART_TX_CTRL 
+Detailed RTL Component Info : 
++---Registers : 
+	               10 Bit    Registers := 1     
+	                2 Bit    Registers := 1     
+	                1 Bit    Registers := 1     
++---Muxes : 
+	   4 Input      2 Bit        Muxes := 1     
+	   2 Input      1 Bit        Muxes := 4     
+	   4 Input      1 Bit        Muxes := 1     
+Module Ps2Interface 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     11 Bit       Adders := 1     
+	   2 Input      7 Bit       Adders := 1     
+	   2 Input      4 Bit       Adders := 3     
++---Registers : 
+	               11 Bit    Registers := 2     
+	                8 Bit    Registers := 1     
+	                7 Bit    Registers := 1     
+	                5 Bit    Registers := 1     
+	                4 Bit    Registers := 3     
+	                1 Bit    Registers := 17    
++---Muxes : 
+	   2 Input     11 Bit        Muxes := 1     
+	   3 Input      5 Bit        Muxes := 1     
+	   2 Input      5 Bit        Muxes := 1     
+	   2 Input      4 Bit        Muxes := 4     
+	   3 Input      4 Bit        Muxes := 2     
+	   3 Input      3 Bit        Muxes := 2     
+	   2 Input      2 Bit        Muxes := 2     
+	  18 Input      2 Bit        Muxes := 1     
+	  18 Input      1 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 7     
+	   4 Input      1 Bit        Muxes := 1     
+Module MouseCtl 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     26 Bit       Adders := 1     
+	   2 Input     24 Bit       Adders := 1     
+	   2 Input     12 Bit       Adders := 4     
+	   2 Input      8 Bit       Adders := 1     
++---Registers : 
+	               26 Bit    Registers := 1     
+	               24 Bit    Registers := 1     
+	               12 Bit    Registers := 6     
+	                8 Bit    Registers := 3     
+	                6 Bit    Registers := 1     
+	                4 Bit    Registers := 1     
+	                1 Bit    Registers := 17    
++---Muxes : 
+	   2 Input     26 Bit        Muxes := 1     
+	   2 Input     24 Bit        Muxes := 1     
+	   2 Input     12 Bit        Muxes := 10    
+	   2 Input      9 Bit        Muxes := 2     
+	  38 Input      8 Bit        Muxes := 1     
+	   3 Input      6 Bit        Muxes := 2     
+	   2 Input      6 Bit        Muxes := 3     
+	   4 Input      6 Bit        Muxes := 2     
+	   5 Input      6 Bit        Muxes := 1     
+	   3 Input      5 Bit        Muxes := 1     
+	   4 Input      5 Bit        Muxes := 6     
+	   5 Input      5 Bit        Muxes := 1     
+	   2 Input      5 Bit        Muxes := 3     
+	   3 Input      4 Bit        Muxes := 1     
+	   4 Input      4 Bit        Muxes := 3     
+	   2 Input      4 Bit        Muxes := 1     
+	   3 Input      3 Bit        Muxes := 1     
+	   4 Input      3 Bit        Muxes := 1     
+	   2 Input      3 Bit        Muxes := 1     
+	   3 Input      2 Bit        Muxes := 2     
+	   2 Input      2 Bit        Muxes := 1     
+	  38 Input      2 Bit        Muxes := 6     
+	  38 Input      1 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+	   3 Input      1 Bit        Muxes := 6     
+Module MouseDisplay 
+Detailed RTL Component Info : 
++---Adders : 
+	   3 Input     13 Bit       Adders := 2     
+	   2 Input     12 Bit       Adders := 3     
+	   3 Input      4 Bit       Adders := 2     
++---Registers : 
+	                4 Bit    Registers := 1     
+	                2 Bit    Registers := 1     
+	                1 Bit    Registers := 1     
+Module vga_ctrl 
+Detailed RTL Component Info : 
++---Adders : 
+	   4 Input      8 Bit       Adders := 1     
+	   3 Input      8 Bit       Adders := 2     
++---Registers : 
+	               12 Bit    Registers := 4     
+	                4 Bit    Registers := 9     
+	                1 Bit    Registers := 5     
++---Muxes : 
+	   2 Input      4 Bit        Muxes := 3     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 90 (col length:60)
+BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[8]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[9]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[10]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[11]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[8]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
+INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[10]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_vga_ctrl/Inst_MouseCtl/\y_max_reg[11] )
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[0]' (FDSE) to 'strEnd_reg[1]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[2]' (FDRE) to 'strEnd_reg[5]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[3]' (FDSE) to 'strEnd_reg[4]'
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\strEnd_reg[4] )
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[5]' (FDRE) to 'strEnd_reg[6]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[6]' (FDRE) to 'strEnd_reg[7]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[7]' (FDRE) to 'strEnd_reg[8]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[8]' (FDRE) to 'strEnd_reg[9]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[9]' (FDRE) to 'strEnd_reg[10]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[10]' (FDRE) to 'strEnd_reg[11]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[11]' (FDRE) to 'strEnd_reg[12]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[12]' (FDRE) to 'strEnd_reg[13]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[13]' (FDRE) to 'strEnd_reg[14]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[14]' (FDRE) to 'strEnd_reg[15]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[15]' (FDRE) to 'strEnd_reg[16]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[16]' (FDRE) to 'strEnd_reg[17]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[17]' (FDRE) to 'strEnd_reg[18]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[18]' (FDRE) to 'strEnd_reg[19]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[19]' (FDRE) to 'strEnd_reg[20]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[20]' (FDRE) to 'strEnd_reg[21]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[21]' (FDRE) to 'strEnd_reg[22]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[22]' (FDRE) to 'strEnd_reg[23]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[23]' (FDRE) to 'strEnd_reg[24]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[24]' (FDRE) to 'strEnd_reg[25]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[25]' (FDRE) to 'strEnd_reg[26]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[26]' (FDRE) to 'strEnd_reg[27]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[27]' (FDRE) to 'strEnd_reg[28]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[28]' (FDRE) to 'strEnd_reg[29]'
+INFO: [Synth 8-3886] merging instance 'strEnd_reg[29]' (FDRE) to 'strEnd_reg[30]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\strEnd_reg[30] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][7]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][7]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][7]' (FDRE) to 'sendStr_reg[23][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][7]' (FDRE) to 'sendStr_reg[22][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][7]' (FDRE) to 'sendStr_reg[21][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][7]' (FDRE) to 'sendStr_reg[19][7]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][7]' (FDRE) to 'sendStr_reg[19][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][7]' (FDRE) to 'sendStr_reg[18][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][7]' (FDRE) to 'sendStr_reg[5][7]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][7]' (FDRE) to 'sendStr_reg[5][7]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][7]' (FDRE) to 'sendStr_reg[14][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[13][7]' (FDRE) to 'sendStr_reg[13][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][7]' (FDRE) to 'sendStr_reg[12][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][7]' (FDRE) to 'sendStr_reg[11][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][7]' (FDRE) to 'sendStr_reg[10][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][7]' (FDRE) to 'sendStr_reg[9][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][7]' (FDRE) to 'sendStr_reg[8][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[7][7]' (FDRE) to 'sendStr_reg[7][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][7]' (FDRE) to 'sendStr_reg[6][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][7]' (FDRE) to 'sendStr_reg[17][3]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[4][7] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[3][7]' (FDRE) to 'sendStr_reg[3][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[2][7]' (FDRE) to 'sendStr_reg[2][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][7]' (FDRE) to 'sendStr_reg[1][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[0][7]' (FDRE) to 'sendStr_reg[0][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][6]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][6]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][6]' (FDRE) to 'sendStr_reg[23][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][6]' (FDSE) to 'sendStr_reg[22][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][6]' (FDSE) to 'sendStr_reg[21][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][6]' (FDSE) to 'sendStr_reg[19][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][6]' (FDSE) to 'sendStr_reg[19][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][6]' (FDRE) to 'sendStr_reg[18][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][6]' (FDSE) to 'sendStr_reg[5][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][6]' (FDSE) to 'sendStr_reg[5][6]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][6]' (FDSE) to 'sendStr_reg[14][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][6]' (FDSE) to 'sendStr_reg[12][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][6]' (FDSE) to 'sendStr_reg[11][0]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][6]' (FDSE) to 'sendStr_reg[10][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][6]' (FDSE) to 'sendStr_reg[9][2]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][6]' (FDRE) to 'sendStr_reg[8][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][6]' (FDSE) to 'sendStr_reg[6][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][6]' (FDSE) to 'sendStr_reg[5][3]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[4][6]' (FDSE) to 'sendStr_reg[4][1]'
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[3][6] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[2][6] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][6]' (FDRE) to 'sendStr_reg[1][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][5]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][5]' (FDRE) to 'sendStr_reg[26][1]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][5]' (FDRE) to 'sendStr_reg[22][4]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][5]' (FDRE) to 'sendStr_reg[19][5]'
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][5]' (FDRE) to 'sendStr_reg[19][0]'
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[18][5] )
+INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][5]' (FDRE) to 'sendStr_reg[5][5]'
+INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[8][5] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[22][4] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[13][4] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[12][4] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[10][4] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[7][4] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[16][3] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[9][3] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[5][3] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[19][2] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[13][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[11][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[10][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[7][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[6][2] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[23][1] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[22][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[21][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[19][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[14][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[3][1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[1][1] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[0][1] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[26][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[24][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[23][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[21][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[18][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[14][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[11][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[9][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[8][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[4][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[2][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[1][0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[0][0] )
+INFO: [Synth 8-3333] propagating constant 1 across sequential element (Inst_UART_TX_CTRL/\txData_reg[9] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[0] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uartData_reg[7] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[8] )
+WARNING: [Synth 8-3332] Sequential element (txData_reg[9]) is unused and will be removed from module UART_TX_CTRL.
+WARNING: [Synth 8-3332] Sequential element (txData_reg[8]) is unused and will be removed from module UART_TX_CTRL.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[3]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[2]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[1]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (zpos_reg[0]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (left_down_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (left_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (middle_down_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (middle_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (right_down_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (right_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (new_event_reg) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (y_max_reg[11]) is unused and will be removed from module MouseCtl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[9]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[8]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
+WARNING: [Synth 8-3332] Sequential element (strEnd_reg[30]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (strEnd_reg[4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][6]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][6]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][7]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[6][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][5]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][3]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[12][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][5]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][4]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (uartData_reg[7]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][2]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[5][3]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[26][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[16][3]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[24][0]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][1]) is unused and will be removed from module GPIO_demo.
+WARNING: [Synth 8-3332] Sequential element (y_max_reg[9]) is unused and will be removed from module MouseCtl.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+ROM:
++-------------+-------------+---------------+----------------+
+|Module Name  | RTL Object  | Depth x Width | Implemented As | 
++-------------+-------------+---------------+----------------+
+|MouseCtl     | write_data  | 64x1          | LUT            | 
+|MouseDisplay | mouserom[0] | 256x2         | LUT            | 
++-------------+-------------+---------------+----------------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5365] Flop ps2_data_h_reg is being inverted and renamed to ps2_data_h_reg_inv.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-----------+------+
+|      |Cell       |Count |
++------+-----------+------+
+|1     |BUFG       |     3|
+|2     |CARRY4     |   132|
+|3     |LUT1       |   368|
+|4     |LUT2       |   207|
+|5     |LUT3       |    91|
+|6     |LUT4       |   138|
+|7     |LUT5       |    73|
+|8     |LUT6       |   157|
+|9     |MMCME2_ADV |     1|
+|10    |MUXF7      |     3|
+|11    |FDRE       |   579|
+|12    |FDSE       |     2|
+|13    |IBUF       |    22|
+|14    |IOBUF      |     2|
+|15    |OBUF       |    43|
++------+-----------+------+
+
+Report Instance Areas: 
++------+------------------------+------------------+------+
+|      |Instance                |Module            |Cells |
++------+------------------------+------------------+------+
+|1     |top                     |                  |  1821|
+|2     |  Inst_btn_debounce     |debouncer         |   215|
+|3     |  Inst_UART_TX_CTRL     |UART_TX_CTRL      |   133|
+|4     |  Inst_vga_ctrl         |vga_ctrl          |  1100|
+|5     |    clk_wiz_0_inst      |clk_wiz_0         |     3|
+|6     |      U0                |clk_wiz_0_clk_wiz |     3|
+|7     |    Inst_MouseCtl       |MouseCtl          |   680|
+|8     |      Inst_Ps2Interface |Ps2Interface      |   211|
+|9     |    Inst_MouseDisplay   |MouseDisplay      |   124|
++------+------------------------+------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 76 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 692.656 ; gain = 116.863
+Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 692.656 ; gain = 482.824
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 157 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+245 Infos, 77 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 692.656 ; gain = 424.176
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.dcp' has been generated.
+report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 692.656 ; gain = 0.000
+INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:11:26 2021...
diff --git a/proj/GPIO.runs/synth_1/runme.sh b/proj/GPIO.runs/synth_1/runme.sh
new file mode 100644
index 0000000..9889f7b
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin
+else
+  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
diff --git a/proj/GPIO.runs/synth_1/vivado.jou b/proj/GPIO.runs/synth_1/vivado.jou
new file mode 100644
index 0000000..d6f7c6b
--- /dev/null
+++ b/proj/GPIO.runs/synth_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Fri Apr 09 23:10:44 2021
+# Process ID: 9840
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1
+# Command line: vivado.exe -log GPIO_demo.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.vds
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source GPIO_demo.tcl -notrace
diff --git a/proj/GPIO.runs/synth_1/vivado.pb b/proj/GPIO.runs/synth_1/vivado.pb
new file mode 100644
index 0000000..7758359
Binary files /dev/null and b/proj/GPIO.runs/synth_1/vivado.pb differ
diff --git a/proj/GPIO.xpr b/proj/GPIO.xpr
new file mode 100644
index 0000000..dc765c1
--- /dev/null
+++ b/proj/GPIO.xpr
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2016.4 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="0138f6f78b4b4ef3a03837b84ae3d333"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
+    <Option Name="IPOutputRepo" Val="$PPRDIR/../repo/cache"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PPRDIR/GPIO.ip_user_files"/>
+    <Option Name="IPStaticSourceDir" Val="$PPRDIR/GPIO.ip_user_files/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="DSANumComputeUnits" Val="16"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="64"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/debouncer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="GPIO_demo"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="GPIO_demo"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design">
+          <Option Id="Directive">0</Option>
+          <Option Id="FlattenHierarchy">1</Option>
+          <Option Id="FsmExtraction">0</Option>
+        </Step>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015">
+          <Desc>Vivado Implementation Defaults</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design">
+          <Option Id="Directive">4</Option>
+        </Step>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design">
+          <Option Id="Directive">14</Option>
+        </Step>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design">
+          <Option Id="Directive">5</Option>
+        </Step>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+</Project>
diff --git a/vivado.jou b/vivado.jou
new file mode 100644
index 0000000..b0b37f0
--- /dev/null
+++ b/vivado.jou
@@ -0,0 +1,74 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Wed Apr 14 08:09:08 2021
+# Process ID: 4032
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6828 C:\Users\Hp\Documents\Compteur8BitsBasys3\Compteur8BitsBasys3.xpr
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr
+launch_runs synth_1 -jobs 2
+wait_on_run synth_1
+launch_runs impl_1 -jobs 2
+wait_on_run impl_1
+remove_files  -fileset sim_1 C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
+file delete -force C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
+reset_run impl_1
+launch_runs impl_1 -jobs 2
+wait_on_run impl_1
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+wait_on_run impl_1
+open_hw
+connect_hw_server
+open_hw_target
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+wait_on_run synth_1
+launch_runs impl_1 -jobs 2
+wait_on_run impl_1
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+wait_on_run synth_1
+launch_runs impl_1 -jobs 2
+wait_on_run impl_1
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+wait_on_run synth_1
+launch_runs impl_1 -jobs 2
+wait_on_run impl_1
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+wait_on_run synth_1
+launch_runs impl_1 -jobs 2
+wait_on_run impl_1
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+wait_on_run impl_1
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+wait_on_run synth_1
+launch_runs impl_1 -jobs 2
+wait_on_run impl_1
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+wait_on_run impl_1
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
diff --git a/vivado.log b/vivado.log
new file mode 100644
index 0000000..b60aa7f
--- /dev/null
+++ b/vivado.log
@@ -0,0 +1,159 @@
+#-----------------------------------------------------------
+# Vivado v2016.4 (64-bit)
+# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+# Start of session at: Wed Apr 14 08:09:08 2021
+# Process ID: 4032
+# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6828 C:\Users\Hp\Documents\Compteur8BitsBasys3\Compteur8BitsBasys3.xpr
+# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
+# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr
+Scanning sources...
+Finished scanning sources
+WARNING: [Project 1-509] GeneratedRun file for 'synth_1' not found
+WARNING: [Project 1-509] GeneratedRun file for 'impl_1' not found
+WARNING: [filemgmt 56-3] IPUserFilesDir: Could not find the directory 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.ip_user_files'.
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
+open_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 794.082 ; gain = 131.480
+launch_runs synth_1 -jobs 2
+INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
+[Wed Apr 14 08:24:05 2021] Launched synth_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 2
+[Wed Apr 14 08:25:26 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+remove_files  -fileset sim_1 C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
+file delete -force C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
+reset_run impl_1
+launch_runs impl_1 -jobs 2
+[Wed Apr 14 08:27:27 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+[Wed Apr 14 08:29:13 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+open_hw
+connect_hw_server
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
+INFO: [Labtools 27-2222] Launching hw_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+****** Xilinx hw_server v2016.4
+  **** Build date : Jan 23 2017-19:37:29
+    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+
+
+connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 881.043 ; gain = 0.000
+open_hw_target
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
+Resolution: 
+1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
+2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
+Resolution: 
+1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
+2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd:1]
+[Wed Apr 14 08:32:22 2021] Launched synth_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
+[Wed Apr 14 08:33:40 2021] Launched synth_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 2
+[Wed Apr 14 08:34:54 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
+[Wed Apr 14 08:40:08 2021] Launched synth_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 2
+[Wed Apr 14 08:41:23 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
+[Wed Apr 14 08:45:24 2021] Launched synth_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 2
+[Wed Apr 14 08:46:41 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
+[Wed Apr 14 08:49:30 2021] Launched synth_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 2
+[Wed Apr 14 08:50:57 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+[Wed Apr 14 08:54:17 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
+Resolution: 
+1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
+2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+reset_run synth_1
+launch_runs synth_1 -jobs 2
+INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
+[Wed Apr 14 09:00:05 2021] Launched synth_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 2
+[Wed Apr 14 09:00:59 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+[Wed Apr 14 09:02:14 2021] Launched impl_1...
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
+Resolution: 
+1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
+2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
+ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA.
+Check cable connectivity and that the target board is powered up then
+use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
+ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
+exit
+INFO: [Common 17-206] Exiting Vivado at Wed Apr 14 18:31:17 2021...