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<!-- -->
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<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
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-<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr">
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+<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/TestGITProcesseur/FPGA_PIR/Processeur.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="DSANumComputeUnits" Val="16"/>
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- <Option Name="WTXSimLaunchSim" Val="230"/>
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+ <Option Name="WTXSimLaunchSim" Val="231"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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@@ -149,7 +149,7 @@
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
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<FileInfo>
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- <Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
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+ <Attr Name="ImportPath" Val="$PPRDIR/../../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
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<Attr Name="ImportTime" Val="1614979917"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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@@ -233,16 +233,6 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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- <File Path="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg">
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- <FileInfo>
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- <Attr Name="UsedIn" Val="simulation"/>
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- </FileInfo>
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- </File>
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- <File Path="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg">
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- <FileInfo>
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- <Attr Name="UsedIn" Val="simulation"/>
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- </FileInfo>
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- </File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="Test_Pipeline"/>
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@@ -275,15 +265,14 @@
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="10">
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- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
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+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
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<Step Id="synth_design"/>
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</Strategy>
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- <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
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+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
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<Step Id="init_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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- <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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</Runs>
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