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Nettoyage

Paul Faure 2 years ago
parent
commit
792c78c136
92 changed files with 1 additions and 10311 deletions
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-<!--The data in this file is primarily intended for consumption by Xilinx tools.
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-The structure and the elements are likely to change over the next few releases.
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-This means code written to parse this file will need to be revisited each subsequent release.-->
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-<section name="Project Information" visible="false">
8
-<property name="ProjectID" value="f5d1f37f0c514482aeb99b8a58e27639" type="ProjectID"/>
9
-<property name="ProjectIteration" value="3" type="ProjectIteration"/>
10
-</section>
11
-<section name="PlanAhead Usage" visible="true">
12
-<item name="Project Data">
13
-<property name="SrcSetCount" value="1" type="SrcSetCount"/>
14
-<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
15
-<property name="DesignMode" value="RTL" type="DesignMode"/>
16
-<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
17
-<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
18
-</item>
19
-<item name="Java Command Handlers">
20
-<property name="AutoConnectTarget" value="1" type="JavaHandler"/>
21
-<property name="LaunchProgramFpga" value="1" type="JavaHandler"/>
22
-<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
23
-<property name="RunBitgen" value="1" type="JavaHandler"/>
24
-<property name="RunImplementation" value="1" type="JavaHandler"/>
25
-<property name="RunSynthesis" value="1" type="JavaHandler"/>
26
-<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
27
-</item>
28
-<item name="Gui Resources Info">
29
-<property name="BaseDialog_OK" value="6" type="GuiResourceData"/>
30
-<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiResourceData"/>
31
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="13" type="GuiResourceData"/>
32
-<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="2" type="GuiResourceData"/>
33
-<property name="PACommandNames_AUTO_CONNECT_TARGET" value="1" type="GuiResourceData"/>
34
-<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="1" type="GuiResourceData"/>
35
-<property name="PACommandNames_RUN_BITGEN" value="1" type="GuiResourceData"/>
36
-<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiResourceData"/>
37
-<property name="ProgramDebugTab_PROGRAM_DEVICE" value="1" type="GuiResourceData"/>
38
-<property name="ProgramFpgaDialog_PROGRAM" value="1" type="GuiResourceData"/>
39
-<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiResourceData"/>
40
-</item>
41
-<item name="Other">
42
-<property name="GuiMode" value="4" type="GuiMode"/>
43
-<property name="BatchMode" value="0" type="BatchMode"/>
44
-<property name="TclMode" value="3" type="TclMode"/>
45
-</item>
46
-</section>
47
-</application>
48
-</document>

+ 0
- 8
proj/GPIO.hw/GPIO.lpr View File

1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
3
-<!--                                                              -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
5
-
6
-<labtools version="1" minor="0">
7
-  <HWSession Dir="hw_1" File="hw.xml"/>
8
-</labtools>

+ 0
- 15
proj/GPIO.hw/hw_1/hw.xml View File

1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
3
-<!--                                                              -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
5
-
6
-<hwsession version="1" minor="2">
7
-  <device name="xc7a35t_0" gui_info=""/>
8
-  <ObjectList object_type="hw_device" gui_info="">
9
-    <Object name="xc7a35t_0" gui_info="">
10
-      <Properties Property="PROBES.FILE" value=""/>
11
-      <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/$_project_name__demo.bit"/>
12
-    </Object>
13
-  </ObjectList>
14
-  <probeset name="hw project" active="false"/>
15
-</hwsession>

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_1.xml View File

1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="synth_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
4
-</Runs>
5
-

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_2.xml View File

1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
4
-</Runs>
5
-

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_3.xml View File

1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
4
-</Runs>
5
-

+ 0
- 0
proj/GPIO.runs/impl_1/.Vivado_Implementation.queue.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.init_design.begin.rst View File

1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.init_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.opt_design.begin.rst View File

1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.opt_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.place_design.begin.rst View File

1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.place_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.route_design.begin.rst View File

1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.route_design.end.rst View File


+ 0
- 10
proj/GPIO.runs/impl_1/.vivado.begin.rst View File

1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="2772">
4
-    </Process>
5
-</ProcessHandle>
6
-<?xml version="1.0"?>
7
-<ProcessHandle Version="1" Minor="0">
8
-    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="12740">
9
-    </Process>
10
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.vivado.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.write_bitstream.begin.rst View File

1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="1988">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.write_bitstream.end.rst View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo.bit View File


+ 0
- 67
proj/GPIO.runs/impl_1/GPIO_demo.tcl View File

1
-proc start_step { step } {
2
-  set stopFile ".stop.rst"
3
-  if {[file isfile .stop.rst]} {
4
-    puts ""
5
-    puts "*** Halting run - EA reset detected ***"
6
-    puts ""
7
-    puts ""
8
-    return -code error
9
-  }
10
-  set beginFile ".$step.begin.rst"
11
-  set platform "$::tcl_platform(platform)"
12
-  set user "$::tcl_platform(user)"
13
-  set pid [pid]
14
-  set host ""
15
-  if { [string equal $platform unix] } {
16
-    if { [info exist ::env(HOSTNAME)] } {
17
-      set host $::env(HOSTNAME)
18
-    }
19
-  } else {
20
-    if { [info exist ::env(COMPUTERNAME)] } {
21
-      set host $::env(COMPUTERNAME)
22
-    }
23
-  }
24
-  set ch [open $beginFile w]
25
-  puts $ch "<?xml version=\"1.0\"?>"
26
-  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
27
-  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
28
-  puts $ch "    </Process>"
29
-  puts $ch "</ProcessHandle>"
30
-  close $ch
31
-}
32
-
33
-proc end_step { step } {
34
-  set endFile ".$step.end.rst"
35
-  set ch [open $endFile w]
36
-  close $ch
37
-}
38
-
39
-proc step_failed { step } {
40
-  set endFile ".$step.error.rst"
41
-  set ch [open $endFile w]
42
-  close $ch
43
-}
44
-
45
-set_msg_config -id {HDL 9-1061} -limit 100000
46
-set_msg_config -id {HDL 9-1654} -limit 100000
47
-
48
-start_step write_bitstream
49
-set ACTIVE_STEP write_bitstream
50
-set rc [catch {
51
-  create_msg_db write_bitstream.pb
52
-  open_checkpoint GPIO_demo_routed.dcp
53
-  set_property webtalk.parent_dir C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.cache/wt [current_project]
54
-  catch { write_mem_info -force GPIO_demo.mmi }
55
-  write_bitstream -force -no_partial_bitfile GPIO_demo.bit 
56
-  catch { write_sysdef -hwdef GPIO_demo.hwdef -bitfile GPIO_demo.bit -meminfo GPIO_demo.mmi -file GPIO_demo.sysdef }
57
-  catch {write_debug_probes -quiet -force debug_nets}
58
-  close_msg_db -file write_bitstream.pb
59
-} RESULT]
60
-if {$rc} {
61
-  step_failed write_bitstream
62
-  return -code error $RESULT
63
-} else {
64
-  end_step write_bitstream
65
-  unset ACTIVE_STEP 
66
-}
67
-

+ 0
- 475
proj/GPIO.runs/impl_1/GPIO_demo.vdi View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:15:32 2021
6
-# Process ID: 960
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace
13
-Design is defaulting to srcset: sources_1
14
-Design is defaulting to constrset: constrs_1
15
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
16
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
17
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
18
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
19
-INFO: [Project 1-570] Preparing netlist for logic optimization
20
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
21
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
22
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
23
-INFO: [Project 1-111] Unisim Transformation Summary:
24
-  A total of 2 instances were transformed.
25
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
26
-
27
-link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
28
-INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
29
-Command: opt_design -directive RuntimeOptimized
30
-INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
31
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
32
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
33
-Running DRC as a precondition to command opt_design
34
-
35
-Starting DRC Task
36
-INFO: [DRC 23-27] Running DRC with 2 threads
37
-INFO: [Project 1-461] DRC finished with 0 Errors
38
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
39
-
40
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
41
-
42
-Starting Logic Optimization Task
43
-Implement Debug Cores | Checksum: 11fc7498c
44
-INFO: [Timing 38-35] Done setting XDC timing constraints.
45
-INFO: [Timing 38-2] Deriving generated clocks
46
-
47
-Phase 1 Retarget
48
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
49
-INFO: [Opt 31-49] Retargeted 0 cell(s).
50
-Phase 1 Retarget | Checksum: 16f269fca
51
-
52
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
53
-
54
-Phase 2 Constant propagation
55
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
56
-INFO: [Opt 31-10] Eliminated 6 cells.
57
-Phase 2 Constant propagation | Checksum: 233a26f9e
58
-
59
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
60
-
61
-Phase 3 Sweep
62
-INFO: [Opt 31-12] Eliminated 363 unconnected nets.
63
-INFO: [Opt 31-11] Eliminated 2 unconnected cells.
64
-Phase 3 Sweep | Checksum: 1bb596469
65
-
66
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
67
-
68
-Phase 4 BUFG optimization
69
-INFO: [Opt 31-12] Eliminated 0 unconnected nets.
70
-INFO: [Opt 31-11] Eliminated 0 unconnected cells.
71
-Phase 4 BUFG optimization | Checksum: 1bb596469
72
-
73
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
74
-
75
-Starting Connectivity Check Task
76
-
77
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
78
-Ending Logic Optimization Task | Checksum: 1bb596469
79
-
80
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
81
-INFO: [Common 17-83] Releasing license: Implementation
82
-24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
83
-opt_design completed successfully
84
-opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
85
-Writing placer database...
86
-Writing XDEF routing.
87
-Writing XDEF routing logical nets.
88
-Writing XDEF routing special nets.
89
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
90
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
91
-INFO: [DRC 23-27] Running DRC with 2 threads
92
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
93
-INFO: [Chipscope 16-241] No debug cores found in the current design.
94
-Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
95
-or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
96
-Command: place_design -directive RuntimeOptimized
97
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
98
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
99
-INFO: [DRC 23-27] Running DRC with 2 threads
100
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
101
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
102
-Running DRC as a precondition to command place_design
103
-INFO: [DRC 23-27] Running DRC with 2 threads
104
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
105
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
106
-
107
-Starting Placer Task
108
-INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
109
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
110
-
111
-Phase 1 Placer Initialization
112
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
113
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
114
-
115
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
116
-INFO: [Timing 38-35] Done setting XDC timing constraints.
117
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
118
-
119
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
120
-
121
-Phase 1.2 Build Placer Netlist Model
122
-Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
123
-
124
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
125
-
126
-Phase 1.3 Constrain Clocks/Macros
127
-Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
128
-
129
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
130
-Phase 1 Placer Initialization | Checksum: f331096b
131
-
132
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
133
-
134
-Phase 2 Global Placement
135
-Phase 2 Global Placement | Checksum: 7e244a0f
136
-
137
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
138
-
139
-Phase 3 Detail Placement
140
-
141
-Phase 3.1 Commit Multi Column Macros
142
-Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
143
-
144
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
145
-
146
-Phase 3.2 Commit Most Macros & LUTRAMs
147
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
148
-
149
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
150
-
151
-Phase 3.3 Area Swap Optimization
152
-Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
153
-
154
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
155
-
156
-Phase 3.4 Pipeline Register Optimization
157
-Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
158
-
159
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
160
-
161
-Phase 3.5 Timing Path Optimizer
162
-Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
163
-
164
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
165
-
166
-Phase 3.6 Small Shape Detail Placement
167
-Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
168
-
169
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
170
-
171
-Phase 3.7 Re-assign LUT pins
172
-Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
173
-
174
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
175
-
176
-Phase 3.8 Pipeline Register Optimization
177
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
178
-
179
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
180
-Phase 3 Detail Placement | Checksum: 1c30709cd
181
-
182
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
183
-
184
-Phase 4 Post Placement Optimization and Clean-Up
185
-
186
-Phase 4.1 Post Commit Optimization
187
-INFO: [Timing 38-35] Done setting XDC timing constraints.
188
-
189
-Phase 4.1.1 Post Placement Optimization
190
-INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
191
-Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
192
-
193
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
194
-Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
195
-
196
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
197
-
198
-Phase 4.2 Post Placement Cleanup
199
-Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
200
-
201
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
202
-
203
-Phase 4.3 Placer Reporting
204
-Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
205
-
206
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
207
-
208
-Phase 4.4 Final Placement Cleanup
209
-Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
210
-
211
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
212
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
213
-
214
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
215
-Ending Placer Task | Checksum: dd20239e
216
-
217
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
218
-INFO: [Common 17-83] Releasing license: Implementation
219
-41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
220
-place_design completed successfully
221
-place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
222
-Writing placer database...
223
-Writing XDEF routing.
224
-Writing XDEF routing logical nets.
225
-Writing XDEF routing special nets.
226
-Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
227
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
228
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
229
-report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
230
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
231
-Command: route_design -directive RuntimeOptimized
232
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
233
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
234
-Running DRC as a precondition to command route_design
235
-INFO: [DRC 23-27] Running DRC with 2 threads
236
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
237
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
238
-
239
-
240
-Starting Routing Task
241
-INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
242
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
243
-Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
244
-
245
-Phase 1 Build RT Design
246
-Phase 1 Build RT Design | Checksum: be9a9a9a
247
-
248
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
249
-
250
-Phase 2 Router Initialization
251
-
252
-Phase 2.1 Create Timer
253
-Phase 2.1 Create Timer | Checksum: be9a9a9a
254
-
255
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
256
-
257
-Phase 2.2 Fix Topology Constraints
258
-Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
259
-
260
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
261
-
262
-Phase 2.3 Pre Route Cleanup
263
-Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
264
-
265
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
266
- Number of Nodes with overlaps = 0
267
-
268
-Phase 2.4 Update Timing
269
-Phase 2.4 Update Timing | Checksum: 111c71c3e
270
-
271
-Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
272
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
273
-
274
-Phase 2 Router Initialization | Checksum: 1ee683561
275
-
276
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
277
-
278
-Phase 3 Initial Routing
279
-Phase 3 Initial Routing | Checksum: 10e02a291
280
-
281
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
282
-
283
-Phase 4 Rip-up And Reroute
284
-
285
-Phase 4.1 Global Iteration 0
286
- Number of Nodes with overlaps = 107
287
- Number of Nodes with overlaps = 0
288
-
289
-Phase 4.1.1 Update Timing
290
-Phase 4.1.1 Update Timing | Checksum: da308246
291
-
292
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
293
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
294
-
295
-Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
296
-
297
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
298
-
299
-Phase 4.2 Global Iteration 1
300
- Number of Nodes with overlaps = 1
301
- Number of Nodes with overlaps = 0
302
-
303
-Phase 4.2.1 Update Timing
304
-Phase 4.2.1 Update Timing | Checksum: 1185cfc05
305
-
306
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
307
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
308
-
309
-Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
310
-
311
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
312
-Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
313
-
314
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
315
-
316
-Phase 5 Delay and Skew Optimization
317
-
318
-Phase 5.1 Delay CleanUp
319
-Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
320
-
321
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
322
-
323
-Phase 5.2 Clock Skew Optimization
324
-Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
325
-
326
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
327
-Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
328
-
329
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
330
-
331
-Phase 6 Post Hold Fix
332
-
333
-Phase 6.1 Hold Fix Iter
334
-
335
-Phase 6.1.1 Update Timing
336
-Phase 6.1.1 Update Timing | Checksum: 16251cbd9
337
-
338
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
339
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
340
-
341
-Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
342
-
343
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
344
-Phase 6 Post Hold Fix | Checksum: 12245b0d3
345
-
346
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
347
-
348
-Phase 7 Route finalize
349
-
350
-Router Utilization Summary
351
-  Global Vertical Routing Utilization    = 0.234075 %
352
-  Global Horizontal Routing Utilization  = 0.228267 %
353
-  Routable Net Status*
354
-  *Does not include unroutable nets such as driverless and loadless.
355
-  Run report_route_status for detailed report.
356
-  Number of Failed Nets               = 0
357
-  Number of Unrouted Nets             = 0
358
-  Number of Partially Routed Nets     = 0
359
-  Number of Node Overlaps             = 0
360
-
361
-Phase 7 Route finalize | Checksum: 1af3f3601
362
-
363
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
364
-
365
-Phase 8 Verifying routed nets
366
-
367
- Verification completed successfully
368
-Phase 8 Verifying routed nets | Checksum: 1af3f3601
369
-
370
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
371
-
372
-Phase 9 Depositing Routes
373
-Phase 9 Depositing Routes | Checksum: 15d59118d
374
-
375
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
376
-
377
-Phase 10 Post Router Timing
378
-INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
379
-
380
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
381
-Phase 10 Post Router Timing | Checksum: 15d59118d
382
-
383
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
384
-INFO: [Route 35-16] Router Completed Successfully
385
-
386
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
387
-
388
-Routing Is Done.
389
-INFO: [Common 17-83] Releasing license: Implementation
390
-56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
391
-route_design completed successfully
392
-route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
393
-Writing placer database...
394
-Writing XDEF routing.
395
-Writing XDEF routing logical nets.
396
-Writing XDEF routing special nets.
397
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
398
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
399
-INFO: [DRC 23-27] Running DRC with 2 threads
400
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
401
-INFO: [Timing 38-35] Done setting XDC timing constraints.
402
-INFO: [DRC 23-133] Running Methodology with 2 threads
403
-INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
404
-INFO: [Timing 38-35] Done setting XDC timing constraints.
405
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
406
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
407
-INFO: [Timing 38-35] Done setting XDC timing constraints.
408
-Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
409
-Running Vector-less Activity Propagation...
410
-
411
-Finished Running Vector-less Activity Propagation
412
-66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
413
-report_power completed successfully
414
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
415
-#-----------------------------------------------------------
416
-# Vivado v2016.4 (64-bit)
417
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
418
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
419
-# Start of session at: Fri Apr 09 23:19:20 2021
420
-# Process ID: 1988
421
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
422
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
423
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
424
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
425
-#-----------------------------------------------------------
426
-source GPIO_demo.tcl -notrace
427
-Command: open_checkpoint GPIO_demo_routed.dcp
428
-
429
-Starting open_checkpoint Task
430
-
431
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
432
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
433
-INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
434
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
435
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
436
-INFO: [Project 1-570] Preparing netlist for logic optimization
437
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
438
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
439
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
440
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
441
-Reading XDEF placement.
442
-Reading placer database...
443
-Reading XDEF routing.
444
-Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
445
-Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
446
-Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
447
-INFO: [Project 1-111] Unisim Transformation Summary:
448
-  A total of 2 instances were transformed.
449
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
450
-
451
-INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
452
-open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
453
-Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
454
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
455
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
456
-Running DRC as a precondition to command write_bitstream
457
-INFO: [DRC 23-27] Running DRC with 2 threads
458
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
459
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
460
-Loading data files...
461
-Loading site data...
462
-Loading route data...
463
-Processing options...
464
-Creating bitmap...
465
-Creating bitstream...
466
-Bitstream compression saved 13383552 bits.
467
-Writing bitstream ./GPIO_demo.bit...
468
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
469
-INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
470
-INFO: [Common 17-83] Releasing license: Implementation
471
-14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
472
-write_bitstream completed successfully
473
-write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
474
-INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
475
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...

+ 0
- 414
proj/GPIO.runs/impl_1/GPIO_demo_960.backup.vdi View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:15:32 2021
6
-# Process ID: 960
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace
13
-Design is defaulting to srcset: sources_1
14
-Design is defaulting to constrset: constrs_1
15
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
16
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
17
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
18
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
19
-INFO: [Project 1-570] Preparing netlist for logic optimization
20
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
21
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
22
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
23
-INFO: [Project 1-111] Unisim Transformation Summary:
24
-  A total of 2 instances were transformed.
25
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
26
-
27
-link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
28
-INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
29
-Command: opt_design -directive RuntimeOptimized
30
-INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
31
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
32
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
33
-Running DRC as a precondition to command opt_design
34
-
35
-Starting DRC Task
36
-INFO: [DRC 23-27] Running DRC with 2 threads
37
-INFO: [Project 1-461] DRC finished with 0 Errors
38
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
39
-
40
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
41
-
42
-Starting Logic Optimization Task
43
-Implement Debug Cores | Checksum: 11fc7498c
44
-INFO: [Timing 38-35] Done setting XDC timing constraints.
45
-INFO: [Timing 38-2] Deriving generated clocks
46
-
47
-Phase 1 Retarget
48
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
49
-INFO: [Opt 31-49] Retargeted 0 cell(s).
50
-Phase 1 Retarget | Checksum: 16f269fca
51
-
52
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
53
-
54
-Phase 2 Constant propagation
55
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
56
-INFO: [Opt 31-10] Eliminated 6 cells.
57
-Phase 2 Constant propagation | Checksum: 233a26f9e
58
-
59
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
60
-
61
-Phase 3 Sweep
62
-INFO: [Opt 31-12] Eliminated 363 unconnected nets.
63
-INFO: [Opt 31-11] Eliminated 2 unconnected cells.
64
-Phase 3 Sweep | Checksum: 1bb596469
65
-
66
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
67
-
68
-Phase 4 BUFG optimization
69
-INFO: [Opt 31-12] Eliminated 0 unconnected nets.
70
-INFO: [Opt 31-11] Eliminated 0 unconnected cells.
71
-Phase 4 BUFG optimization | Checksum: 1bb596469
72
-
73
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
74
-
75
-Starting Connectivity Check Task
76
-
77
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
78
-Ending Logic Optimization Task | Checksum: 1bb596469
79
-
80
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
81
-INFO: [Common 17-83] Releasing license: Implementation
82
-24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
83
-opt_design completed successfully
84
-opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
85
-Writing placer database...
86
-Writing XDEF routing.
87
-Writing XDEF routing logical nets.
88
-Writing XDEF routing special nets.
89
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
90
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
91
-INFO: [DRC 23-27] Running DRC with 2 threads
92
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
93
-INFO: [Chipscope 16-241] No debug cores found in the current design.
94
-Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
95
-or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
96
-Command: place_design -directive RuntimeOptimized
97
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
98
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
99
-INFO: [DRC 23-27] Running DRC with 2 threads
100
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
101
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
102
-Running DRC as a precondition to command place_design
103
-INFO: [DRC 23-27] Running DRC with 2 threads
104
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
105
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
106
-
107
-Starting Placer Task
108
-INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
109
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
110
-
111
-Phase 1 Placer Initialization
112
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
113
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
114
-
115
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
116
-INFO: [Timing 38-35] Done setting XDC timing constraints.
117
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
118
-
119
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
120
-
121
-Phase 1.2 Build Placer Netlist Model
122
-Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
123
-
124
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
125
-
126
-Phase 1.3 Constrain Clocks/Macros
127
-Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
128
-
129
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
130
-Phase 1 Placer Initialization | Checksum: f331096b
131
-
132
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
133
-
134
-Phase 2 Global Placement
135
-Phase 2 Global Placement | Checksum: 7e244a0f
136
-
137
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
138
-
139
-Phase 3 Detail Placement
140
-
141
-Phase 3.1 Commit Multi Column Macros
142
-Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
143
-
144
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
145
-
146
-Phase 3.2 Commit Most Macros & LUTRAMs
147
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
148
-
149
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
150
-
151
-Phase 3.3 Area Swap Optimization
152
-Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
153
-
154
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
155
-
156
-Phase 3.4 Pipeline Register Optimization
157
-Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
158
-
159
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
160
-
161
-Phase 3.5 Timing Path Optimizer
162
-Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
163
-
164
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
165
-
166
-Phase 3.6 Small Shape Detail Placement
167
-Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
168
-
169
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
170
-
171
-Phase 3.7 Re-assign LUT pins
172
-Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
173
-
174
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
175
-
176
-Phase 3.8 Pipeline Register Optimization
177
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
178
-
179
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
180
-Phase 3 Detail Placement | Checksum: 1c30709cd
181
-
182
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
183
-
184
-Phase 4 Post Placement Optimization and Clean-Up
185
-
186
-Phase 4.1 Post Commit Optimization
187
-INFO: [Timing 38-35] Done setting XDC timing constraints.
188
-
189
-Phase 4.1.1 Post Placement Optimization
190
-INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
191
-Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
192
-
193
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
194
-Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
195
-
196
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
197
-
198
-Phase 4.2 Post Placement Cleanup
199
-Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
200
-
201
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
202
-
203
-Phase 4.3 Placer Reporting
204
-Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
205
-
206
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
207
-
208
-Phase 4.4 Final Placement Cleanup
209
-Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
210
-
211
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
212
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
213
-
214
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
215
-Ending Placer Task | Checksum: dd20239e
216
-
217
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
218
-INFO: [Common 17-83] Releasing license: Implementation
219
-41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
220
-place_design completed successfully
221
-place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
222
-Writing placer database...
223
-Writing XDEF routing.
224
-Writing XDEF routing logical nets.
225
-Writing XDEF routing special nets.
226
-Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
227
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
228
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
229
-report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
230
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
231
-Command: route_design -directive RuntimeOptimized
232
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
233
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
234
-Running DRC as a precondition to command route_design
235
-INFO: [DRC 23-27] Running DRC with 2 threads
236
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
237
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
238
-
239
-
240
-Starting Routing Task
241
-INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
242
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
243
-Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
244
-
245
-Phase 1 Build RT Design
246
-Phase 1 Build RT Design | Checksum: be9a9a9a
247
-
248
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
249
-
250
-Phase 2 Router Initialization
251
-
252
-Phase 2.1 Create Timer
253
-Phase 2.1 Create Timer | Checksum: be9a9a9a
254
-
255
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
256
-
257
-Phase 2.2 Fix Topology Constraints
258
-Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
259
-
260
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
261
-
262
-Phase 2.3 Pre Route Cleanup
263
-Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
264
-
265
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
266
- Number of Nodes with overlaps = 0
267
-
268
-Phase 2.4 Update Timing
269
-Phase 2.4 Update Timing | Checksum: 111c71c3e
270
-
271
-Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
272
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
273
-
274
-Phase 2 Router Initialization | Checksum: 1ee683561
275
-
276
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
277
-
278
-Phase 3 Initial Routing
279
-Phase 3 Initial Routing | Checksum: 10e02a291
280
-
281
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
282
-
283
-Phase 4 Rip-up And Reroute
284
-
285
-Phase 4.1 Global Iteration 0
286
- Number of Nodes with overlaps = 107
287
- Number of Nodes with overlaps = 0
288
-
289
-Phase 4.1.1 Update Timing
290
-Phase 4.1.1 Update Timing | Checksum: da308246
291
-
292
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
293
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
294
-
295
-Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
296
-
297
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
298
-
299
-Phase 4.2 Global Iteration 1
300
- Number of Nodes with overlaps = 1
301
- Number of Nodes with overlaps = 0
302
-
303
-Phase 4.2.1 Update Timing
304
-Phase 4.2.1 Update Timing | Checksum: 1185cfc05
305
-
306
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
307
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
308
-
309
-Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
310
-
311
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
312
-Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
313
-
314
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
315
-
316
-Phase 5 Delay and Skew Optimization
317
-
318
-Phase 5.1 Delay CleanUp
319
-Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
320
-
321
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
322
-
323
-Phase 5.2 Clock Skew Optimization
324
-Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
325
-
326
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
327
-Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
328
-
329
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
330
-
331
-Phase 6 Post Hold Fix
332
-
333
-Phase 6.1 Hold Fix Iter
334
-
335
-Phase 6.1.1 Update Timing
336
-Phase 6.1.1 Update Timing | Checksum: 16251cbd9
337
-
338
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
339
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
340
-
341
-Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
342
-
343
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
344
-Phase 6 Post Hold Fix | Checksum: 12245b0d3
345
-
346
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
347
-
348
-Phase 7 Route finalize
349
-
350
-Router Utilization Summary
351
-  Global Vertical Routing Utilization    = 0.234075 %
352
-  Global Horizontal Routing Utilization  = 0.228267 %
353
-  Routable Net Status*
354
-  *Does not include unroutable nets such as driverless and loadless.
355
-  Run report_route_status for detailed report.
356
-  Number of Failed Nets               = 0
357
-  Number of Unrouted Nets             = 0
358
-  Number of Partially Routed Nets     = 0
359
-  Number of Node Overlaps             = 0
360
-
361
-Phase 7 Route finalize | Checksum: 1af3f3601
362
-
363
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
364
-
365
-Phase 8 Verifying routed nets
366
-
367
- Verification completed successfully
368
-Phase 8 Verifying routed nets | Checksum: 1af3f3601
369
-
370
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
371
-
372
-Phase 9 Depositing Routes
373
-Phase 9 Depositing Routes | Checksum: 15d59118d
374
-
375
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
376
-
377
-Phase 10 Post Router Timing
378
-INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
379
-
380
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
381
-Phase 10 Post Router Timing | Checksum: 15d59118d
382
-
383
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
384
-INFO: [Route 35-16] Router Completed Successfully
385
-
386
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
387
-
388
-Routing Is Done.
389
-INFO: [Common 17-83] Releasing license: Implementation
390
-56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
391
-route_design completed successfully
392
-route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
393
-Writing placer database...
394
-Writing XDEF routing.
395
-Writing XDEF routing logical nets.
396
-Writing XDEF routing special nets.
397
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
398
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
399
-INFO: [DRC 23-27] Running DRC with 2 threads
400
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
401
-INFO: [Timing 38-35] Done setting XDC timing constraints.
402
-INFO: [DRC 23-133] Running Methodology with 2 threads
403
-INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
404
-INFO: [Timing 38-35] Done setting XDC timing constraints.
405
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
406
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
407
-INFO: [Timing 38-35] Done setting XDC timing constraints.
408
-Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
409
-Running Vector-less Activity Propagation...
410
-
411
-Finished Running Vector-less Activity Propagation
412
-66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
413
-report_power completed successfully
414
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...

+ 0
- 235
proj/GPIO.runs/impl_1/GPIO_demo_clock_utilization_routed.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
----------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:39 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_clock_utilization -file GPIO_demo_clock_utilization_routed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : 7a35t-cpg236
9
-| Speed File   : -1  PRODUCTION 1.16 2016-11-09
10
----------------------------------------------------------------------------------------
11
-
12
-Clock Utilization Report
13
-
14
-Table of Contents
15
------------------
16
-1. Clock Primitive Utilization
17
-2. Global Clock Resources
18
-3. Global Clock Source Details
19
-4. Clock Regions: Key Resource Utilization
20
-5. Clock Regions : Global Clock Summary
21
-6. Cell Type Counts per Global Clock: Region X0Y0
22
-7. Cell Type Counts per Global Clock: Region X1Y0
23
-8. Cell Type Counts per Global Clock: Region X0Y1
24
-9. Load Cell Placement Summary for Global Clock g0
25
-10. Load Cell Placement Summary for Global Clock g1
26
-11. Load Cell Placement Summary for Global Clock g2
27
-
28
-1. Clock Primitive Utilization
29
-------------------------------
30
-
31
-+----------+------+-----------+-----+--------------+--------+
32
-| Type     | Used | Available | LOC | Clock Region | Pblock |
33
-+----------+------+-----------+-----+--------------+--------+
34
-| BUFGCTRL |    3 |        32 |   0 |            0 |      0 |
35
-| BUFH     |    0 |        72 |   0 |            0 |      0 |
36
-| BUFIO    |    0 |        20 |   0 |            0 |      0 |
37
-| BUFMR    |    0 |        10 |   0 |            0 |      0 |
38
-| BUFR     |    0 |        20 |   0 |            0 |      0 |
39
-| MMCM     |    1 |         5 |   0 |            0 |      0 |
40
-| PLL      |    0 |         5 |   0 |            0 |      0 |
41
-+----------+------+-----------+-----+--------------+--------+
42
-
43
-
44
-2. Global Clock Resources
45
--------------------------
46
-
47
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
48
-| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock              | Driver Pin                                    | Net                                                    |
49
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
50
-| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |      |                   |                 2 |         336 |               0 |        9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1               |
51
-| g1        | src1      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |      |                   |                 2 |         243 |               0 |       10.000 | sys_clk_pin        | CLK_IBUF_BUFG_inst/O                          | CLK_IBUF_BUFG                                          |
52
-| g2        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y2 | n/a          |      |                   |                 1 |           1 |               0 |       10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/O    | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
53
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
54
-* Clock Loads column represents the clock pin loads (pin count)
55
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
56
-
57
-
58
-3. Global Clock Source Details
59
-------------------------------
60
-
61
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
62
-| Source Id | Global Id | Driver Type/Pin     | Constraint | Site            | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock       | Driver Pin                                             | Net                                                |
63
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
64
-| src0      | g0        | MMCME2_ADV/CLKOUT0  | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |               9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0  | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |
65
-| src0      | g2        | MMCME2_ADV/CLKFBOUT | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |              10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |
66
-| src1      | g1        | IBUF/O              | IOB_X1Y26  | IOB_X1Y26       | X1Y0         |           1 |               0 |              10.000 | sys_clk_pin        | CLK_IBUF_inst/O                                        | CLK_IBUF                                           |
67
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
68
-* Clock Loads column represents the clock pin loads (pin count)
69
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
70
-
71
-
72
-4. Clock Regions: Key Resource Utilization
73
-------------------------------------------
74
-
75
-+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
76
-|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
77
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
78
-| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
79
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
80
-| X0Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  484 |  1200 |  206 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
81
-| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   31 |  1500 |    2 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
82
-| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   63 |  1200 |   21 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
83
-| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
84
-| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1800 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
85
-| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |   950 |    0 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
86
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
87
-* Global Clock column represents track count; while other columns represents cell counts
88
-
89
-
90
-5. Clock Regions : Global Clock Summary
91
----------------------------------------
92
-
93
-+----+----+----+
94
-|    | X0 | X1 |
95
-+----+----+----+
96
-| Y2 |  0 |  0 |
97
-| Y1 |  1 |  0 |
98
-| Y0 |  2 |  2 |
99
-+----+----+----+
100
-
101
-
102
-6. Cell Type Counts per Global Clock: Region X0Y0
103
--------------------------------------------------
104
-
105
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
106
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
107
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
108
-| g0        | n/a   | BUFG/O          | None       |         273 |               0 | 273 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
109
-| g1        | n/a   | BUFG/O          | None       |         211 |               0 | 211 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | CLK_IBUF_BUFG                            |
110
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
111
-* Clock Loads column represents the clock pin loads (pin count)
112
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
113
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
114
-
115
-
116
-7. Cell Type Counts per Global Clock: Region X1Y0
117
--------------------------------------------------
118
-
119
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
120
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                                    |
121
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
122
-| g1        | n/a   | BUFG/O          | None       |          32 |               0 | 31 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | CLK_IBUF_BUFG                                          |
123
-| g2        | n/a   | BUFG/O          | None       |           1 |               0 |  0 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
124
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
125
-* Clock Loads column represents the clock pin loads (pin count)
126
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
127
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
128
-
129
-
130
-8. Cell Type Counts per Global Clock: Region X0Y1
131
--------------------------------------------------
132
-
133
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
134
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
135
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
136
-| g0        | n/a   | BUFG/O          | None       |          63 |               0 | 63 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
137
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
138
-* Clock Loads column represents the clock pin loads (pin count)
139
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
140
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
141
-
142
-
143
-9. Load Cell Placement Summary for Global Clock g0
144
---------------------------------------------------
145
-
146
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
147
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                      |
148
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
149
-| g0        | BUFG/O          | n/a               | clk_out1_clk_wiz_0 |       9.259 | {0.000 4.630} |          |         336 |        0 |              0 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
150
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
151
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
152
-** IO Loads column represents load cell count of IO types
153
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
154
-**** GT Loads column represents load cell count of GT types
155
-
156
-
157
-+----+------+----+
158
-|    | X0   | X1 |
159
-+----+------+----+
160
-| Y2 |    0 |  0 |
161
-| Y1 |   63 |  0 |
162
-| Y0 |  273 |  0 |
163
-+----+------+----+
164
-
165
-
166
-10. Load Cell Placement Summary for Global Clock g1
167
----------------------------------------------------
168
-
169
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
170
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net           |
171
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
172
-| g1        | BUFG/O          | n/a               | sys_clk_pin |      10.000 | {0.000 5.000} |          |         242 |        0 |              1 |        0 | CLK_IBUF_BUFG |
173
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
174
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
175
-** IO Loads column represents load cell count of IO types
176
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
177
-**** GT Loads column represents load cell count of GT types
178
-
179
-
180
-+----+------+-----+
181
-|    | X0   | X1  |
182
-+----+------+-----+
183
-| Y2 |    0 |   0 |
184
-| Y1 |    0 |   0 |
185
-| Y0 |  211 |  32 |
186
-+----+------+-----+
187
-
188
-
189
-11. Load Cell Placement Summary for Global Clock g2
190
----------------------------------------------------
191
-
192
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
193
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                                    |
194
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
195
-| g2        | BUFG/O          | n/a               | clkfbout_clk_wiz_0 |      10.000 | {0.000 5.000} |          |           0 |        0 |              1 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
196
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
197
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
198
-** IO Loads column represents load cell count of IO types
199
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
200
-**** GT Loads column represents load cell count of GT types
201
-
202
-
203
-+----+----+----+
204
-|    | X0 | X1 |
205
-+----+----+----+
206
-| Y2 |  0 |  0 |
207
-| Y1 |  0 |  0 |
208
-| Y0 |  0 |  1 |
209
-+----+----+----+
210
-
211
-
212
-
213
-# Location of BUFG Primitives 
214
-set_property LOC BUFGCTRL_X0Y2 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf]
215
-set_property LOC BUFGCTRL_X0Y0 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf]
216
-set_property LOC BUFGCTRL_X0Y1 [get_cells CLK_IBUF_BUFG_inst]
217
-
218
-# Location of IO Primitives which is load of clock spine
219
-
220
-# Location of clock ports
221
-set_property LOC IOB_X1Y26 [get_ports CLK]
222
-
223
-# Clock net "Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1" driven by instance "Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf" located at site "BUFGCTRL_X0Y0"
224
-#startgroup
225
-create_pblock {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}
226
-add_cells_to_pblock [get_pblocks  {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1"}]]]
227
-resize_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
228
-#endgroup
229
-
230
-# Clock net "CLK_IBUF_BUFG" driven by instance "CLK_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1"
231
-#startgroup
232
-create_pblock {CLKAG_CLK_IBUF_BUFG}
233
-add_cells_to_pblock [get_pblocks  {CLKAG_CLK_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLK_IBUF_BUFG"}]]]
234
-resize_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
235
-#endgroup

+ 0
- 104
proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
---------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:08 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_control_sets -verbose -file GPIO_demo_control_sets_placed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35t
9
---------------------------------------------------------------------------------------
10
-
11
-Control Set Information
12
-
13
-Table of Contents
14
------------------
15
-1. Summary
16
-2. Flip-Flop Distribution
17
-3. Detailed Control Set Information
18
-
19
-1. Summary
20
-----------
21
-
22
-+----------------------------------------------------------+-------+
23
-|                          Status                          | Count |
24
-+----------------------------------------------------------+-------+
25
-| Number of unique control sets                            |    36 |
26
-| Unused register locations in slices containing registers |    94 |
27
-+----------------------------------------------------------+-------+
28
-
29
-
30
-2. Flip-Flop Distribution
31
--------------------------
32
-
33
-+--------------+-----------------------+------------------------+-----------------+--------------+
34
-| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
35
-+--------------+-----------------------+------------------------+-----------------+--------------+
36
-| No           | No                    | No                     |             132 |           57 |
37
-| No           | No                    | Yes                    |               0 |            0 |
38
-| No           | Yes                   | No                     |             226 |           57 |
39
-| Yes          | No                    | No                     |             105 |           40 |
40
-| Yes          | No                    | Yes                    |               0 |            0 |
41
-| Yes          | Yes                   | No                     |             115 |           32 |
42
-+--------------+-----------------------+------------------------+-----------------+--------------+
43
-
44
-
45
-3. Detailed Control Set Information
46
------------------------------------
47
-
48
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
49
-|                Clock Signal               |                                Enable Signal                               |                              Set/Reset Signal                              | Slice Load Count | Bel Load Count |
50
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
51
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk_inter0                   |                1 |              4 |
52
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/data_inter0                  |                1 |              4 |
53
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_overflow_i_1_n_0                             |                                                                            |                2 |              4 |
54
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/shift_frame                  | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/reset_bit_count              |                1 |              4 |
55
-|  CLK_IBUF_BUFG                            | eqOp2_in                                                                   | tmrVal[3]_i_1_n_0                                                          |                2 |              4 |
56
-|  CLK_IBUF_BUFG                            |                                                                            | sendStr[3][0]                                                              |                1 |              5 |
57
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_1_n_0 |                2 |              7 |
58
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/g0_b0_n_0                                      |                                                                            |                2 |              7 |
59
-|  CLK_IBUF_BUFG                            | uartSend                                                                   |                                                                            |                2 |              7 |
60
-|  CLK_IBUF_BUFG                            | uartData                                                                   |                                                                            |                6 |              7 |
61
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/load_rx_data_reg_n_0         |                                                                            |                2 |              8 |
62
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_inc[7]_i_1_n_0                               |                                                                            |                3 |              8 |
63
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_inc[7]_i_1_n_0                               |                                                                            |                4 |              8 |
64
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_1_n_0             |                                                                            |                2 |             10 |
65
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_new_reg_n_0                                  |                                                                            |                3 |             11 |
66
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_1_n_0 |                3 |             11 |
67
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/eqOp4_in                                                     | Inst_vga_ctrl/v_cntr_reg0                                                  |                3 |             12 |
68
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/vga_red_reg[3]_i_1_n_0                                       |                2 |             12 |
69
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/eqOp4_in                                                     |                3 |             12 |
70
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_new_reg_n_0                                  |                                                                            |                4 |             12 |
71
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_1_n_0 |                4 |             14 |
72
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_UART_TX_CTRL/bitTmr[0]_i_1_n_0                                        |                4 |             14 |
73
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[4][0]_i_1_n_0                              |                4 |             16 |
74
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[1][0]_i_1_n_0                              |                4 |             16 |
75
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[2][0]_i_1_n_0                              |                4 |             16 |
76
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[3][0]_i_1_n_0                              |                4 |             16 |
77
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[0][0]_i_1_n_0                              |                4 |             16 |
78
-|  CLK_IBUF_BUFG                            |                                                                            |                                                                            |               10 |             17 |
79
-|  CLK_IBUF_BUFG                            |                                                                            | reset_cntr0                                                                |                5 |             18 |
80
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/v_sync_reg                                                   |                                                                            |               10 |             23 |
81
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_timeout_cnt_reg_n_0                      |                7 |             24 |
82
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_periodic_check_cnt                       |                6 |             26 |
83
-|  CLK_IBUF_BUFG                            |                                                                            | tmrCntr0                                                                   |                7 |             27 |
84
-|  CLK_IBUF_BUFG                            | uartData                                                                   | strIndex0                                                                  |                8 |             31 |
85
-|  CLK_IBUF_BUFG                            | Inst_UART_TX_CTRL/txBit_i_1_n_0                                            | Inst_UART_TX_CTRL/READY                                                    |                9 |             32 |
86
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            |                                                                            |               47 |            115 |
87
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
88
-
89
-
90
-+--------+-----------------------+
91
-| Fanout | Number of ControlSets |
92
-+--------+-----------------------+
93
-| 4      |                     5 |
94
-| 5      |                     1 |
95
-| 7      |                     4 |
96
-| 8      |                     3 |
97
-| 10     |                     1 |
98
-| 11     |                     2 |
99
-| 12     |                     4 |
100
-| 14     |                     2 |
101
-| 16+    |                    14 |
102
-+--------+-----------------------+
103
-
104
-

+ 0
- 35
proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
-------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:01 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_drc -file GPIO_demo_drc_opted.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Synthesized
11
-------------------------------------------------------------------------------------
12
-
13
-Report DRC
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-           Ruledeck: default
26
-             Max violations: <unlimited>
27
-             Violations found: 0
28
-+------+----------+-------------+------------+
29
-| Rule | Severity | Description | Violations |
30
-+------+----------+-------------+------------+
31
-+------+----------+-------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.pb View File


+ 0
- 35
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
----------------------------------------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:37 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_drc -file GPIO_demo_drc_routed.rpt -pb GPIO_demo_drc_routed.pb -rpx GPIO_demo_drc_routed.rpx
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Routed
11
----------------------------------------------------------------------------------------------------------------------
12
-
13
-Report DRC
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-           Ruledeck: default
26
-             Max violations: <unlimited>
27
-             Violations found: 0
28
-+------+----------+-------------+------------+
29
-| Rule | Severity | Description | Violations |
30
-+------+----------+-------------+------------+
31
-+------+----------+-------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpx View File


+ 0
- 277
proj/GPIO.runs/impl_1/GPIO_demo_io_placed.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
-------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:08 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_io -file GPIO_demo_io_placed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35t
9
-| Speed File   : -1
10
-| Package      : cpg236
11
-------------------------------------------------------------------------------------
12
-
13
-IO Information
14
-
15
-Table of Contents
16
------------------
17
-1. Summary
18
-2. IO Assignments by Package Pin
19
-
20
-1. Summary
21
-----------
22
-
23
-+---------------+
24
-| Total User IO |
25
-+---------------+
26
-|            67 |
27
-+---------------+
28
-
29
-
30
-2. IO Assignments by Package Pin
31
---------------------------------
32
-
33
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
34
-| Pin Number | Signal Name  | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity |
35
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
36
-| A1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
37
-| A2         |              |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
38
-| A3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
39
-| A4         |              |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
40
-| A5         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
41
-| A6         |              |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
42
-| A7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
43
-| A8         |              |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
44
-| A9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
45
-| A10        |              |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
46
-| A11        |              | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
47
-| A12        |              | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
48
-| A13        |              | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
49
-| A14        |              | High Range | IO_L6P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
50
-| A15        |              | High Range | IO_L6N_T0_VREF_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
51
-| A16        |              | High Range | IO_L12P_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
52
-| A17        |              | High Range | IO_L12N_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
53
-| A18        | UART_TXD     | High Range | IO_L19N_T3_VREF_16           | OUTPUT        | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
54
-| A19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
55
-| B1         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
56
-| B2         |              |            | MGTPTXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
57
-| B3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
58
-| B4         |              |            | MGTPRXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
59
-| B5         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
60
-| B6         |              |            | MGTPRXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
61
-| B7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
62
-| B8         |              |            | MGTREFCLK0P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
63
-| B9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
64
-| B10        |              |            | MGTREFCLK1P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
65
-| B11        |              | Dedicated  | DXN_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
66
-| B12        |              | Dedicated  | VREFP_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
67
-| B13        |              | Dedicated  | VN_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
68
-| B14        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
69
-| B15        |              | High Range | IO_L11N_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
70
-| B16        |              | High Range | IO_L13N_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
71
-| B17        | PS2_DATA     | High Range | IO_L14N_T2_SRCC_16           | BIDIR         | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      | PULLUP    |          |      | NONE             |
72
-| B18        |              | High Range | IO_L19P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
73
-| B19        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
74
-| C1         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
75
-| C2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
76
-| C3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
77
-| C4         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
78
-| C5         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
79
-| C6         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
80
-| C7         |              |            | MGTRREF_216                  | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
81
-| C8         |              | Dedicated  | TCK_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
82
-| C9         |              | Dedicated  | VCCBATT_0                    | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
83
-| C10        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
84
-| C11        |              | Dedicated  | CCLK_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
85
-| C12        |              | Dedicated  | GNDADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
86
-| C13        |              | Dedicated  | VCCADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
87
-| C14        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
88
-| C15        |              | High Range | IO_L11P_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
89
-| C16        |              | High Range | IO_L13P_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
90
-| C17        | PS2_CLK      | High Range | IO_L14P_T2_SRCC_16           | BIDIR         | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      | PULLUP    |          |      | NONE             |
91
-| C18        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
92
-| C19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
93
-| D1         |              |            | MGTPTXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
94
-| D2         |              |            | MGTPTXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
95
-| D3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
96
-| D17        | VGA_GREEN[3] | High Range | IO_0_14                      | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
97
-| D18        |              | High Range | IO_L1P_T0_D00_MOSI_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
98
-| D19        |              | High Range | IO_L1N_T0_D01_DIN_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
99
-| E1         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
100
-| E2         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
101
-| E3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
102
-| E17        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
103
-| E18        |              | High Range | IO_L3P_T0_DQS_PUDC_B_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
104
-| E19        | LED[1]       | High Range | IO_L3N_T0_DQS_EMCCLK_14      | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
105
-| F1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
106
-| F2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
107
-| F3         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
108
-| F17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
109
-| F18        |              | High Range | IO_L2N_T0_D03_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
110
-| F19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
111
-| G1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
112
-| G2         |              | High Range | IO_L1N_T0_AD4N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
113
-| G3         |              | High Range | IO_L1P_T0_AD4P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
114
-| G7         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
115
-| G8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
116
-| G9         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
117
-| G10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
118
-| G11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
119
-| G12        |              | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
120
-| G13        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
121
-| G17        | VGA_GREEN[2] | High Range | IO_L5N_T0_D07_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
122
-| G18        |              | High Range | IO_L2P_T0_D02_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
123
-| G19        | VGA_RED[0]   | High Range | IO_L4N_T0_D05_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
124
-| H1         |              | High Range | IO_L3P_T0_DQS_AD5P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
125
-| H2         |              | High Range | IO_L2P_T0_AD12P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
126
-| H3         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
127
-| H7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
128
-| H8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
129
-| H9         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
130
-| H10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
131
-| H11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
132
-| H12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
133
-| H13        |              |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |
134
-| H17        | VGA_GREEN[1] | High Range | IO_L5P_T0_D06_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
135
-| H18        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
136
-| H19        | VGA_RED[1]   | High Range | IO_L4P_T0_D04_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
137
-| J1         |              | High Range | IO_L3N_T0_DQS_AD5N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
138
-| J2         |              | High Range | IO_L2N_T0_AD12N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
139
-| J3         |              | High Range | IO_L7P_T1_AD6P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
140
-| J7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
141
-| J8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
142
-| J9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
143
-| J10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
144
-| J11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
145
-| J12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
146
-| J13        |              |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |
147
-| J17        | VGA_GREEN[0] | High Range | IO_L7P_T1_D09_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
148
-| J18        | VGA_BLUE[3]  | High Range | IO_L7N_T1_D10_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
149
-| J19        | VGA_RED[2]   | High Range | IO_L6N_T0_D08_VREF_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
150
-| K1         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
151
-| K2         |              | High Range | IO_L5P_T0_AD13P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
152
-| K3         |              | High Range | IO_L7N_T1_AD6N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
153
-| K7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
154
-| K8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
155
-| K12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
156
-| K13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
157
-| K17        |              | High Range | IO_L12N_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
158
-| K18        | VGA_BLUE[2]  | High Range | IO_L8N_T1_D12_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
159
-| K19        |              | High Range | IO_L6P_T0_FCS_B_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
160
-| L1         | LED[15]      | High Range | IO_L6N_T0_VREF_35            | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
161
-| L2         |              | High Range | IO_L5N_T0_AD13N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
162
-| L3         |              | High Range | IO_L8P_T1_AD14P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
163
-| L7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
164
-| L8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
165
-| L9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
166
-| L10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
167
-| L11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
168
-| L12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
169
-| L13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
170
-| L17        |              | High Range | IO_L12P_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
171
-| L18        | VGA_BLUE[1]  | High Range | IO_L8P_T1_D11_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
172
-| L19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
173
-| M1         |              | High Range | IO_L9N_T1_DQS_AD7N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
174
-| M2         |              | High Range | IO_L9P_T1_DQS_AD7P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
175
-| M3         |              | High Range | IO_L8N_T1_AD14N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
176
-| M7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
177
-| M8         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
178
-| M9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
179
-| M10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
180
-| M11        |              |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
181
-| M12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
182
-| M13        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
183
-| M17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
184
-| M18        |              | High Range | IO_L11P_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
185
-| M19        |              | High Range | IO_L11N_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
186
-| N1         |              | High Range | IO_L10N_T1_AD15N_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
187
-| N2         |              | High Range | IO_L10P_T1_AD15P_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
188
-| N3         | LED[13]      | High Range | IO_L12P_T1_MRCC_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
189
-| N7         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
190
-| N8         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
191
-| N9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
192
-| N10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
193
-| N11        |              |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
194
-| N12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
195
-| N13        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
196
-| N17        |              | High Range | IO_L13P_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
197
-| N18        | VGA_BLUE[0]  | High Range | IO_L9P_T1_DQS_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
198
-| N19        | VGA_RED[3]   | High Range | IO_L9N_T1_DQS_D13_14         | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
199
-| P1         | LED[14]      | High Range | IO_L19N_T3_VREF_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
200
-| P2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
201
-| P3         | LED[12]      | High Range | IO_L12N_T1_MRCC_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
202
-| P17        |              | High Range | IO_L13N_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
203
-| P18        |              | High Range | IO_L14P_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
204
-| P19        | VGA_HS       | High Range | IO_L10P_T1_D14_14            | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
205
-| R1         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
206
-| R2         | SW[15]       | High Range | IO_L1P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
207
-| R3         | SW[11]       | High Range | IO_L2P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
208
-| R17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
209
-| R18        |              | High Range | IO_L14N_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
210
-| R19        | VGA_VS       | High Range | IO_L10N_T1_D15_14            | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
211
-| T1         | SW[14]       | High Range | IO_L3P_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
212
-| T2         | SW[10]       | High Range | IO_L1N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
213
-| T3         | SW[9]        | High Range | IO_L2N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
214
-| T17        | BTN[2]       | High Range | IO_L17P_T2_A14_D30_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
215
-| T18        | BTN[0]       | High Range | IO_L17N_T2_A13_D29_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
216
-| T19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
217
-| U1         | SW[13]       | High Range | IO_L3N_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
218
-| U2         | SSEG_AN[0]   | High Range | IO_L9N_T1_DQS_34             | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
219
-| U3         | LED[11]      | High Range | IO_L9P_T1_DQS_34             | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
220
-| U4         | SSEG_AN[1]   | High Range | IO_L11P_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
221
-| U5         | SSEG_CA[4]   | High Range | IO_L16P_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
222
-| U6         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
223
-| U7         | SSEG_CA[6]   | High Range | IO_L19P_T3_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
224
-| U8         | SSEG_CA[2]   | High Range | IO_L14P_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
225
-| U9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
226
-| U10        |              | Dedicated  | M2_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
227
-| U11        |              | Dedicated  | INIT_B_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
228
-| U12        |              | Dedicated  | DONE_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
229
-| U13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
230
-| U14        | LED[6]       | High Range | IO_25_14                     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
231
-| U15        | LED[5]       | High Range | IO_L23P_T3_A03_D19_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
232
-| U16        | LED[0]       | High Range | IO_L23N_T3_A02_D18_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
233
-| U17        | BTN[3]       | High Range | IO_L18P_T2_A12_D28_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
234
-| U18        | BTN[4]       | High Range | IO_L18N_T2_A11_D27_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
235
-| U19        | LED[2]       | High Range | IO_L15P_T2_DQS_RDWR_B_14     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
236
-| V1         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
237
-| V2         | SW[8]        | High Range | IO_L5P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
238
-| V3         | LED[9]       | High Range | IO_L6P_T0_34                 | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
239
-| V4         | SSEG_AN[2]   | High Range | IO_L11N_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
240
-| V5         | SSEG_CA[5]   | High Range | IO_L16N_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
241
-| V6         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
242
-| V7         | SSEG_CA[7]   | High Range | IO_L19N_T3_VREF_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
243
-| V8         | SSEG_CA[3]   | High Range | IO_L14N_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
244
-| V9         |              | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
245
-| V10        |              | Dedicated  | PROGRAM_B_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
246
-| V11        |              | Dedicated  | CFGBVS_0                     | Config        |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
247
-| V12        |              | Dedicated  | M0_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
248
-| V13        | LED[8]       | High Range | IO_L24P_T3_A01_D17_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
249
-| V14        | LED[7]       | High Range | IO_L24N_T3_A00_D16_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
250
-| V15        | SW[5]        | High Range | IO_L21P_T3_DQS_14            | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
251
-| V16        | SW[1]        | High Range | IO_L19P_T3_A10_D26_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
252
-| V17        | SW[0]        | High Range | IO_L19N_T3_A09_D25_VREF_14   | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
253
-| V18        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
254
-| V19        | LED[3]       | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
255
-| W1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
256
-| W2         | SW[12]       | High Range | IO_L5N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
257
-| W3         | LED[10]      | High Range | IO_L6N_T0_VREF_34            | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
258
-| W4         | SSEG_AN[3]   | High Range | IO_L12N_T1_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
259
-| W5         | CLK          | High Range | IO_L12P_T1_MRCC_34           | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
260
-| W6         | SSEG_CA[1]   | High Range | IO_L13N_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
261
-| W7         | SSEG_CA[0]   | High Range | IO_L13P_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
262
-| W8         |              | Dedicated  | TDO_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
263
-| W9         |              | Dedicated  | TMS_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
264
-| W10        |              | Dedicated  | TDI_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
265
-| W11        |              | Dedicated  | M1_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
266
-| W12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
267
-| W13        | SW[7]        | High Range | IO_L22P_T3_A05_D21_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
268
-| W14        | SW[6]        | High Range | IO_L22N_T3_A04_D20_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
269
-| W15        | SW[4]        | High Range | IO_L21N_T3_DQS_A06_D22_14    | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
270
-| W16        | SW[2]        | High Range | IO_L20P_T3_A08_D24_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
271
-| W17        | SW[3]        | High Range | IO_L20N_T3_A07_D23_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
272
-| W18        | LED[4]       | High Range | IO_L16P_T2_CSI_B_14          | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
273
-| W19        | BTN[1]       | High Range | IO_L16N_T2_A15_D31_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
274
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
275
-* Default value
276
-
277
-

+ 0
- 205
proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
--------------------------------------------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:38 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_methodology -file GPIO_demo_methodology_drc_routed.rpt -rpx GPIO_demo_methodology_drc_routed.rpx
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Routed
11
--------------------------------------------------------------------------------------------------------------------------
12
-
13
-Report Methodology
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-             Max violations: <unlimited>
26
-             Violations found: 34
27
-+-----------+----------+-------------------------------+------------+
28
-| Rule      | Severity | Description                   | Violations |
29
-+-----------+----------+-------------------------------+------------+
30
-| TIMING-18 | Warning  | Missing input or output delay | 34         |
31
-+-----------+----------+-------------------------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-TIMING-18#1 Warning
36
-Missing input or output delay  
37
-An input delay is missing on BTN[0] relative to clock(s) sys_clk_pin 
38
-Related violations: <none>
39
-
40
-TIMING-18#2 Warning
41
-Missing input or output delay  
42
-An input delay is missing on BTN[1] relative to clock(s) sys_clk_pin 
43
-Related violations: <none>
44
-
45
-TIMING-18#3 Warning
46
-Missing input or output delay  
47
-An input delay is missing on BTN[2] relative to clock(s) sys_clk_pin 
48
-Related violations: <none>
49
-
50
-TIMING-18#4 Warning
51
-Missing input or output delay  
52
-An input delay is missing on BTN[3] relative to clock(s) sys_clk_pin 
53
-Related violations: <none>
54
-
55
-TIMING-18#5 Warning
56
-Missing input or output delay  
57
-An input delay is missing on BTN[4] relative to clock(s) sys_clk_pin 
58
-Related violations: <none>
59
-
60
-TIMING-18#6 Warning
61
-Missing input or output delay  
62
-An input delay is missing on PS2_CLK relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
63
-Related violations: <none>
64
-
65
-TIMING-18#7 Warning
66
-Missing input or output delay  
67
-An input delay is missing on PS2_DATA relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
68
-Related violations: <none>
69
-
70
-TIMING-18#8 Warning
71
-Missing input or output delay  
72
-An output delay is missing on SSEG_AN[0] relative to clock(s) sys_clk_pin 
73
-Related violations: <none>
74
-
75
-TIMING-18#9 Warning
76
-Missing input or output delay  
77
-An output delay is missing on SSEG_AN[1] relative to clock(s) sys_clk_pin 
78
-Related violations: <none>
79
-
80
-TIMING-18#10 Warning
81
-Missing input or output delay  
82
-An output delay is missing on SSEG_AN[2] relative to clock(s) sys_clk_pin 
83
-Related violations: <none>
84
-
85
-TIMING-18#11 Warning
86
-Missing input or output delay  
87
-An output delay is missing on SSEG_AN[3] relative to clock(s) sys_clk_pin 
88
-Related violations: <none>
89
-
90
-TIMING-18#12 Warning
91
-Missing input or output delay  
92
-An output delay is missing on SSEG_CA[0] relative to clock(s) sys_clk_pin 
93
-Related violations: <none>
94
-
95
-TIMING-18#13 Warning
96
-Missing input or output delay  
97
-An output delay is missing on SSEG_CA[1] relative to clock(s) sys_clk_pin 
98
-Related violations: <none>
99
-
100
-TIMING-18#14 Warning
101
-Missing input or output delay  
102
-An output delay is missing on SSEG_CA[2] relative to clock(s) sys_clk_pin 
103
-Related violations: <none>
104
-
105
-TIMING-18#15 Warning
106
-Missing input or output delay  
107
-An output delay is missing on SSEG_CA[3] relative to clock(s) sys_clk_pin 
108
-Related violations: <none>
109
-
110
-TIMING-18#16 Warning
111
-Missing input or output delay  
112
-An output delay is missing on SSEG_CA[4] relative to clock(s) sys_clk_pin 
113
-Related violations: <none>
114
-
115
-TIMING-18#17 Warning
116
-Missing input or output delay  
117
-An output delay is missing on SSEG_CA[5] relative to clock(s) sys_clk_pin 
118
-Related violations: <none>
119
-
120
-TIMING-18#18 Warning
121
-Missing input or output delay  
122
-An output delay is missing on SSEG_CA[6] relative to clock(s) sys_clk_pin 
123
-Related violations: <none>
124
-
125
-TIMING-18#19 Warning
126
-Missing input or output delay  
127
-An output delay is missing on SSEG_CA[7] relative to clock(s) sys_clk_pin 
128
-Related violations: <none>
129
-
130
-TIMING-18#20 Warning
131
-Missing input or output delay  
132
-An output delay is missing on UART_TXD relative to clock(s) sys_clk_pin 
133
-Related violations: <none>
134
-
135
-TIMING-18#21 Warning
136
-Missing input or output delay  
137
-An output delay is missing on VGA_BLUE[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
138
-Related violations: <none>
139
-
140
-TIMING-18#22 Warning
141
-Missing input or output delay  
142
-An output delay is missing on VGA_BLUE[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
143
-Related violations: <none>
144
-
145
-TIMING-18#23 Warning
146
-Missing input or output delay  
147
-An output delay is missing on VGA_BLUE[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
148
-Related violations: <none>
149
-
150
-TIMING-18#24 Warning
151
-Missing input or output delay  
152
-An output delay is missing on VGA_BLUE[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
153
-Related violations: <none>
154
-
155
-TIMING-18#25 Warning
156
-Missing input or output delay  
157
-An output delay is missing on VGA_GREEN[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
158
-Related violations: <none>
159
-
160
-TIMING-18#26 Warning
161
-Missing input or output delay  
162
-An output delay is missing on VGA_GREEN[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
163
-Related violations: <none>
164
-
165
-TIMING-18#27 Warning
166
-Missing input or output delay  
167
-An output delay is missing on VGA_GREEN[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
168
-Related violations: <none>
169
-
170
-TIMING-18#28 Warning
171
-Missing input or output delay  
172
-An output delay is missing on VGA_GREEN[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
173
-Related violations: <none>
174
-
175
-TIMING-18#29 Warning
176
-Missing input or output delay  
177
-An output delay is missing on VGA_HS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
178
-Related violations: <none>
179
-
180
-TIMING-18#30 Warning
181
-Missing input or output delay  
182
-An output delay is missing on VGA_RED[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
183
-Related violations: <none>
184
-
185
-TIMING-18#31 Warning
186
-Missing input or output delay  
187
-An output delay is missing on VGA_RED[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
188
-Related violations: <none>
189
-
190
-TIMING-18#32 Warning
191
-Missing input or output delay  
192
-An output delay is missing on VGA_RED[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
193
-Related violations: <none>
194
-
195
-TIMING-18#33 Warning
196
-Missing input or output delay  
197
-An output delay is missing on VGA_RED[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
198
-Related violations: <none>
199
-
200
-TIMING-18#34 Warning
201
-Missing input or output delay  
202
-An output delay is missing on VGA_VS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
203
-Related violations: <none>
204
-
205
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpx View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp View File


+ 0
- 157
proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
--------------------------------------------------------------------------------------------------------------------------------------------------
3
-| Tool Version     : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date             : Fri Apr 09 23:16:38 2021
5
-| Host             : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command          : report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
7
-| Design           : GPIO_demo
8
-| Device           : xc7a35tcpg236-1
9
-| Design State     : routed
10
-| Grade            : commercial
11
-| Process          : typical
12
-| Characterization : Production
13
--------------------------------------------------------------------------------------------------------------------------------------------------
14
-
15
-Power Report
16
-
17
-Table of Contents
18
------------------
19
-1. Summary
20
-1.1 On-Chip Components
21
-1.2 Power Supply Summary
22
-1.3 Confidence Level
23
-2. Settings
24
-2.1 Environment
25
-2.2 Clock Constraints
26
-3. Detailed Reports
27
-3.1 By Hierarchy
28
-
29
-1. Summary
30
-----------
31
-
32
-+--------------------------+-------+
33
-| Total On-Chip Power (W)  | 0.223 |
34
-| Dynamic (W)              | 0.151 |
35
-| Device Static (W)        | 0.072 |
36
-| Effective TJA (C/W)      | 5.0   |
37
-| Max Ambient (C)          | 83.9  |
38
-| Junction Temperature (C) | 26.1  |
39
-| Confidence Level         | Low   |
40
-| Setting File             | ---   |
41
-| Simulation Activity File | ---   |
42
-| Design Nets Matched      | NA    |
43
-+--------------------------+-------+
44
-
45
-
46
-1.1 On-Chip Components
47
-----------------------
48
-
49
-+----------------+-----------+----------+-----------+-----------------+
50
-| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
51
-+----------------+-----------+----------+-----------+-----------------+
52
-| Clocks         |     0.005 |        5 |       --- |             --- |
53
-| Slice Logic    |     0.003 |     1426 |       --- |             --- |
54
-|   LUT as Logic |     0.002 |      564 |     20800 |            2.71 |
55
-|   CARRY4       |    <0.001 |      132 |      8150 |            1.62 |
56
-|   Register     |    <0.001 |      578 |     41600 |            1.39 |
57
-|   F7/F8 Muxes  |    <0.001 |        3 |     32600 |           <0.01 |
58
-|   Others       |     0.000 |       18 |       --- |             --- |
59
-| Signals        |     0.002 |     1137 |       --- |             --- |
60
-| MMCM           |     0.123 |        1 |         5 |           20.00 |
61
-| I/O            |     0.018 |       67 |       106 |           63.21 |
62
-| Static Power   |     0.072 |          |           |                 |
63
-| Total          |     0.223 |          |           |                 |
64
-+----------------+-----------+----------+-----------+-----------------+
65
-
66
-
67
-1.2 Power Supply Summary
68
-------------------------
69
-
70
-+-----------+-------------+-----------+-------------+------------+
71
-| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
72
-+-----------+-------------+-----------+-------------+------------+
73
-| Vccint    |       1.000 |     0.020 |       0.010 |      0.010 |
74
-| Vccaux    |       1.800 |     0.081 |       0.069 |      0.013 |
75
-| Vcco33    |       3.300 |     0.006 |       0.005 |      0.001 |
76
-| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
77
-| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
78
-| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
79
-| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
80
-| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
81
-| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
82
-| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |
83
-| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
84
-| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
85
-| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
86
-+-----------+-------------+-----------+-------------+------------+
87
-
88
-
89
-1.3 Confidence Level
90
---------------------
91
-
92
-+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
93
-| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
94
-+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
95
-| Design implementation state | High       | Design is routed                                       |                                                                                                            |
96
-| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
97
-| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
98
-| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
99
-| Device models               | High       | Device models are Production                           |                                                                                                            |
100
-|                             |            |                                                        |                                                                                                            |
101
-| Overall confidence level    | Low        |                                                        |                                                                                                            |
102
-+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
103
-
104
-
105
-2. Settings
106
------------
107
-
108
-2.1 Environment
109
----------------
110
-
111
-+-----------------------+--------------------------+
112
-| Ambient Temp (C)      | 25.0                     |
113
-| ThetaJA (C/W)         | 5.0                      |
114
-| Airflow (LFM)         | 250                      |
115
-| Heat Sink             | medium (Medium Profile)  |
116
-| ThetaSA (C/W)         | 4.6                      |
117
-| Board Selection       | medium (10"x10")         |
118
-| # of Board Layers     | 12to15 (12 to 15 Layers) |
119
-| Board Temperature (C) | 25.0                     |
120
-+-----------------------+--------------------------+
121
-
122
-
123
-2.2 Clock Constraints
124
----------------------
125
-
126
-+--------------------+----------------------------------------------------+-----------------+
127
-| Clock              | Domain                                             | Constraint (ns) |
128
-+--------------------+----------------------------------------------------+-----------------+
129
-| clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |             9.3 |
130
-| clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |            10.0 |
131
-| sys_clk_pin        | CLK                                                |            10.0 |
132
-+--------------------+----------------------------------------------------+-----------------+
133
-
134
-
135
-3. Detailed Reports
136
--------------------
137
-
138
-3.1 By Hierarchy
139
-----------------
140
-
141
-+-----------------------------+-----------+
142
-| Name                        | Power (W) |
143
-+-----------------------------+-----------+
144
-| GPIO_demo                   |     0.151 |
145
-|   Inst_UART_TX_CTRL         |    <0.001 |
146
-|   Inst_btn_debounce         |    <0.001 |
147
-|   Inst_vga_ctrl             |     0.130 |
148
-|     Inst_MouseCtl           |     0.004 |
149
-|       Inst_Ps2Interface     |     0.001 |
150
-|         ps2_clk_IOBUF_inst  |     0.000 |
151
-|         ps2_data_IOBUF_inst |     0.000 |
152
-|     Inst_MouseDisplay       |    <0.001 |
153
-|     clk_wiz_0_inst          |     0.124 |
154
-|       U0                    |     0.124 |
155
-+-----------------------------+-----------+
156
-
157
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpx View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_power_summary_routed.pb View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_route_status.pb View File


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proj/GPIO.runs/impl_1/GPIO_demo_route_status.rpt View File

1
-Design Route Status
2
-                                               :      # nets :
3
-   ------------------------------------------- : ----------- :
4
-   # of logical nets.......................... :        1888 :
5
-       # of nets not needing routing.......... :         743 :
6
-           # of internally routed nets........ :         743 :
7
-       # of routable nets..................... :        1145 :
8
-           # of fully routed nets............. :        1145 :
9
-       # of nets with routing errors.......... :           0 :
10
-   ------------------------------------------- : ----------- :
11
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp View File


+ 0
- 2891
proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpt
File diff suppressed because it is too large
View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_timing_summary_routed.rpx View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.pb View File


+ 0
- 212
proj/GPIO.runs/impl_1/GPIO_demo_utilization_placed.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
----------------------------------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:08 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_utilization -file GPIO_demo_utilization_placed.rpt -pb GPIO_demo_utilization_placed.pb
7
-| Design       : GPIO_demo
8
-| Device       : 7a35tcpg236-1
9
-| Design State : Fully Placed
10
----------------------------------------------------------------------------------------------------------------
11
-
12
-Utilization Design Information
13
-
14
-Table of Contents
15
------------------
16
-1. Slice Logic
17
-1.1 Summary of Registers by Type
18
-2. Slice Logic Distribution
19
-3. Memory
20
-4. DSP
21
-5. IO and GT Specific
22
-6. Clocking
23
-7. Specific Feature
24
-8. Primitives
25
-9. Black Boxes
26
-10. Instantiated Netlists
27
-
28
-1. Slice Logic
29
---------------
30
-
31
-+-------------------------+------+-------+-----------+-------+
32
-|        Site Type        | Used | Fixed | Available | Util% |
33
-+-------------------------+------+-------+-----------+-------+
34
-| Slice LUTs              |  564 |     0 |     20800 |  2.71 |
35
-|   LUT as Logic          |  564 |     0 |     20800 |  2.71 |
36
-|   LUT as Memory         |    0 |     0 |      9600 |  0.00 |
37
-| Slice Registers         |  578 |     0 |     41600 |  1.39 |
38
-|   Register as Flip Flop |  578 |     0 |     41600 |  1.39 |
39
-|   Register as Latch     |    0 |     0 |     41600 |  0.00 |
40
-| F7 Muxes                |    3 |     0 |     16300 |  0.02 |
41
-| F8 Muxes                |    0 |     0 |      8150 |  0.00 |
42
-+-------------------------+------+-------+-----------+-------+
43
-
44
-
45
-1.1 Summary of Registers by Type
46
---------------------------------
47
-
48
-+-------+--------------+-------------+--------------+
49
-| Total | Clock Enable | Synchronous | Asynchronous |
50
-+-------+--------------+-------------+--------------+
51
-| 0     |            _ |           - |            - |
52
-| 0     |            _ |           - |          Set |
53
-| 0     |            _ |           - |        Reset |
54
-| 0     |            _ |         Set |            - |
55
-| 0     |            _ |       Reset |            - |
56
-| 0     |          Yes |           - |            - |
57
-| 0     |          Yes |           - |          Set |
58
-| 0     |          Yes |           - |        Reset |
59
-| 2     |          Yes |         Set |            - |
60
-| 576   |          Yes |       Reset |            - |
61
-+-------+--------------+-------------+--------------+
62
-
63
-
64
-2. Slice Logic Distribution
65
----------------------------
66
-
67
-+-------------------------------------------+------+-------+-----------+-------+
68
-|                 Site Type                 | Used | Fixed | Available | Util% |
69
-+-------------------------------------------+------+-------+-----------+-------+
70
-| Slice                                     |  282 |     0 |      8150 |  3.46 |
71
-|   SLICEL                                  |  182 |     0 |           |       |
72
-|   SLICEM                                  |  100 |     0 |           |       |
73
-| LUT as Logic                              |  564 |     0 |     20800 |  2.71 |
74
-|   using O5 output only                    |    0 |       |           |       |
75
-|   using O6 output only                    |  433 |       |           |       |
76
-|   using O5 and O6                         |  131 |       |           |       |
77
-| LUT as Memory                             |    0 |     0 |      9600 |  0.00 |
78
-|   LUT as Distributed RAM                  |    0 |     0 |           |       |
79
-|   LUT as Shift Register                   |    0 |     0 |           |       |
80
-| LUT Flip Flop Pairs                       |  171 |     0 |     20800 |  0.82 |
81
-|   fully used LUT-FF pairs                 |   54 |       |           |       |
82
-|   LUT-FF pairs with one unused LUT output |  110 |       |           |       |
83
-|   LUT-FF pairs with one unused Flip Flop  |  111 |       |           |       |
84
-| Unique Control Sets                       |   36 |       |           |       |
85
-+-------------------------------------------+------+-------+-----------+-------+
86
-* Note: Review the Control Sets Report for more information regarding control sets.
87
-
88
-
89
-3. Memory
90
----------
91
-
92
-+----------------+------+-------+-----------+-------+
93
-|    Site Type   | Used | Fixed | Available | Util% |
94
-+----------------+------+-------+-----------+-------+
95
-| Block RAM Tile |    0 |     0 |        50 |  0.00 |
96
-|   RAMB36/FIFO* |    0 |     0 |        50 |  0.00 |
97
-|   RAMB18       |    0 |     0 |       100 |  0.00 |
98
-+----------------+------+-------+-----------+-------+
99
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
100
-
101
-
102
-4. DSP
103
-------
104
-
105
-+-----------+------+-------+-----------+-------+
106
-| Site Type | Used | Fixed | Available | Util% |
107
-+-----------+------+-------+-----------+-------+
108
-| DSPs      |    0 |     0 |        90 |  0.00 |
109
-+-----------+------+-------+-----------+-------+
110
-
111
-
112
-5. IO and GT Specific
113
----------------------
114
-
115
-+-----------------------------+------+-------+-----------+-------+
116
-|          Site Type          | Used | Fixed | Available | Util% |
117
-+-----------------------------+------+-------+-----------+-------+
118
-| Bonded IOB                  |   67 |    67 |       106 | 63.21 |
119
-|   IOB Master Pads           |   30 |       |           |       |
120
-|   IOB Slave Pads            |   35 |       |           |       |
121
-| Bonded IPADs                |    0 |     0 |        10 |  0.00 |
122
-| Bonded OPADs                |    0 |     0 |         4 |  0.00 |
123
-| PHY_CONTROL                 |    0 |     0 |         5 |  0.00 |
124
-| PHASER_REF                  |    0 |     0 |         5 |  0.00 |
125
-| OUT_FIFO                    |    0 |     0 |        20 |  0.00 |
126
-| IN_FIFO                     |    0 |     0 |        20 |  0.00 |
127
-| IDELAYCTRL                  |    0 |     0 |         5 |  0.00 |
128
-| IBUFDS                      |    0 |     0 |       104 |  0.00 |
129
-| GTPE2_CHANNEL               |    0 |     0 |         2 |  0.00 |
130
-| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        20 |  0.00 |
131
-| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        20 |  0.00 |
132
-| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       250 |  0.00 |
133
-| IBUFDS_GTE2                 |    0 |     0 |         2 |  0.00 |
134
-| ILOGIC                      |    0 |     0 |       106 |  0.00 |
135
-| OLOGIC                      |    0 |     0 |       106 |  0.00 |
136
-+-----------------------------+------+-------+-----------+-------+
137
-
138
-
139
-6. Clocking
140
------------
141
-
142
-+------------+------+-------+-----------+-------+
143
-|  Site Type | Used | Fixed | Available | Util% |
144
-+------------+------+-------+-----------+-------+
145
-| BUFGCTRL   |    3 |     0 |        32 |  9.38 |
146
-| BUFIO      |    0 |     0 |        20 |  0.00 |
147
-| MMCME2_ADV |    1 |     0 |         5 | 20.00 |
148
-| PLLE2_ADV  |    0 |     0 |         5 |  0.00 |
149
-| BUFMRCE    |    0 |     0 |        10 |  0.00 |
150
-| BUFHCE     |    0 |     0 |        72 |  0.00 |
151
-| BUFR       |    0 |     0 |        20 |  0.00 |
152
-+------------+------+-------+-----------+-------+
153
-
154
-
155
-7. Specific Feature
156
--------------------
157
-
158
-+-------------+------+-------+-----------+-------+
159
-|  Site Type  | Used | Fixed | Available | Util% |
160
-+-------------+------+-------+-----------+-------+
161
-| BSCANE2     |    0 |     0 |         4 |  0.00 |
162
-| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
163
-| DNA_PORT    |    0 |     0 |         1 |  0.00 |
164
-| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
165
-| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
166
-| ICAPE2      |    0 |     0 |         2 |  0.00 |
167
-| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
168
-| STARTUPE2   |    0 |     0 |         1 |  0.00 |
169
-| XADC        |    0 |     0 |         1 |  0.00 |
170
-+-------------+------+-------+-----------+-------+
171
-
172
-
173
-8. Primitives
174
--------------
175
-
176
-+------------+------+---------------------+
177
-|  Ref Name  | Used | Functional Category |
178
-+------------+------+---------------------+
179
-| FDRE       |  576 |        Flop & Latch |
180
-| LUT2       |  207 |                 LUT |
181
-| LUT6       |  157 |                 LUT |
182
-| LUT4       |  136 |                 LUT |
183
-| CARRY4     |  132 |          CarryLogic |
184
-| LUT3       |   93 |                 LUT |
185
-| LUT5       |   72 |                 LUT |
186
-| OBUF       |   43 |                  IO |
187
-| LUT1       |   30 |                 LUT |
188
-| IBUF       |   24 |                  IO |
189
-| MUXF7      |    3 |               MuxFx |
190
-| BUFG       |    3 |               Clock |
191
-| OBUFT      |    2 |                  IO |
192
-| FDSE       |    2 |        Flop & Latch |
193
-| MMCME2_ADV |    1 |               Clock |
194
-+------------+------+---------------------+
195
-
196
-
197
-9. Black Boxes
198
---------------
199
-
200
-+----------+------+
201
-| Ref Name | Used |
202
-+----------+------+
203
-
204
-
205
-10. Instantiated Netlists
206
--------------------------
207
-
208
-+----------+------+
209
-| Ref Name | Used |
210
-+----------+------+
211
-
212
-

+ 0
- 244
proj/GPIO.runs/impl_1/ISEWrap.js View File

1
-//
2
-//  Vivado(TM)
3
-//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
4
-//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
5
-//
6
-
7
-// GLOBAL VARIABLES
8
-var ISEShell = new ActiveXObject( "WScript.Shell" );
9
-var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
10
-var ISERunDir = "";
11
-var ISELogFile = "runme.log";
12
-var ISELogFileStr = null;
13
-var ISELogEcho = true;
14
-var ISEOldVersionWSH = false;
15
-
16
-
17
-
18
-// BOOTSTRAP
19
-ISEInit();
20
-
21
-
22
-
23
-//
24
-// ISE FUNCTIONS
25
-//
26
-function ISEInit() {
27
-
28
-  // 1. RUN DIR setup
29
-  var ISEScrFP = WScript.ScriptFullName;
30
-  var ISEScrN = WScript.ScriptName;
31
-  ISERunDir = 
32
-    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
33
-
34
-  // 2. LOG file setup
35
-  ISELogFileStr = ISEOpenFile( ISELogFile );
36
-
37
-  // 3. LOG echo?
38
-  var ISEScriptArgs = WScript.Arguments;
39
-  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
40
-    if ( ISEScriptArgs(loopi) == "-quiet" ) {
41
-      ISELogEcho = false;
42
-      break;
43
-    }
44
-  }
45
-
46
-  // 4. WSH version check
47
-  var ISEOptimalVersionWSH = 5.6;
48
-  var ISECurrentVersionWSH = WScript.Version;
49
-  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
50
-
51
-    ISEStdErr( "" );
52
-    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
53
-	       ISEOptimalVersionWSH + " or higher. Downloads" );
54
-    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
55
-    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
56
-    ISEStdErr( "" );
57
-
58
-    ISEOldVersionWSH = true;
59
-  }
60
-
61
-}
62
-
63
-function ISEStep( ISEProg, ISEArgs ) {
64
-
65
-  // CHECK for a STOP FILE
66
-  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
67
-    ISEStdErr( "" );
68
-    ISEStdErr( "*** Halting run - EA reset detected ***" );
69
-    ISEStdErr( "" );
70
-    WScript.Quit( 1 );
71
-  }
72
-
73
-  // WRITE STEP HEADER to LOG
74
-  ISEStdOut( "" );
75
-  ISEStdOut( "*** Running " + ISEProg );
76
-  ISEStdOut( "    with args " + ISEArgs );
77
-  ISEStdOut( "" );
78
-
79
-  // LAUNCH!
80
-  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
81
-  if ( ISEExitCode != 0 ) {
82
-    WScript.Quit( ISEExitCode );
83
-  }
84
-
85
-}
86
-
87
-function ISEExec( ISEProg, ISEArgs ) {
88
-
89
-  var ISEStep = ISEProg;
90
-  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
91
-    ISEProg += ".bat";
92
-  }
93
-
94
-  var ISECmdLine = ISEProg + " " + ISEArgs;
95
-  var ISEExitCode = 1;
96
-
97
-  if ( ISEOldVersionWSH ) { // WSH 5.1
98
-
99
-    // BEGIN file creation
100
-    ISETouchFile( ISEStep, "begin" );
101
-
102
-    // LAUNCH!
103
-    ISELogFileStr.Close();
104
-    ISECmdLine = 
105
-      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
106
-    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
107
-    ISELogFileStr = ISEOpenFile( ISELogFile );
108
-
109
-  } else {  // WSH 5.6
110
-
111
-    // LAUNCH!
112
-    ISEShell.CurrentDirectory = ISERunDir;
113
-
114
-    // Redirect STDERR to STDOUT
115
-    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
116
-    var ISEProcess = ISEShell.Exec( ISECmdLine );
117
-    
118
-    // BEGIN file creation
119
-    var ISENetwork = WScript.CreateObject( "WScript.Network" );
120
-    var ISEHost = ISENetwork.ComputerName;
121
-    var ISEUser = ISENetwork.UserName;
122
-    var ISEPid = ISEProcess.ProcessID;
123
-    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
124
-    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
125
-    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
126
-    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
127
-			    "\" Owner=\"" + ISEUser + 
128
-			    "\" Host=\"" + ISEHost + 
129
-			    "\" Pid=\"" + ISEPid +
130
-			    "\">" );
131
-    ISEBeginFile.WriteLine( "    </Process>" );
132
-    ISEBeginFile.WriteLine( "</ProcessHandle>" );
133
-    ISEBeginFile.Close();
134
-    
135
-    var ISEOutStr = ISEProcess.StdOut;
136
-    var ISEErrStr = ISEProcess.StdErr;
137
-    
138
-    // WAIT for ISEStep to finish
139
-    while ( ISEProcess.Status == 0 ) {
140
-      
141
-      // dump stdout then stderr - feels a little arbitrary
142
-      while ( !ISEOutStr.AtEndOfStream ) {
143
-        ISEStdOut( ISEOutStr.ReadLine() );
144
-      }  
145
-      
146
-      WScript.Sleep( 100 );
147
-    }
148
-
149
-    ISEExitCode = ISEProcess.ExitCode;
150
-  }
151
-
152
-  ISELogFileStr.Close();
153
-
154
-  // END/ERROR file creation
155
-  if ( ISEExitCode != 0 ) {    
156
-    ISETouchFile( ISEStep, "error" );
157
-    
158
-  } else {
159
-    ISETouchFile( ISEStep, "end" );
160
-  }
161
-
162
-  return ISEExitCode;
163
-}
164
-
165
-
166
-//
167
-// UTILITIES
168
-//
169
-function ISEStdOut( ISELine ) {
170
-
171
-  ISELogFileStr.WriteLine( ISELine );
172
-  
173
-  if ( ISELogEcho ) {
174
-    WScript.StdOut.WriteLine( ISELine );
175
-  }
176
-}
177
-
178
-function ISEStdErr( ISELine ) {
179
-  
180
-  ISELogFileStr.WriteLine( ISELine );
181
-
182
-  if ( ISELogEcho ) {
183
-    WScript.StdErr.WriteLine( ISELine );
184
-  }
185
-}
186
-
187
-function ISETouchFile( ISERoot, ISEStatus ) {
188
-
189
-  var ISETFile = 
190
-    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
191
-  ISETFile.Close();
192
-}
193
-
194
-function ISEOpenFile( ISEFilename ) {
195
-
196
-  // This function has been updated to deal with a problem seen in CR #870871.
197
-  // In that case the user runs a script that runs impl_1, and then turns around
198
-  // and runs impl_1 -to_step write_bitstream. That second run takes place in
199
-  // the same directory, which means we may hit some of the same files, and in
200
-  // particular, we will open the runme.log file. Even though this script closes
201
-  // the file (now), we see cases where a subsequent attempt to open the file
202
-  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
203
-  // play? In any case, we try to work around this by first waiting if the file
204
-  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
205
-  // and try to open the file 10 times with a one second delay after each attempt.
206
-  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
207
-  // If there is an unrecognized exception when trying to open the file, we output
208
-  // an error message and write details to an exception.log file.
209
-  var ISEFullPath = ISERunDir + "/" + ISEFilename;
210
-  if (ISEFileSys.FileExists(ISEFullPath)) {
211
-    // File is already there. This could be a problem. Wait in case it is still in use.
212
-    WScript.Sleep(5000);
213
-  }
214
-  var i;
215
-  for (i = 0; i < 10; ++i) {
216
-    try {
217
-      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
218
-    } catch (exception) {
219
-      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
220
-      if (error_code == 52) { // 52 is bad file name or number.
221
-        // Wait a second and try again.
222
-        WScript.Sleep(1000);
223
-        continue;
224
-      } else {
225
-        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
226
-        var exceptionFilePath = ISERunDir + "/exception.log";
227
-        if (!ISEFileSys.FileExists(exceptionFilePath)) {
228
-          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
229
-          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
230
-          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
231
-          exceptionFile.WriteLine("\tException name: " + exception.name);
232
-          exceptionFile.WriteLine("\tException error code: " + error_code);
233
-          exceptionFile.WriteLine("\tException message: " + exception.message);
234
-          exceptionFile.Close();
235
-        }
236
-        throw exception;
237
-      }
238
-    }
239
-  }
240
-  // If we reached this point, we failed to open the file after 10 attempts.
241
-  // We need to error out.
242
-  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
243
-  WScript.Quit(1);
244
-}

+ 0
- 63
proj/GPIO.runs/impl_1/ISEWrap.sh View File

1
-#!/bin/sh
2
-
3
-#
4
-#  Vivado(TM)
5
-#  ISEWrap.sh: Vivado Runs Script for UNIX
6
-#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
7
-#
8
-
9
-HD_LOG=$1
10
-shift
11
-
12
-# CHECK for a STOP FILE
13
-if [ -f .stop.rst ]
14
-then
15
-echo ""                                        >> $HD_LOG
16
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
17
-echo ""                                        >> $HD_LOG
18
-exit 1
19
-fi
20
-
21
-ISE_STEP=$1
22
-shift
23
-
24
-# WRITE STEP HEADER to LOG
25
-echo ""                      >> $HD_LOG
26
-echo "*** Running $ISE_STEP" >> $HD_LOG
27
-echo "    with args $@"      >> $HD_LOG
28
-echo ""                      >> $HD_LOG
29
-
30
-# LAUNCH!
31
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
32
-
33
-# BEGIN file creation
34
-ISE_PID=$!
35
-if [ X != X$HOSTNAME ]
36
-then
37
-ISE_HOST=$HOSTNAME #bash
38
-else
39
-ISE_HOST=$HOST     #csh
40
-fi
41
-ISE_USER=$USER
42
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
43
-/bin/touch $ISE_BEGINFILE
44
-echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
45
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
46
-echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
47
-echo "    </Process>"                                                                              >> $ISE_BEGINFILE
48
-echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
49
-
50
-# WAIT for ISEStep to finish
51
-wait $ISE_PID
52
-
53
-# END/ERROR file creation
54
-RETVAL=$?
55
-if [ $RETVAL -eq 0 ]
56
-then
57
-    /bin/touch .$ISE_STEP.end.rst
58
-else
59
-    /bin/touch .$ISE_STEP.error.rst
60
-fi
61
-
62
-exit $RETVAL
63
-

+ 0
- 157
proj/GPIO.runs/impl_1/gen_run.xml View File

1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1618002924">
3
-  <File Type="PWROPT-DRC" Name="GPIO_demo_drc_pwropted.rpt"/>
4
-  <File Type="OPT-METHODOLOGY-DRC" Name="GPIO_demo_methodology_drc_opted.rpt"/>
5
-  <File Type="INIT-TIMING" Name="GPIO_demo_timing_summary_init.rpt"/>
6
-  <File Type="ROUTE-PWR-RPX" Name="GPIO_demo_power_routed.rpx"/>
7
-  <File Type="PA-TCL" Name="GPIO_demo.tcl"/>
8
-  <File Type="OPT-HWDEF" Name="GPIO_demo.hwdef"/>
9
-  <File Type="RDI-RDI" Name="GPIO_demo.vdi"/>
10
-  <File Type="OPT-DCP" Name="GPIO_demo_opt.dcp"/>
11
-  <File Type="OPT-DRC" Name="GPIO_demo_drc_opted.rpt"/>
12
-  <File Type="OPT-TIMING" Name="GPIO_demo_timing_summary_opted.rpt"/>
13
-  <File Type="PWROPT-DCP" Name="GPIO_demo_pwropt.dcp"/>
14
-  <File Type="PWROPT-TIMING" Name="GPIO_demo_timing_summary_pwropted.rpt"/>
15
-  <File Type="PLACE-DCP" Name="GPIO_demo_placed.dcp"/>
16
-  <File Type="PLACE-IO" Name="GPIO_demo_io_placed.rpt"/>
17
-  <File Type="PLACE-CLK" Name="GPIO_demo_clock_utilization_placed.rpt"/>
18
-  <File Type="PLACE-UTIL" Name="GPIO_demo_utilization_placed.rpt"/>
19
-  <File Type="PLACE-UTIL-PB" Name="GPIO_demo_utilization_placed.pb"/>
20
-  <File Type="PLACE-CTRL" Name="GPIO_demo_control_sets_placed.rpt"/>
21
-  <File Type="PLACE-SIMILARITY" Name="GPIO_demo_incremental_reuse_placed.rpt"/>
22
-  <File Type="PLACE-PRE-SIMILARITY" Name="GPIO_demo_incremental_reuse_pre_placed.rpt"/>
23
-  <File Type="PLACE-TIMING" Name="GPIO_demo_timing_summary_placed.rpt"/>
24
-  <File Type="POSTPLACE-PWROPT-DCP" Name="GPIO_demo_postplace_pwropt.dcp"/>
25
-  <File Type="POSTPLACE-PWROPT-TIMING" Name="GPIO_demo_timing_summary_postplace_pwropted.rpt"/>
26
-  <File Type="PHYSOPT-DCP" Name="GPIO_demo_physopt.dcp"/>
27
-  <File Type="PHYSOPT-DRC" Name="GPIO_demo_drc_physopted.rpt"/>
28
-  <File Type="PHYSOPT-TIMING" Name="GPIO_demo_timing_summary_physopted.rpt"/>
29
-  <File Type="ROUTE-ERROR-DCP" Name="GPIO_demo_routed_error.dcp"/>
30
-  <File Type="ROUTE-DCP" Name="GPIO_demo_routed.dcp"/>
31
-  <File Type="ROUTE-BLACKBOX-DCP" Name="GPIO_demo_routed_bb.dcp"/>
32
-  <File Type="ROUTE-DRC" Name="GPIO_demo_drc_routed.rpt"/>
33
-  <File Type="ROUTE-DRC-PB" Name="GPIO_demo_drc_routed.pb"/>
34
-  <File Type="BG-BIN" Name="GPIO_demo.bin"/>
35
-  <File Type="ROUTE-DRC-RPX" Name="GPIO_demo_drc_routed.rpx"/>
36
-  <File Type="BG-DRC" Name="GPIO_demo.drc"/>
37
-  <File Type="ROUTE-METHODOLOGY-DRC" Name="GPIO_demo_methodology_drc_routed.rpt"/>
38
-  <File Type="BITSTR-MSK" Name="GPIO_demo.msk"/>
39
-  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="GPIO_demo_methodology_drc_routed.rpx"/>
40
-  <File Type="BG-BGN" Name="GPIO_demo.bgn"/>
41
-  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="GPIO_demo_methodology_drc_routed.pb"/>
42
-  <File Type="ROUTE-PWR" Name="GPIO_demo_power_routed.rpt"/>
43
-  <File Type="ROUTE-PWR-SUM" Name="GPIO_demo_power_summary_routed.pb"/>
44
-  <File Type="ROUTE-STATUS" Name="GPIO_demo_route_status.rpt"/>
45
-  <File Type="ROUTE-STATUS-PB" Name="GPIO_demo_route_status.pb"/>
46
-  <File Type="ROUTE-TIMINGSUMMARY" Name="GPIO_demo_timing_summary_routed.rpt"/>
47
-  <File Type="ROUTE-TIMING-PB" Name="GPIO_demo_timing_summary_routed.pb"/>
48
-  <File Type="ROUTE-TIMING-RPX" Name="GPIO_demo_timing_summary_routed.rpx"/>
49
-  <File Type="ROUTE-SIMILARITY" Name="GPIO_demo_incremental_reuse_routed.rpt"/>
50
-  <File Type="ROUTE-CLK" Name="GPIO_demo_clock_utilization_routed.rpt"/>
51
-  <File Type="POSTROUTE-PHYSOPT-DCP" Name="GPIO_demo_postroute_physopt.dcp"/>
52
-  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="GPIO_demo_postroute_physopt_bb.dcp"/>
53
-  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="GPIO_demo_timing_summary_postroute_physopted.rpt"/>
54
-  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="GPIO_demo_timing_summary_postroute_physopted.pb"/>
55
-  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="GPIO_demo_timing_summary_postroute_physopted.rpx"/>
56
-  <File Type="BG-BIT" Name="GPIO_demo.bit"/>
57
-  <File Type="BITSTR-RBT" Name="GPIO_demo.rbt"/>
58
-  <File Type="BITSTR-NKY" Name="GPIO_demo.nky"/>
59
-  <File Type="BITSTR-BMM" Name="GPIO_demo_bd.bmm"/>
60
-  <File Type="BITSTR-MMI" Name="GPIO_demo.mmi"/>
61
-  <File Type="BITSTR-SYSDEF" Name="GPIO_demo.sysdef"/>
62
-  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
63
-  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
64
-    <Filter Type="Srcs"/>
65
-    <File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
66
-      <FileInfo>
67
-        <Attr Name="UsedIn" Val="synthesis"/>
68
-        <Attr Name="UsedIn" Val="simulation"/>
69
-      </FileInfo>
70
-    </File>
71
-    <File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
72
-      <FileInfo>
73
-        <Attr Name="UsedIn" Val="synthesis"/>
74
-        <Attr Name="UsedIn" Val="simulation"/>
75
-      </FileInfo>
76
-    </File>
77
-    <File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
78
-      <FileInfo>
79
-        <Attr Name="UsedIn" Val="synthesis"/>
80
-        <Attr Name="UsedIn" Val="simulation"/>
81
-      </FileInfo>
82
-    </File>
83
-    <File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
84
-      <FileInfo>
85
-        <Attr Name="UsedIn" Val="synthesis"/>
86
-        <Attr Name="UsedIn" Val="simulation"/>
87
-      </FileInfo>
88
-    </File>
89
-    <File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
90
-      <FileInfo>
91
-        <Attr Name="UsedIn" Val="synthesis"/>
92
-        <Attr Name="UsedIn" Val="simulation"/>
93
-      </FileInfo>
94
-    </File>
95
-    <File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
96
-      <FileInfo>
97
-        <Attr Name="UsedIn" Val="synthesis"/>
98
-        <Attr Name="UsedIn" Val="simulation"/>
99
-      </FileInfo>
100
-    </File>
101
-    <File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
102
-      <FileInfo>
103
-        <Attr Name="UsedIn" Val="synthesis"/>
104
-        <Attr Name="UsedIn" Val="simulation"/>
105
-      </FileInfo>
106
-    </File>
107
-    <File Path="$PPRDIR/../src/hdl/debouncer.vhd">
108
-      <FileInfo>
109
-        <Attr Name="UsedIn" Val="synthesis"/>
110
-        <Attr Name="UsedIn" Val="simulation"/>
111
-      </FileInfo>
112
-    </File>
113
-    <File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
114
-      <FileInfo>
115
-        <Attr Name="UsedIn" Val="synthesis"/>
116
-        <Attr Name="UsedIn" Val="simulation"/>
117
-      </FileInfo>
118
-    </File>
119
-    <Config>
120
-      <Option Name="DesignMode" Val="RTL"/>
121
-      <Option Name="TopModule" Val="GPIO_demo"/>
122
-      <Option Name="TopAutoSet" Val="TRUE"/>
123
-    </Config>
124
-  </FileSet>
125
-  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
126
-    <Filter Type="Constrs"/>
127
-    <File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
128
-      <FileInfo>
129
-        <Attr Name="UsedIn" Val="synthesis"/>
130
-        <Attr Name="UsedIn" Val="implementation"/>
131
-      </FileInfo>
132
-    </File>
133
-    <Config>
134
-      <Option Name="ConstrsType" Val="XDC"/>
135
-    </Config>
136
-  </FileSet>
137
-  <Strategy Version="1" Minor="2">
138
-    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015">
139
-      <Desc>Vivado Implementation Defaults</Desc>
140
-    </StratHandle>
141
-    <Step Id="init_design"/>
142
-    <Step Id="opt_design">
143
-      <Option Id="Directive">4</Option>
144
-    </Step>
145
-    <Step Id="power_opt_design"/>
146
-    <Step Id="place_design">
147
-      <Option Id="Directive">14</Option>
148
-    </Step>
149
-    <Step Id="post_place_power_opt_design"/>
150
-    <Step Id="phys_opt_design"/>
151
-    <Step Id="route_design">
152
-      <Option Id="Directive">5</Option>
153
-    </Step>
154
-    <Step Id="post_route_phys_opt_design"/>
155
-    <Step Id="write_bitstream"/>
156
-  </Strategy>
157
-</GenRun>

+ 0
- 9
proj/GPIO.runs/impl_1/htr.txt View File

1
-REM
2
-REM Vivado(TM)
3
-REM htr.txt: a Vivado-generated description of how-to-repeat the
4
-REM          the basic steps of a run.  Note that runme.bat/sh needs
5
-REM          to be invoked for Vivado to track run status.
6
-REM Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
7
-REM
8
-
9
-vivado -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace

BIN
proj/GPIO.runs/impl_1/init_design.pb View File


BIN
proj/GPIO.runs/impl_1/opt_design.pb View File


BIN
proj/GPIO.runs/impl_1/place_design.pb View File


+ 0
- 31
proj/GPIO.runs/impl_1/project.wdf View File

1
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
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23
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
24
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
25
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
26
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
27
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
28
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
29
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
30
-5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3031333866366637386234623465663361303338333762383461653364333333:506172656e742050412070726f6a656374204944:00
31
-eof:1785114370

BIN
proj/GPIO.runs/impl_1/route_design.pb View File


+ 0
- 40
proj/GPIO.runs/impl_1/rundef.js View File

1
-//
2
-// Vivado(TM)
3
-// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
4
-// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
5
-//
6
-
7
-var WshShell = new ActiveXObject( "WScript.Shell" );
8
-var ProcEnv = WshShell.Environment( "Process" );
9
-var PathVal = ProcEnv("PATH");
10
-if ( PathVal.length == 0 ) {
11
-  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;";
12
-} else {
13
-  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;" + PathVal;
14
-}
15
-
16
-ProcEnv("PATH") = PathVal;
17
-
18
-var RDScrFP = WScript.ScriptFullName;
19
-var RDScrN = WScript.ScriptName;
20
-var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
21
-var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
22
-eval( EAInclude(ISEJScriptLib) );
23
-
24
-
25
-// pre-commands:
26
-ISETouchFile( "write_bitstream", "begin" );
27
-ISEStep( "vivado",
28
-         "-log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace" );
29
-
30
-
31
-
32
-
33
-
34
-function EAInclude( EAInclFilename ) {
35
-  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
36
-  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
37
-  var EAIFContents = EAInclFile.ReadAll();
38
-  EAInclFile.Close();
39
-  return EAIFContents;
40
-}

+ 0
- 10
proj/GPIO.runs/impl_1/runme.bat View File

1
-@echo off
2
-
3
-rem  Vivado (TM)
4
-rem  runme.bat: a Vivado-generated Script
5
-rem  Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
6
-
7
-
8
-set HD_SDIR=%~dp0
9
-cd /d "%HD_SDIR%"
10
-cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

+ 0
- 473
proj/GPIO.runs/impl_1/runme.log View File

1
-
2
-*** Running vivado
3
-    with args -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
4
-
5
-
6
-****** Vivado v2016.4 (64-bit)
7
-  **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
8
-  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
9
-    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
10
-
11
-source GPIO_demo.tcl -notrace
12
-Design is defaulting to srcset: sources_1
13
-Design is defaulting to constrset: constrs_1
14
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
15
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
16
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
17
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
18
-INFO: [Project 1-570] Preparing netlist for logic optimization
19
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
20
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
21
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
22
-INFO: [Project 1-111] Unisim Transformation Summary:
23
-  A total of 2 instances were transformed.
24
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
25
-
26
-link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
27
-INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
28
-Command: opt_design -directive RuntimeOptimized
29
-INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
30
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
31
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
32
-Running DRC as a precondition to command opt_design
33
-
34
-Starting DRC Task
35
-INFO: [DRC 23-27] Running DRC with 2 threads
36
-INFO: [Project 1-461] DRC finished with 0 Errors
37
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
38
-
39
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
40
-
41
-Starting Logic Optimization Task
42
-Implement Debug Cores | Checksum: 11fc7498c
43
-INFO: [Timing 38-35] Done setting XDC timing constraints.
44
-INFO: [Timing 38-2] Deriving generated clocks
45
-
46
-Phase 1 Retarget
47
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
48
-INFO: [Opt 31-49] Retargeted 0 cell(s).
49
-Phase 1 Retarget | Checksum: 16f269fca
50
-
51
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
52
-
53
-Phase 2 Constant propagation
54
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
55
-INFO: [Opt 31-10] Eliminated 6 cells.
56
-Phase 2 Constant propagation | Checksum: 233a26f9e
57
-
58
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
59
-
60
-Phase 3 Sweep
61
-INFO: [Opt 31-12] Eliminated 363 unconnected nets.
62
-INFO: [Opt 31-11] Eliminated 2 unconnected cells.
63
-Phase 3 Sweep | Checksum: 1bb596469
64
-
65
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
66
-
67
-Phase 4 BUFG optimization
68
-INFO: [Opt 31-12] Eliminated 0 unconnected nets.
69
-INFO: [Opt 31-11] Eliminated 0 unconnected cells.
70
-Phase 4 BUFG optimization | Checksum: 1bb596469
71
-
72
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
73
-
74
-Starting Connectivity Check Task
75
-
76
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
77
-Ending Logic Optimization Task | Checksum: 1bb596469
78
-
79
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
80
-INFO: [Common 17-83] Releasing license: Implementation
81
-24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
82
-opt_design completed successfully
83
-opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
84
-Writing placer database...
85
-Writing XDEF routing.
86
-Writing XDEF routing logical nets.
87
-Writing XDEF routing special nets.
88
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
89
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
90
-INFO: [DRC 23-27] Running DRC with 2 threads
91
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
92
-INFO: [Chipscope 16-241] No debug cores found in the current design.
93
-Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
94
-or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
95
-Command: place_design -directive RuntimeOptimized
96
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
97
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
98
-INFO: [DRC 23-27] Running DRC with 2 threads
99
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
100
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
101
-Running DRC as a precondition to command place_design
102
-INFO: [DRC 23-27] Running DRC with 2 threads
103
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
104
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
105
-
106
-Starting Placer Task
107
-INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
108
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
109
-
110
-Phase 1 Placer Initialization
111
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
112
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
113
-
114
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
115
-INFO: [Timing 38-35] Done setting XDC timing constraints.
116
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
117
-
118
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
119
-
120
-Phase 1.2 Build Placer Netlist Model
121
-Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
122
-
123
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
124
-
125
-Phase 1.3 Constrain Clocks/Macros
126
-Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
127
-
128
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
129
-Phase 1 Placer Initialization | Checksum: f331096b
130
-
131
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
132
-
133
-Phase 2 Global Placement
134
-Phase 2 Global Placement | Checksum: 7e244a0f
135
-
136
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
137
-
138
-Phase 3 Detail Placement
139
-
140
-Phase 3.1 Commit Multi Column Macros
141
-Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
142
-
143
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
144
-
145
-Phase 3.2 Commit Most Macros & LUTRAMs
146
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
147
-
148
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
149
-
150
-Phase 3.3 Area Swap Optimization
151
-Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
152
-
153
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
154
-
155
-Phase 3.4 Pipeline Register Optimization
156
-Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
157
-
158
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
159
-
160
-Phase 3.5 Timing Path Optimizer
161
-Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
162
-
163
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
164
-
165
-Phase 3.6 Small Shape Detail Placement
166
-Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
167
-
168
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
169
-
170
-Phase 3.7 Re-assign LUT pins
171
-Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
172
-
173
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
174
-
175
-Phase 3.8 Pipeline Register Optimization
176
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
177
-
178
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
179
-Phase 3 Detail Placement | Checksum: 1c30709cd
180
-
181
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
182
-
183
-Phase 4 Post Placement Optimization and Clean-Up
184
-
185
-Phase 4.1 Post Commit Optimization
186
-INFO: [Timing 38-35] Done setting XDC timing constraints.
187
-
188
-Phase 4.1.1 Post Placement Optimization
189
-INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
190
-Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
191
-
192
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
193
-Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
194
-
195
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
196
-
197
-Phase 4.2 Post Placement Cleanup
198
-Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
199
-
200
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
201
-
202
-Phase 4.3 Placer Reporting
203
-Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
204
-
205
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
206
-
207
-Phase 4.4 Final Placement Cleanup
208
-Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
209
-
210
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
211
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
212
-
213
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
214
-Ending Placer Task | Checksum: dd20239e
215
-
216
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
217
-INFO: [Common 17-83] Releasing license: Implementation
218
-41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
219
-place_design completed successfully
220
-place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
221
-Writing placer database...
222
-Writing XDEF routing.
223
-Writing XDEF routing logical nets.
224
-Writing XDEF routing special nets.
225
-Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
226
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
227
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
228
-report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
229
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
230
-Command: route_design -directive RuntimeOptimized
231
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
232
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
233
-Running DRC as a precondition to command route_design
234
-INFO: [DRC 23-27] Running DRC with 2 threads
235
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
236
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
237
-
238
-
239
-Starting Routing Task
240
-INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
241
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
242
-Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
243
-
244
-Phase 1 Build RT Design
245
-Phase 1 Build RT Design | Checksum: be9a9a9a
246
-
247
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
248
-
249
-Phase 2 Router Initialization
250
-
251
-Phase 2.1 Create Timer
252
-Phase 2.1 Create Timer | Checksum: be9a9a9a
253
-
254
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
255
-
256
-Phase 2.2 Fix Topology Constraints
257
-Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
258
-
259
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
260
-
261
-Phase 2.3 Pre Route Cleanup
262
-Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
263
-
264
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
265
- Number of Nodes with overlaps = 0
266
-
267
-Phase 2.4 Update Timing
268
-Phase 2.4 Update Timing | Checksum: 111c71c3e
269
-
270
-Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
271
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
272
-
273
-Phase 2 Router Initialization | Checksum: 1ee683561
274
-
275
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
276
-
277
-Phase 3 Initial Routing
278
-Phase 3 Initial Routing | Checksum: 10e02a291
279
-
280
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
281
-
282
-Phase 4 Rip-up And Reroute
283
-
284
-Phase 4.1 Global Iteration 0
285
- Number of Nodes with overlaps = 107
286
- Number of Nodes with overlaps = 0
287
-
288
-Phase 4.1.1 Update Timing
289
-Phase 4.1.1 Update Timing | Checksum: da308246
290
-
291
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
292
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
293
-
294
-Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
295
-
296
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
297
-
298
-Phase 4.2 Global Iteration 1
299
- Number of Nodes with overlaps = 1
300
- Number of Nodes with overlaps = 0
301
-
302
-Phase 4.2.1 Update Timing
303
-Phase 4.2.1 Update Timing | Checksum: 1185cfc05
304
-
305
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
306
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
307
-
308
-Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
309
-
310
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
311
-Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
312
-
313
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
314
-
315
-Phase 5 Delay and Skew Optimization
316
-
317
-Phase 5.1 Delay CleanUp
318
-Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
319
-
320
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
321
-
322
-Phase 5.2 Clock Skew Optimization
323
-Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
324
-
325
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
326
-Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
327
-
328
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
329
-
330
-Phase 6 Post Hold Fix
331
-
332
-Phase 6.1 Hold Fix Iter
333
-
334
-Phase 6.1.1 Update Timing
335
-Phase 6.1.1 Update Timing | Checksum: 16251cbd9
336
-
337
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
338
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
339
-
340
-Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
341
-
342
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
343
-Phase 6 Post Hold Fix | Checksum: 12245b0d3
344
-
345
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
346
-
347
-Phase 7 Route finalize
348
-
349
-Router Utilization Summary
350
-  Global Vertical Routing Utilization    = 0.234075 %
351
-  Global Horizontal Routing Utilization  = 0.228267 %
352
-  Routable Net Status*
353
-  *Does not include unroutable nets such as driverless and loadless.
354
-  Run report_route_status for detailed report.
355
-  Number of Failed Nets               = 0
356
-  Number of Unrouted Nets             = 0
357
-  Number of Partially Routed Nets     = 0
358
-  Number of Node Overlaps             = 0
359
-
360
-Phase 7 Route finalize | Checksum: 1af3f3601
361
-
362
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
363
-
364
-Phase 8 Verifying routed nets
365
-
366
- Verification completed successfully
367
-Phase 8 Verifying routed nets | Checksum: 1af3f3601
368
-
369
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
370
-
371
-Phase 9 Depositing Routes
372
-Phase 9 Depositing Routes | Checksum: 15d59118d
373
-
374
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
375
-
376
-Phase 10 Post Router Timing
377
-INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
378
-
379
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
380
-Phase 10 Post Router Timing | Checksum: 15d59118d
381
-
382
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
383
-INFO: [Route 35-16] Router Completed Successfully
384
-
385
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
386
-
387
-Routing Is Done.
388
-INFO: [Common 17-83] Releasing license: Implementation
389
-56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
390
-route_design completed successfully
391
-route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
392
-Writing placer database...
393
-Writing XDEF routing.
394
-Writing XDEF routing logical nets.
395
-Writing XDEF routing special nets.
396
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
397
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
398
-INFO: [DRC 23-27] Running DRC with 2 threads
399
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
400
-INFO: [Timing 38-35] Done setting XDC timing constraints.
401
-INFO: [DRC 23-133] Running Methodology with 2 threads
402
-INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
403
-INFO: [Timing 38-35] Done setting XDC timing constraints.
404
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
405
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
406
-INFO: [Timing 38-35] Done setting XDC timing constraints.
407
-Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
408
-Running Vector-less Activity Propagation...
409
-
410
-Finished Running Vector-less Activity Propagation
411
-66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
412
-report_power completed successfully
413
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
414
-
415
-*** Running vivado
416
-    with args -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
417
-
418
-
419
-****** Vivado v2016.4 (64-bit)
420
-  **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
421
-  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
422
-    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
423
-
424
-source GPIO_demo.tcl -notrace
425
-Command: open_checkpoint GPIO_demo_routed.dcp
426
-
427
-Starting open_checkpoint Task
428
-
429
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
430
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
431
-INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
432
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
433
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
434
-INFO: [Project 1-570] Preparing netlist for logic optimization
435
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
436
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
437
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
438
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
439
-Reading XDEF placement.
440
-Reading placer database...
441
-Reading XDEF routing.
442
-Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
443
-Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
444
-Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
445
-INFO: [Project 1-111] Unisim Transformation Summary:
446
-  A total of 2 instances were transformed.
447
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
448
-
449
-INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
450
-open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
451
-Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
452
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
453
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
454
-Running DRC as a precondition to command write_bitstream
455
-INFO: [DRC 23-27] Running DRC with 2 threads
456
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
457
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
458
-Loading data files...
459
-Loading site data...
460
-Loading route data...
461
-Processing options...
462
-Creating bitmap...
463
-Creating bitstream...
464
-Bitstream compression saved 13383552 bits.
465
-Writing bitstream ./GPIO_demo.bit...
466
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
467
-INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
468
-INFO: [Common 17-83] Releasing license: Implementation
469
-14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
470
-write_bitstream completed successfully
471
-write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
472
-INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
473
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...

+ 0
- 47
proj/GPIO.runs/impl_1/runme.sh View File

1
-#!/bin/sh
2
-
3
-# 
4
-# Vivado(TM)
5
-# runme.sh: a Vivado-generated Runs Script for UNIX
6
-# Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
7
-# 
8
-
9
-echo "This script was generated under a different operating system."
10
-echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
11
-exit
12
-
13
-if [ -z "$PATH" ]; then
14
-  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin
15
-else
16
-  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin:$PATH
17
-fi
18
-export PATH
19
-
20
-if [ -z "$LD_LIBRARY_PATH" ]; then
21
-  LD_LIBRARY_PATH=
22
-else
23
-  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
24
-fi
25
-export LD_LIBRARY_PATH
26
-
27
-HD_PWD='C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1'
28
-cd "$HD_PWD"
29
-
30
-HD_LOG=runme.log
31
-/bin/touch $HD_LOG
32
-
33
-ISEStep="./ISEWrap.sh"
34
-EAStep()
35
-{
36
-     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
37
-     if [ $? -ne 0 ]
38
-     then
39
-         exit
40
-     fi
41
-}
42
-
43
-# pre-commands:
44
-/bin/touch .write_bitstream.begin.rst
45
-EAStep vivado -log GPIO_demo.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
46
-
47
-

+ 0
- 506
proj/GPIO.runs/impl_1/usage_statistics_webtalk.html View File

1
-<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
2
-<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
3
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
4
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
5
-<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
6
-  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>1756540</TD>
7
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Fri Apr 09 23:19:55 2021</TD>
8
-  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
9
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2016.4 (64-bit)</TD>
10
-  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>0138f6f78b4b4ef3a03837b84ae3d333</TD>
11
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
12
-  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
13
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>89e526329a235cb691995f8457477284</TD>
14
-  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
15
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
16
-  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
17
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>cpg236</TD>
18
-  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
19
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
20
-</TR> </TABLE><BR>
21
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
22
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
23
-<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz</TD>
24
-  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2592 MHz</TD>
25
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
26
-  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
27
-</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
28
-  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
29
-</TR> </TABLE><BR>
30
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
31
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
32
-<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
33
-   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
34
-<TR ALIGN='LEFT'>   <TD>runbitgen=1</TD>
35
-   <TD>runimplementation=1</TD>
36
-   <TD>runsynthesis=1</TD>
37
-</TR>  </TABLE>
38
-  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
39
-   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
40
-<TR ALIGN='LEFT'>   <TD>guimode=1</TD>
41
-</TR>  </TABLE>
42
-</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
43
-   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
44
-<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
45
-   <TD>core_container=false</TD>
46
-   <TD>currentimplrun=impl_1</TD>
47
-   <TD>currentsynthesisrun=synth_1</TD>
48
-</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
49
-   <TD>designmode=RTL</TD>
50
-   <TD>export_simulation_activehdl=0</TD>
51
-   <TD>export_simulation_ies=0</TD>
52
-</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=0</TD>
53
-   <TD>export_simulation_questa=0</TD>
54
-   <TD>export_simulation_riviera=0</TD>
55
-   <TD>export_simulation_vcs=0</TD>
56
-</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=0</TD>
57
-   <TD>implstrategy=Vivado Implementation Defaults</TD>
58
-   <TD>launch_simulation_activehdl=0</TD>
59
-   <TD>launch_simulation_ies=0</TD>
60
-</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
61
-   <TD>launch_simulation_questa=0</TD>
62
-   <TD>launch_simulation_riviera=0</TD>
63
-   <TD>launch_simulation_vcs=0</TD>
64
-</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
65
-   <TD>simulator_language=Mixed</TD>
66
-   <TD>srcsetcount=9</TD>
67
-   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
68
-</TR><TR ALIGN='LEFT'>   <TD>target_language=VHDL</TD>
69
-   <TD>target_simulator=XSim</TD>
70
-   <TD>totalimplruns=1</TD>
71
-   <TD>totalsynthesisruns=1</TD>
72
-</TR>  </TABLE>
73
-</TR> </TABLE><BR>
74
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
75
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
76
-   <TR><TD>
77
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
78
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
79
-<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
80
-    <TD>carry4=132</TD>
81
-    <TD>fdre=579</TD>
82
-    <TD>fdse=2</TD>
83
-</TR><TR ALIGN='LEFT'>    <TD>gnd=8</TD>
84
-    <TD>ibuf=24</TD>
85
-    <TD>lut1=368</TD>
86
-    <TD>lut2=207</TD>
87
-</TR><TR ALIGN='LEFT'>    <TD>lut3=91</TD>
88
-    <TD>lut4=138</TD>
89
-    <TD>lut5=73</TD>
90
-    <TD>lut6=157</TD>
91
-</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv=1</TD>
92
-    <TD>muxf7=3</TD>
93
-    <TD>obuf=43</TD>
94
-    <TD>obuft=2</TD>
95
-</TR><TR ALIGN='LEFT'>    <TD>vcc=8</TD>
96
-</TR>   </TABLE>
97
-   </TD></TR>
98
-   <TR><TD>
99
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
100
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
101
-<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
102
-    <TD>carry4=132</TD>
103
-    <TD>fdre=579</TD>
104
-    <TD>fdse=2</TD>
105
-</TR><TR ALIGN='LEFT'>    <TD>gnd=8</TD>
106
-    <TD>ibuf=22</TD>
107
-    <TD>iobuf=2</TD>
108
-    <TD>lut1=368</TD>
109
-</TR><TR ALIGN='LEFT'>    <TD>lut2=207</TD>
110
-    <TD>lut3=91</TD>
111
-    <TD>lut4=138</TD>
112
-    <TD>lut5=73</TD>
113
-</TR><TR ALIGN='LEFT'>    <TD>lut6=157</TD>
114
-    <TD>mmcme2_adv=1</TD>
115
-    <TD>muxf7=3</TD>
116
-    <TD>obuf=43</TD>
117
-</TR><TR ALIGN='LEFT'>    <TD>vcc=8</TD>
118
-</TR>   </TABLE>
119
-   </TD></TR>
120
-  </TABLE><BR>
121
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
122
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
123
-   <TR><TD>
124
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
125
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v5_1/1</B></TD></TR>
126
-<TR ALIGN='LEFT'>    <TD>clkin1_period=10.0</TD>
127
-    <TD>clkin2_period=10.0</TD>
128
-    <TD>clock_mgr_type=NA</TD>
129
-    <TD>component_name=clk_wiz_0</TD>
130
-</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
131
-    <TD>enable_axi=0</TD>
132
-    <TD>feedback_source=FDBK_AUTO</TD>
133
-    <TD>feedback_type=SINGLE</TD>
134
-</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
135
-    <TD>manual_override=false</TD>
136
-    <TD>num_out_clk=1</TD>
137
-    <TD>primitive=MMCM</TD>
138
-</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
139
-    <TD>use_dyn_reconfig=false</TD>
140
-    <TD>use_inclk_stopped=false</TD>
141
-    <TD>use_inclk_switchover=false</TD>
142
-</TR><TR ALIGN='LEFT'>    <TD>use_locked=false</TD>
143
-    <TD>use_max_i_jitter=false</TD>
144
-    <TD>use_min_o_jitter=false</TD>
145
-    <TD>use_phase_alignment=true</TD>
146
-</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
147
-    <TD>use_reset=false</TD>
148
-</TR>   </TABLE>
149
-   </TD></TR>
150
-  </TABLE><BR>
151
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
152
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
153
-   <TR><TD>
154
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
155
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
156
-<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
157
-    <TD>-checks=default::[not_specified]</TD>
158
-    <TD>-fail_on=default::[not_specified]</TD>
159
-    <TD>-force=default::[not_specified]</TD>
160
-</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
161
-    <TD>-messages=default::[not_specified]</TD>
162
-    <TD>-name=default::[not_specified]</TD>
163
-    <TD>-return_string=default::[not_specified]</TD>
164
-</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
165
-    <TD>-upgrade_cw=default::[not_specified]</TD>
166
-</TR>   </TABLE>
167
-   </TD></TR>
168
-  </TABLE><BR>
169
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
170
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
171
-   <TR><TD>
172
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
173
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
174
-<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
175
-    <TD>bufgctrl_fixed=0</TD>
176
-    <TD>bufgctrl_used=3</TD>
177
-    <TD>bufgctrl_util_percentage=9.38</TD>
178
-</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=72</TD>
179
-    <TD>bufhce_fixed=0</TD>
180
-    <TD>bufhce_used=0</TD>
181
-    <TD>bufhce_util_percentage=0.00</TD>
182
-</TR><TR ALIGN='LEFT'>    <TD>bufio_available=20</TD>
183
-    <TD>bufio_fixed=0</TD>
184
-    <TD>bufio_used=0</TD>
185
-    <TD>bufio_util_percentage=0.00</TD>
186
-</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=10</TD>
187
-    <TD>bufmrce_fixed=0</TD>
188
-    <TD>bufmrce_used=0</TD>
189
-    <TD>bufmrce_util_percentage=0.00</TD>
190
-</TR><TR ALIGN='LEFT'>    <TD>bufr_available=20</TD>
191
-    <TD>bufr_fixed=0</TD>
192
-    <TD>bufr_used=0</TD>
193
-    <TD>bufr_util_percentage=0.00</TD>
194
-</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=5</TD>
195
-    <TD>mmcme2_adv_fixed=0</TD>
196
-    <TD>mmcme2_adv_used=1</TD>
197
-    <TD>mmcme2_adv_util_percentage=20.00</TD>
198
-</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=5</TD>
199
-    <TD>plle2_adv_fixed=0</TD>
200
-    <TD>plle2_adv_used=0</TD>
201
-    <TD>plle2_adv_util_percentage=0.00</TD>
202
-</TR>   </TABLE>
203
-   </TD></TR>
204
-   <TR><TD>
205
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
206
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
207
-<TR ALIGN='LEFT'>    <TD>dsps_available=90</TD>
208
-    <TD>dsps_fixed=0</TD>
209
-    <TD>dsps_used=0</TD>
210
-    <TD>dsps_util_percentage=0.00</TD>
211
-</TR>   </TABLE>
212
-   </TD></TR>
213
-   <TR><TD>
214
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
215
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
216
-<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
217
-    <TD>diff_hstl_i=0</TD>
218
-    <TD>diff_hstl_i_18=0</TD>
219
-    <TD>diff_hstl_ii=0</TD>
220
-</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
221
-    <TD>diff_hsul_12=0</TD>
222
-    <TD>diff_mobile_ddr=0</TD>
223
-    <TD>diff_sstl135=0</TD>
224
-</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
225
-    <TD>diff_sstl15=0</TD>
226
-    <TD>diff_sstl15_r=0</TD>
227
-    <TD>diff_sstl18_i=0</TD>
228
-</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
229
-    <TD>hstl_i=0</TD>
230
-    <TD>hstl_i_18=0</TD>
231
-    <TD>hstl_ii=0</TD>
232
-</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
233
-    <TD>hsul_12=0</TD>
234
-    <TD>lvcmos12=0</TD>
235
-    <TD>lvcmos15=0</TD>
236
-</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
237
-    <TD>lvcmos25=0</TD>
238
-    <TD>lvcmos33=1</TD>
239
-    <TD>lvds_25=0</TD>
240
-</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
241
-    <TD>mini_lvds_25=0</TD>
242
-    <TD>mobile_ddr=0</TD>
243
-    <TD>pci33_3=0</TD>
244
-</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
245
-    <TD>rsds_25=0</TD>
246
-    <TD>sstl135=0</TD>
247
-    <TD>sstl135_r=0</TD>
248
-</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
249
-    <TD>sstl15_r=0</TD>
250
-    <TD>sstl18_i=0</TD>
251
-    <TD>sstl18_ii=0</TD>
252
-</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
253
-</TR>   </TABLE>
254
-   </TD></TR>
255
-   <TR><TD>
256
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
257
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
258
-<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=50</TD>
259
-    <TD>block_ram_tile_fixed=0</TD>
260
-    <TD>block_ram_tile_used=0</TD>
261
-    <TD>block_ram_tile_util_percentage=0.00</TD>
262
-</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=100</TD>
263
-    <TD>ramb18_fixed=0</TD>
264
-    <TD>ramb18_used=0</TD>
265
-    <TD>ramb18_util_percentage=0.00</TD>
266
-</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=50</TD>
267
-    <TD>ramb36_fifo_fixed=0</TD>
268
-    <TD>ramb36_fifo_used=0</TD>
269
-    <TD>ramb36_fifo_util_percentage=0.00</TD>
270
-</TR>   </TABLE>
271
-   </TD></TR>
272
-   <TR><TD>
273
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
274
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
275
-<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
276
-    <TD>bufg_used=3</TD>
277
-    <TD>carry4_functional_category=CarryLogic</TD>
278
-    <TD>carry4_used=132</TD>
279
-</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
280
-    <TD>fdre_used=576</TD>
281
-    <TD>fdse_functional_category=Flop &amp; Latch</TD>
282
-    <TD>fdse_used=2</TD>
283
-</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
284
-    <TD>ibuf_used=24</TD>
285
-    <TD>lut1_functional_category=LUT</TD>
286
-    <TD>lut1_used=30</TD>
287
-</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
288
-    <TD>lut2_used=207</TD>
289
-    <TD>lut3_functional_category=LUT</TD>
290
-    <TD>lut3_used=93</TD>
291
-</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
292
-    <TD>lut4_used=136</TD>
293
-    <TD>lut5_functional_category=LUT</TD>
294
-    <TD>lut5_used=72</TD>
295
-</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
296
-    <TD>lut6_used=157</TD>
297
-    <TD>mmcme2_adv_functional_category=Clock</TD>
298
-    <TD>mmcme2_adv_used=1</TD>
299
-</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
300
-    <TD>muxf7_used=3</TD>
301
-    <TD>obuf_functional_category=IO</TD>
302
-    <TD>obuf_used=43</TD>
303
-</TR><TR ALIGN='LEFT'>    <TD>obuft_functional_category=IO</TD>
304
-    <TD>obuft_used=2</TD>
305
-</TR>   </TABLE>
306
-   </TD></TR>
307
-   <TR><TD>
308
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
309
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
310
-<TR ALIGN='LEFT'>    <TD>f7_muxes_available=16300</TD>
311
-    <TD>f7_muxes_fixed=0</TD>
312
-    <TD>f7_muxes_used=3</TD>
313
-    <TD>f7_muxes_util_percentage=0.02</TD>
314
-</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=8150</TD>
315
-    <TD>f8_muxes_fixed=0</TD>
316
-    <TD>f8_muxes_used=0</TD>
317
-    <TD>f8_muxes_util_percentage=0.00</TD>
318
-</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=20800</TD>
319
-    <TD>lut_as_logic_fixed=0</TD>
320
-    <TD>lut_as_logic_used=564</TD>
321
-    <TD>lut_as_logic_util_percentage=2.71</TD>
322
-</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=9600</TD>
323
-    <TD>lut_as_memory_fixed=0</TD>
324
-    <TD>lut_as_memory_used=0</TD>
325
-    <TD>lut_as_memory_util_percentage=0.00</TD>
326
-</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=41600</TD>
327
-    <TD>register_as_flip_flop_fixed=0</TD>
328
-    <TD>register_as_flip_flop_used=578</TD>
329
-    <TD>register_as_flip_flop_util_percentage=1.39</TD>
330
-</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=41600</TD>
331
-    <TD>register_as_latch_fixed=0</TD>
332
-    <TD>register_as_latch_used=0</TD>
333
-    <TD>register_as_latch_util_percentage=0.00</TD>
334
-</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=20800</TD>
335
-    <TD>slice_luts_fixed=0</TD>
336
-    <TD>slice_luts_used=564</TD>
337
-    <TD>slice_luts_util_percentage=2.71</TD>
338
-</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=41600</TD>
339
-    <TD>slice_registers_fixed=0</TD>
340
-    <TD>slice_registers_used=578</TD>
341
-    <TD>slice_registers_util_percentage=1.39</TD>
342
-</TR><TR ALIGN='LEFT'>    <TD>fully_used_lut_ff_pairs_fixed=1.39</TD>
343
-    <TD>fully_used_lut_ff_pairs_used=54</TD>
344
-    <TD>lut_as_distributed_ram_fixed=0</TD>
345
-    <TD>lut_as_distributed_ram_used=0</TD>
346
-</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=20800</TD>
347
-    <TD>lut_as_logic_fixed=0</TD>
348
-    <TD>lut_as_logic_used=564</TD>
349
-    <TD>lut_as_logic_util_percentage=2.71</TD>
350
-</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=9600</TD>
351
-    <TD>lut_as_memory_fixed=0</TD>
352
-    <TD>lut_as_memory_used=0</TD>
353
-    <TD>lut_as_memory_util_percentage=0.00</TD>
354
-</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
355
-    <TD>lut_as_shift_register_used=0</TD>
356
-    <TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=0</TD>
357
-    <TD>lut_ff_pairs_with_one_unused_flip_flop_used=111</TD>
358
-</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=111</TD>
359
-    <TD>lut_ff_pairs_with_one_unused_lut_output_used=110</TD>
360
-    <TD>lut_flip_flop_pairs_available=20800</TD>
361
-    <TD>lut_flip_flop_pairs_fixed=0</TD>
362
-</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_used=171</TD>
363
-    <TD>lut_flip_flop_pairs_util_percentage=0.82</TD>
364
-    <TD>slice_available=8150</TD>
365
-    <TD>slice_fixed=0</TD>
366
-</TR><TR ALIGN='LEFT'>    <TD>slice_used=282</TD>
367
-    <TD>slice_util_percentage=3.46</TD>
368
-    <TD>slicel_fixed=0</TD>
369
-    <TD>slicel_used=182</TD>
370
-</TR><TR ALIGN='LEFT'>    <TD>slicem_fixed=0</TD>
371
-    <TD>slicem_used=100</TD>
372
-    <TD>unique_control_sets_used=36</TD>
373
-    <TD>using_o5_and_o6_fixed=36</TD>
374
-</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=131</TD>
375
-    <TD>using_o5_output_only_fixed=131</TD>
376
-    <TD>using_o5_output_only_used=0</TD>
377
-    <TD>using_o6_output_only_fixed=0</TD>
378
-</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=433</TD>
379
-</TR>   </TABLE>
380
-   </TD></TR>
381
-   <TR><TD>
382
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
383
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
384
-<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
385
-    <TD>bscane2_fixed=0</TD>
386
-    <TD>bscane2_used=0</TD>
387
-    <TD>bscane2_util_percentage=0.00</TD>
388
-</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
389
-    <TD>capturee2_fixed=0</TD>
390
-    <TD>capturee2_used=0</TD>
391
-    <TD>capturee2_util_percentage=0.00</TD>
392
-</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
393
-    <TD>dna_port_fixed=0</TD>
394
-    <TD>dna_port_used=0</TD>
395
-    <TD>dna_port_util_percentage=0.00</TD>
396
-</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
397
-    <TD>efuse_usr_fixed=0</TD>
398
-    <TD>efuse_usr_used=0</TD>
399
-    <TD>efuse_usr_util_percentage=0.00</TD>
400
-</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
401
-    <TD>frame_ecce2_fixed=0</TD>
402
-    <TD>frame_ecce2_used=0</TD>
403
-    <TD>frame_ecce2_util_percentage=0.00</TD>
404
-</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
405
-    <TD>icape2_fixed=0</TD>
406
-    <TD>icape2_used=0</TD>
407
-    <TD>icape2_util_percentage=0.00</TD>
408
-</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
409
-    <TD>pcie_2_1_fixed=0</TD>
410
-    <TD>pcie_2_1_used=0</TD>
411
-    <TD>pcie_2_1_util_percentage=0.00</TD>
412
-</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
413
-    <TD>startupe2_fixed=0</TD>
414
-    <TD>startupe2_used=0</TD>
415
-    <TD>startupe2_util_percentage=0.00</TD>
416
-</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
417
-    <TD>xadc_fixed=0</TD>
418
-    <TD>xadc_used=0</TD>
419
-    <TD>xadc_util_percentage=0.00</TD>
420
-</TR>   </TABLE>
421
-   </TD></TR>
422
-  </TABLE><BR>
423
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
424
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
425
-   <TR><TD>
426
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
427
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
428
-<TR ALIGN='LEFT'>    <TD>actual_expansions=695075</TD>
429
-    <TD>bogomips=0</TD>
430
-    <TD>bram18=0</TD>
431
-    <TD>bram36=0</TD>
432
-</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
433
-    <TD>bufr=0</TD>
434
-    <TD>congestion_level=0</TD>
435
-    <TD>ctrls=36</TD>
436
-</TR><TR ALIGN='LEFT'>    <TD>dsp=0</TD>
437
-    <TD>effort=2</TD>
438
-    <TD>estimated_expansions=723384</TD>
439
-    <TD>ff=578</TD>
440
-</TR><TR ALIGN='LEFT'>    <TD>global_clocks=3</TD>
441
-    <TD>high_fanout_nets=0</TD>
442
-    <TD>iob=67</TD>
443
-    <TD>lut=609</TD>
444
-</TR><TR ALIGN='LEFT'>    <TD>movable_instances=1499</TD>
445
-    <TD>nets=1904</TD>
446
-    <TD>pins=8775</TD>
447
-    <TD>pll=0</TD>
448
-</TR><TR ALIGN='LEFT'>    <TD>router_runtime=0.000000</TD>
449
-    <TD>router_timing_driven=1</TD>
450
-    <TD>threads=2</TD>
451
-    <TD>timing_constraints_exist=1</TD>
452
-</TR>   </TABLE>
453
-   </TD></TR>
454
-  </TABLE><BR>
455
- <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
456
-  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
457
-   <TR><TD>
458
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
459
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
460
-<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
461
-    <TD>-bufg=default::12</TD>
462
-    <TD>-cascade_dsp=default::auto</TD>
463
-    <TD>-constrset=default::[not_specified]</TD>
464
-</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
465
-    <TD>-directive=RuntimeOptimized</TD>
466
-    <TD>-fanout_limit=default::10000</TD>
467
-    <TD>-flatten_hierarchy=none</TD>
468
-</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=off</TD>
469
-    <TD>-gated_clock_conversion=default::off</TD>
470
-    <TD>-generic=default::[not_specified]</TD>
471
-    <TD>-include_dirs=default::[not_specified]</TD>
472
-</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
473
-    <TD>-max_bram=default::-1</TD>
474
-    <TD>-max_bram_cascade_height=default::-1</TD>
475
-    <TD>-max_dsp=default::-1</TD>
476
-</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
477
-    <TD>-max_uram_cascade_height=default::-1</TD>
478
-    <TD>-mode=default::default</TD>
479
-    <TD>-name=default::[not_specified]</TD>
480
-</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
481
-    <TD>-no_srlextract=default::[not_specified]</TD>
482
-    <TD>-no_timing_driven=default::[not_specified]</TD>
483
-    <TD>-part=xc7a35tcpg236-1</TD>
484
-</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
485
-    <TD>-retiming=default::[not_specified]</TD>
486
-    <TD>-rtl=default::[not_specified]</TD>
487
-    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
488
-</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
489
-    <TD>-seu_protect=default::none</TD>
490
-    <TD>-shreg_min_size=default::3</TD>
491
-    <TD>-top=GPIO_demo</TD>
492
-</TR><TR ALIGN='LEFT'>    <TD>-verilog_define=default::[not_specified]</TD>
493
-</TR>   </TABLE>
494
-   </TD></TR>
495
-   <TR><TD>
496
-   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
497
-    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
498
-<TR ALIGN='LEFT'>    <TD>elapsed=00:00:34s</TD>
499
-    <TD>hls_ip=0</TD>
500
-    <TD>memory_gain=424.176MB</TD>
501
-    <TD>memory_peak=692.656MB</TD>
502
-</TR>   </TABLE>
503
-   </TD></TR>
504
-  </TABLE><BR>
505
-</BODY>
506
-</HTML>

+ 0
- 453
proj/GPIO.runs/impl_1/usage_statistics_webtalk.xml View File

1
-<?xml version="1.0" encoding="UTF-8" ?>
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-<webTalkData  fileName='usage_statistics_webtalk.xml'  majorVersion='1' minorVersion='0' timeStamp='Fri Apr 09 23:19:55 2021'>
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-<section name="__ROOT__" level="0" order="1" description="">
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- <section name="software_version_and_target_device" level="1" order="1" description="">
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-  <keyValuePair key="beta" value="FALSE" description="" />
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-  <keyValuePair key="build_version" value="1756540" description="" />
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-  <keyValuePair key="date_generated" value="Fri Apr 09 23:19:55 2021" description="" />
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-  <keyValuePair key="os_platform" value="WIN64" description="" />
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-  <keyValuePair key="product_version" value="Vivado v2016.4 (64-bit)" description="" />
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-  <keyValuePair key="project_id" value="0138f6f78b4b4ef3a03837b84ae3d333" description="" />
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-  <keyValuePair key="project_iteration" value="1" description="" />
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-  <keyValuePair key="random_id" value="89e526329a235cb691995f8457477284" description="" />
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-  <keyValuePair key="registration_id" value="89e526329a235cb691995f8457477284" description="" />
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-  <keyValuePair key="route_design" value="TRUE" description="" />
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-  <keyValuePair key="target_device" value="xc7a35t" description="" />
16
-  <keyValuePair key="target_family" value="artix7" description="" />
17
-  <keyValuePair key="target_package" value="cpg236" description="" />
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-  <keyValuePair key="target_speed" value="-1" description="" />
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-  <keyValuePair key="tool_flow" value="Vivado" description="" />
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- </section>
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- <section name="user_environment" level="1" order="2" description="">
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-  <keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz" description="" />
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-  <keyValuePair key="cpu_speed" value="2592 MHz" description="" />
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-  <keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
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-  <keyValuePair key="os_release" value="major release  (build 9200)" description="" />
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-  <keyValuePair key="system_ram" value="8.000 GB" description="" />
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-  <keyValuePair key="total_processors" value="1" description="" />
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- </section>
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- <section name="ip_statistics" level="1" order="3" description="">
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-  <section name="clk_wiz_v5_1/1" level="2" order="1" description="">
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-   <keyValuePair key="clkin1_period" value="10.0" description="" />
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-   <keyValuePair key="clkin2_period" value="10.0" description="" />
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-   <keyValuePair key="clock_mgr_type" value="NA" description="" />
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-   <keyValuePair key="component_name" value="clk_wiz_0" description="" />
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-   <keyValuePair key="core_container" value="NA" description="" />
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-   <keyValuePair key="enable_axi" value="0" description="" />
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-   <keyValuePair key="feedback_source" value="FDBK_AUTO" description="" />
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-   <keyValuePair key="feedback_type" value="SINGLE" description="" />
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-   <keyValuePair key="iptotal" value="1" description="" />
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-   <keyValuePair key="manual_override" value="false" description="" />
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-   <keyValuePair key="num_out_clk" value="1" description="" />
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-   <keyValuePair key="primitive" value="MMCM" description="" />
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-   <keyValuePair key="use_dyn_phase_shift" value="false" description="" />
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-   <keyValuePair key="use_dyn_reconfig" value="false" description="" />
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-   <keyValuePair key="use_inclk_stopped" value="false" description="" />
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-   <keyValuePair key="use_inclk_switchover" value="false" description="" />
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-   <keyValuePair key="use_locked" value="false" description="" />
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-   <keyValuePair key="use_max_i_jitter" value="false" description="" />
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-   <keyValuePair key="use_min_o_jitter" value="false" description="" />
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-   <keyValuePair key="use_phase_alignment" value="true" description="" />
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-   <keyValuePair key="use_power_down" value="false" description="" />
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-   <keyValuePair key="use_reset" value="false" description="" />
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-  </section>
54
- </section>
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- <section name="report_drc" level="1" order="4" description="">
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-  <section name="command_line_options" level="2" order="1" description="">
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-   <keyValuePair key="-append" value="default::[not_specified]" description="" />
58
-   <keyValuePair key="-checks" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-force" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-format" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-messages" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-name" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
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-   <keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
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-  </section>
68
- </section>
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- <section name="report_utilization" level="1" order="5" description="">
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-  <section name="clocking" level="2" order="1" description="">
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-   <keyValuePair key="bufgctrl_available" value="32" description="" />
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-   <keyValuePair key="bufgctrl_fixed" value="0" description="" />
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-   <keyValuePair key="bufgctrl_used" value="3" description="" />
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-   <keyValuePair key="bufgctrl_util_percentage" value="9.38" description="" />
75
-   <keyValuePair key="bufhce_available" value="72" description="" />
76
-   <keyValuePair key="bufhce_fixed" value="0" description="" />
77
-   <keyValuePair key="bufhce_used" value="0" description="" />
78
-   <keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
79
-   <keyValuePair key="bufio_available" value="20" description="" />
80
-   <keyValuePair key="bufio_fixed" value="0" description="" />
81
-   <keyValuePair key="bufio_used" value="0" description="" />
82
-   <keyValuePair key="bufio_util_percentage" value="0.00" description="" />
83
-   <keyValuePair key="bufmrce_available" value="10" description="" />
84
-   <keyValuePair key="bufmrce_fixed" value="0" description="" />
85
-   <keyValuePair key="bufmrce_used" value="0" description="" />
86
-   <keyValuePair key="bufmrce_util_percentage" value="0.00" description="" />
87
-   <keyValuePair key="bufr_available" value="20" description="" />
88
-   <keyValuePair key="bufr_fixed" value="0" description="" />
89
-   <keyValuePair key="bufr_used" value="0" description="" />
90
-   <keyValuePair key="bufr_util_percentage" value="0.00" description="" />
91
-   <keyValuePair key="mmcme2_adv_available" value="5" description="" />
92
-   <keyValuePair key="mmcme2_adv_fixed" value="0" description="" />
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-   <keyValuePair key="mmcme2_adv_used" value="1" description="" />
94
-   <keyValuePair key="mmcme2_adv_util_percentage" value="20.00" description="" />
95
-   <keyValuePair key="plle2_adv_available" value="5" description="" />
96
-   <keyValuePair key="plle2_adv_fixed" value="0" description="" />
97
-   <keyValuePair key="plle2_adv_used" value="0" description="" />
98
-   <keyValuePair key="plle2_adv_util_percentage" value="0.00" description="" />
99
-  </section>
100
-  <section name="dsp" level="2" order="2" description="">
101
-   <keyValuePair key="dsps_available" value="90" description="" />
102
-   <keyValuePair key="dsps_fixed" value="0" description="" />
103
-   <keyValuePair key="dsps_used" value="0" description="" />
104
-   <keyValuePair key="dsps_util_percentage" value="0.00" description="" />
105
-  </section>
106
-  <section name="io_standard" level="2" order="3" description="">
107
-   <keyValuePair key="blvds_25" value="0" description="" />
108
-   <keyValuePair key="diff_hstl_i" value="0" description="" />
109
-   <keyValuePair key="diff_hstl_i_18" value="0" description="" />
110
-   <keyValuePair key="diff_hstl_ii" value="0" description="" />
111
-   <keyValuePair key="diff_hstl_ii_18" value="0" description="" />
112
-   <keyValuePair key="diff_hsul_12" value="0" description="" />
113
-   <keyValuePair key="diff_mobile_ddr" value="0" description="" />
114
-   <keyValuePair key="diff_sstl135" value="0" description="" />
115
-   <keyValuePair key="diff_sstl135_r" value="0" description="" />
116
-   <keyValuePair key="diff_sstl15" value="0" description="" />
117
-   <keyValuePair key="diff_sstl15_r" value="0" description="" />
118
-   <keyValuePair key="diff_sstl18_i" value="0" description="" />
119
-   <keyValuePair key="diff_sstl18_ii" value="0" description="" />
120
-   <keyValuePair key="hstl_i" value="0" description="" />
121
-   <keyValuePair key="hstl_i_18" value="0" description="" />
122
-   <keyValuePair key="hstl_ii" value="0" description="" />
123
-   <keyValuePair key="hstl_ii_18" value="0" description="" />
124
-   <keyValuePair key="hsul_12" value="0" description="" />
125
-   <keyValuePair key="lvcmos12" value="0" description="" />
126
-   <keyValuePair key="lvcmos15" value="0" description="" />
127
-   <keyValuePair key="lvcmos18" value="0" description="" />
128
-   <keyValuePair key="lvcmos25" value="0" description="" />
129
-   <keyValuePair key="lvcmos33" value="1" description="" />
130
-   <keyValuePair key="lvds_25" value="0" description="" />
131
-   <keyValuePair key="lvttl" value="0" description="" />
132
-   <keyValuePair key="mini_lvds_25" value="0" description="" />
133
-   <keyValuePair key="mobile_ddr" value="0" description="" />
134
-   <keyValuePair key="pci33_3" value="0" description="" />
135
-   <keyValuePair key="ppds_25" value="0" description="" />
136
-   <keyValuePair key="rsds_25" value="0" description="" />
137
-   <keyValuePair key="sstl135" value="0" description="" />
138
-   <keyValuePair key="sstl135_r" value="0" description="" />
139
-   <keyValuePair key="sstl15" value="0" description="" />
140
-   <keyValuePair key="sstl15_r" value="0" description="" />
141
-   <keyValuePair key="sstl18_i" value="0" description="" />
142
-   <keyValuePair key="sstl18_ii" value="0" description="" />
143
-   <keyValuePair key="tmds_33" value="0" description="" />
144
-  </section>
145
-  <section name="memory" level="2" order="4" description="">
146
-   <keyValuePair key="block_ram_tile_available" value="50" description="" />
147
-   <keyValuePair key="block_ram_tile_fixed" value="0" description="" />
148
-   <keyValuePair key="block_ram_tile_used" value="0" description="" />
149
-   <keyValuePair key="block_ram_tile_util_percentage" value="0.00" description="" />
150
-   <keyValuePair key="ramb18_available" value="100" description="" />
151
-   <keyValuePair key="ramb18_fixed" value="0" description="" />
152
-   <keyValuePair key="ramb18_used" value="0" description="" />
153
-   <keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
154
-   <keyValuePair key="ramb36_fifo_available" value="50" description="" />
155
-   <keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
156
-   <keyValuePair key="ramb36_fifo_used" value="0" description="" />
157
-   <keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
158
-  </section>
159
-  <section name="primitives" level="2" order="5" description="">
160
-   <keyValuePair key="bufg_functional_category" value="Clock" description="" />
161
-   <keyValuePair key="bufg_used" value="3" description="" />
162
-   <keyValuePair key="carry4_functional_category" value="CarryLogic" description="" />
163
-   <keyValuePair key="carry4_used" value="132" description="" />
164
-   <keyValuePair key="fdre_functional_category" value="Flop &amp; Latch" description="" />
165
-   <keyValuePair key="fdre_used" value="576" description="" />
166
-   <keyValuePair key="fdse_functional_category" value="Flop &amp; Latch" description="" />
167
-   <keyValuePair key="fdse_used" value="2" description="" />
168
-   <keyValuePair key="ibuf_functional_category" value="IO" description="" />
169
-   <keyValuePair key="ibuf_used" value="24" description="" />
170
-   <keyValuePair key="lut1_functional_category" value="LUT" description="" />
171
-   <keyValuePair key="lut1_used" value="30" description="" />
172
-   <keyValuePair key="lut2_functional_category" value="LUT" description="" />
173
-   <keyValuePair key="lut2_used" value="207" description="" />
174
-   <keyValuePair key="lut3_functional_category" value="LUT" description="" />
175
-   <keyValuePair key="lut3_used" value="93" description="" />
176
-   <keyValuePair key="lut4_functional_category" value="LUT" description="" />
177
-   <keyValuePair key="lut4_used" value="136" description="" />
178
-   <keyValuePair key="lut5_functional_category" value="LUT" description="" />
179
-   <keyValuePair key="lut5_used" value="72" description="" />
180
-   <keyValuePair key="lut6_functional_category" value="LUT" description="" />
181
-   <keyValuePair key="lut6_used" value="157" description="" />
182
-   <keyValuePair key="mmcme2_adv_functional_category" value="Clock" description="" />
183
-   <keyValuePair key="mmcme2_adv_used" value="1" description="" />
184
-   <keyValuePair key="muxf7_functional_category" value="MuxFx" description="" />
185
-   <keyValuePair key="muxf7_used" value="3" description="" />
186
-   <keyValuePair key="obuf_functional_category" value="IO" description="" />
187
-   <keyValuePair key="obuf_used" value="43" description="" />
188
-   <keyValuePair key="obuft_functional_category" value="IO" description="" />
189
-   <keyValuePair key="obuft_used" value="2" description="" />
190
-  </section>
191
-  <section name="slice_logic" level="2" order="6" description="">
192
-   <keyValuePair key="f7_muxes_available" value="16300" description="" />
193
-   <keyValuePair key="f7_muxes_fixed" value="0" description="" />
194
-   <keyValuePair key="f7_muxes_used" value="3" description="" />
195
-   <keyValuePair key="f7_muxes_util_percentage" value="0.02" description="" />
196
-   <keyValuePair key="f8_muxes_available" value="8150" description="" />
197
-   <keyValuePair key="f8_muxes_fixed" value="0" description="" />
198
-   <keyValuePair key="f8_muxes_used" value="0" description="" />
199
-   <keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
200
-   <keyValuePair key="fully_used_lut_ff_pairs_fixed" value="1.39" description="" />
201
-   <keyValuePair key="fully_used_lut_ff_pairs_used" value="54" description="" />
202
-   <keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
203
-   <keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
204
-   <keyValuePair key="lut_as_logic_available" value="20800" description="" />
205
-   <keyValuePair key="lut_as_logic_available" value="20800" description="" />
206
-   <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
207
-   <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
208
-   <keyValuePair key="lut_as_logic_used" value="564" description="" />
209
-   <keyValuePair key="lut_as_logic_used" value="564" description="" />
210
-   <keyValuePair key="lut_as_logic_util_percentage" value="2.71" description="" />
211
-   <keyValuePair key="lut_as_logic_util_percentage" value="2.71" description="" />
212
-   <keyValuePair key="lut_as_memory_available" value="9600" description="" />
213
-   <keyValuePair key="lut_as_memory_available" value="9600" description="" />
214
-   <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
215
-   <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
216
-   <keyValuePair key="lut_as_memory_used" value="0" description="" />
217
-   <keyValuePair key="lut_as_memory_used" value="0" description="" />
218
-   <keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
219
-   <keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
220
-   <keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
221
-   <keyValuePair key="lut_as_shift_register_used" value="0" description="" />
222
-   <keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_fixed" value="0" description="" />
223
-   <keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_used" value="111" description="" />
224
-   <keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_fixed" value="111" description="" />
225
-   <keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_used" value="110" description="" />
226
-   <keyValuePair key="lut_flip_flop_pairs_available" value="20800" description="" />
227
-   <keyValuePair key="lut_flip_flop_pairs_fixed" value="0" description="" />
228
-   <keyValuePair key="lut_flip_flop_pairs_used" value="171" description="" />
229
-   <keyValuePair key="lut_flip_flop_pairs_util_percentage" value="0.82" description="" />
230
-   <keyValuePair key="register_as_flip_flop_available" value="41600" description="" />
231
-   <keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
232
-   <keyValuePair key="register_as_flip_flop_used" value="578" description="" />
233
-   <keyValuePair key="register_as_flip_flop_util_percentage" value="1.39" description="" />
234
-   <keyValuePair key="register_as_latch_available" value="41600" description="" />
235
-   <keyValuePair key="register_as_latch_fixed" value="0" description="" />
236
-   <keyValuePair key="register_as_latch_used" value="0" description="" />
237
-   <keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
238
-   <keyValuePair key="slice_available" value="8150" description="" />
239
-   <keyValuePair key="slice_fixed" value="0" description="" />
240
-   <keyValuePair key="slice_luts_available" value="20800" description="" />
241
-   <keyValuePair key="slice_luts_fixed" value="0" description="" />
242
-   <keyValuePair key="slice_luts_used" value="564" description="" />
243
-   <keyValuePair key="slice_luts_util_percentage" value="2.71" description="" />
244
-   <keyValuePair key="slice_registers_available" value="41600" description="" />
245
-   <keyValuePair key="slice_registers_fixed" value="0" description="" />
246
-   <keyValuePair key="slice_registers_used" value="578" description="" />
247
-   <keyValuePair key="slice_registers_util_percentage" value="1.39" description="" />
248
-   <keyValuePair key="slice_used" value="282" description="" />
249
-   <keyValuePair key="slice_util_percentage" value="3.46" description="" />
250
-   <keyValuePair key="slicel_fixed" value="0" description="" />
251
-   <keyValuePair key="slicel_used" value="182" description="" />
252
-   <keyValuePair key="slicem_fixed" value="0" description="" />
253
-   <keyValuePair key="slicem_used" value="100" description="" />
254
-   <keyValuePair key="unique_control_sets_used" value="36" description="" />
255
-   <keyValuePair key="using_o5_and_o6_fixed" value="36" description="" />
256
-   <keyValuePair key="using_o5_and_o6_used" value="131" description="" />
257
-   <keyValuePair key="using_o5_output_only_fixed" value="131" description="" />
258
-   <keyValuePair key="using_o5_output_only_used" value="0" description="" />
259
-   <keyValuePair key="using_o6_output_only_fixed" value="0" description="" />
260
-   <keyValuePair key="using_o6_output_only_used" value="433" description="" />
261
-  </section>
262
-  <section name="specific_feature" level="2" order="7" description="">
263
-   <keyValuePair key="bscane2_available" value="4" description="" />
264
-   <keyValuePair key="bscane2_fixed" value="0" description="" />
265
-   <keyValuePair key="bscane2_used" value="0" description="" />
266
-   <keyValuePair key="bscane2_util_percentage" value="0.00" description="" />
267
-   <keyValuePair key="capturee2_available" value="1" description="" />
268
-   <keyValuePair key="capturee2_fixed" value="0" description="" />
269
-   <keyValuePair key="capturee2_used" value="0" description="" />
270
-   <keyValuePair key="capturee2_util_percentage" value="0.00" description="" />
271
-   <keyValuePair key="dna_port_available" value="1" description="" />
272
-   <keyValuePair key="dna_port_fixed" value="0" description="" />
273
-   <keyValuePair key="dna_port_used" value="0" description="" />
274
-   <keyValuePair key="dna_port_util_percentage" value="0.00" description="" />
275
-   <keyValuePair key="efuse_usr_available" value="1" description="" />
276
-   <keyValuePair key="efuse_usr_fixed" value="0" description="" />
277
-   <keyValuePair key="efuse_usr_used" value="0" description="" />
278
-   <keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
279
-   <keyValuePair key="frame_ecce2_available" value="1" description="" />
280
-   <keyValuePair key="frame_ecce2_fixed" value="0" description="" />
281
-   <keyValuePair key="frame_ecce2_used" value="0" description="" />
282
-   <keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
283
-   <keyValuePair key="icape2_available" value="2" description="" />
284
-   <keyValuePair key="icape2_fixed" value="0" description="" />
285
-   <keyValuePair key="icape2_used" value="0" description="" />
286
-   <keyValuePair key="icape2_util_percentage" value="0.00" description="" />
287
-   <keyValuePair key="pcie_2_1_available" value="1" description="" />
288
-   <keyValuePair key="pcie_2_1_fixed" value="0" description="" />
289
-   <keyValuePair key="pcie_2_1_used" value="0" description="" />
290
-   <keyValuePair key="pcie_2_1_util_percentage" value="0.00" description="" />
291
-   <keyValuePair key="startupe2_available" value="1" description="" />
292
-   <keyValuePair key="startupe2_fixed" value="0" description="" />
293
-   <keyValuePair key="startupe2_used" value="0" description="" />
294
-   <keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
295
-   <keyValuePair key="xadc_available" value="1" description="" />
296
-   <keyValuePair key="xadc_fixed" value="0" description="" />
297
-   <keyValuePair key="xadc_used" value="0" description="" />
298
-   <keyValuePair key="xadc_util_percentage" value="0.00" description="" />
299
-  </section>
300
- </section>
301
- <section name="router" level="1" order="6" description="">
302
-  <section name="usage" level="2" order="1" description="">
303
-   <keyValuePair key="actual_expansions" value="695075" description="" />
304
-   <keyValuePair key="bogomips" value="0" description="" />
305
-   <keyValuePair key="bram18" value="0" description="" />
306
-   <keyValuePair key="bram36" value="0" description="" />
307
-   <keyValuePair key="bufg" value="0" description="" />
308
-   <keyValuePair key="bufr" value="0" description="" />
309
-   <keyValuePair key="congestion_level" value="0" description="" />
310
-   <keyValuePair key="ctrls" value="36" description="" />
311
-   <keyValuePair key="dsp" value="0" description="" />
312
-   <keyValuePair key="effort" value="2" description="" />
313
-   <keyValuePair key="estimated_expansions" value="723384" description="" />
314
-   <keyValuePair key="ff" value="578" description="" />
315
-   <keyValuePair key="global_clocks" value="3" description="" />
316
-   <keyValuePair key="high_fanout_nets" value="0" description="" />
317
-   <keyValuePair key="iob" value="67" description="" />
318
-   <keyValuePair key="lut" value="609" description="" />
319
-   <keyValuePair key="movable_instances" value="1499" description="" />
320
-   <keyValuePair key="nets" value="1904" description="" />
321
-   <keyValuePair key="pins" value="8775" description="" />
322
-   <keyValuePair key="pll" value="0" description="" />
323
-   <keyValuePair key="router_runtime" value="0.000000" description="" />
324
-   <keyValuePair key="router_timing_driven" value="1" description="" />
325
-   <keyValuePair key="threads" value="2" description="" />
326
-   <keyValuePair key="timing_constraints_exist" value="1" description="" />
327
-  </section>
328
- </section>
329
- <section name="synthesis" level="1" order="7" description="">
330
-  <section name="command_line_options" level="2" order="1" description="">
331
-   <keyValuePair key="-assert" value="default::[not_specified]" description="" />
332
-   <keyValuePair key="-bufg" value="default::12" description="" />
333
-   <keyValuePair key="-cascade_dsp" value="default::auto" description="" />
334
-   <keyValuePair key="-constrset" value="default::[not_specified]" description="" />
335
-   <keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
336
-   <keyValuePair key="-directive" value="RuntimeOptimized" description="" />
337
-   <keyValuePair key="-fanout_limit" value="default::10000" description="" />
338
-   <keyValuePair key="-flatten_hierarchy" value="none" description="" />
339
-   <keyValuePair key="-fsm_extraction" value="off" description="" />
340
-   <keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
341
-   <keyValuePair key="-generic" value="default::[not_specified]" description="" />
342
-   <keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
343
-   <keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
344
-   <keyValuePair key="-max_bram" value="default::-1" description="" />
345
-   <keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
346
-   <keyValuePair key="-max_dsp" value="default::-1" description="" />
347
-   <keyValuePair key="-max_uram" value="default::-1" description="" />
348
-   <keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
349
-   <keyValuePair key="-mode" value="default::default" description="" />
350
-   <keyValuePair key="-name" value="default::[not_specified]" description="" />
351
-   <keyValuePair key="-no_lc" value="default::[not_specified]" description="" />
352
-   <keyValuePair key="-no_srlextract" value="default::[not_specified]" description="" />
353
-   <keyValuePair key="-no_timing_driven" value="default::[not_specified]" description="" />
354
-   <keyValuePair key="-part" value="xc7a35tcpg236-1" description="" />
355
-   <keyValuePair key="-resource_sharing" value="default::auto" description="" />
356
-   <keyValuePair key="-retiming" value="default::[not_specified]" description="" />
357
-   <keyValuePair key="-rtl" value="default::[not_specified]" description="" />
358
-   <keyValuePair key="-rtl_skip_constraints" value="default::[not_specified]" description="" />
359
-   <keyValuePair key="-rtl_skip_ip" value="default::[not_specified]" description="" />
360
-   <keyValuePair key="-seu_protect" value="default::none" description="" />
361
-   <keyValuePair key="-shreg_min_size" value="default::3" description="" />
362
-   <keyValuePair key="-top" value="GPIO_demo" description="" />
363
-   <keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
364
-  </section>
365
-  <section name="usage" level="2" order="2" description="">
366
-   <keyValuePair key="elapsed" value="00:00:34s" description="" />
367
-   <keyValuePair key="hls_ip" value="0" description="" />
368
-   <keyValuePair key="memory_gain" value="424.176MB" description="" />
369
-   <keyValuePair key="memory_peak" value="692.656MB" description="" />
370
-  </section>
371
- </section>
372
- <section name="unisim_transformation" level="1" order="8" description="">
373
-  <section name="post_unisim_transformation" level="2" order="1" description="">
374
-   <keyValuePair key="bufg" value="3" description="" />
375
-   <keyValuePair key="carry4" value="132" description="" />
376
-   <keyValuePair key="fdre" value="579" description="" />
377
-   <keyValuePair key="fdse" value="2" description="" />
378
-   <keyValuePair key="gnd" value="8" description="" />
379
-   <keyValuePair key="ibuf" value="24" description="" />
380
-   <keyValuePair key="lut1" value="368" description="" />
381
-   <keyValuePair key="lut2" value="207" description="" />
382
-   <keyValuePair key="lut3" value="91" description="" />
383
-   <keyValuePair key="lut4" value="138" description="" />
384
-   <keyValuePair key="lut5" value="73" description="" />
385
-   <keyValuePair key="lut6" value="157" description="" />
386
-   <keyValuePair key="mmcme2_adv" value="1" description="" />
387
-   <keyValuePair key="muxf7" value="3" description="" />
388
-   <keyValuePair key="obuf" value="43" description="" />
389
-   <keyValuePair key="obuft" value="2" description="" />
390
-   <keyValuePair key="vcc" value="8" description="" />
391
-  </section>
392
-  <section name="pre_unisim_transformation" level="2" order="2" description="">
393
-   <keyValuePair key="bufg" value="3" description="" />
394
-   <keyValuePair key="carry4" value="132" description="" />
395
-   <keyValuePair key="fdre" value="579" description="" />
396
-   <keyValuePair key="fdse" value="2" description="" />
397
-   <keyValuePair key="gnd" value="8" description="" />
398
-   <keyValuePair key="ibuf" value="22" description="" />
399
-   <keyValuePair key="iobuf" value="2" description="" />
400
-   <keyValuePair key="lut1" value="368" description="" />
401
-   <keyValuePair key="lut2" value="207" description="" />
402
-   <keyValuePair key="lut3" value="91" description="" />
403
-   <keyValuePair key="lut4" value="138" description="" />
404
-   <keyValuePair key="lut5" value="73" description="" />
405
-   <keyValuePair key="lut6" value="157" description="" />
406
-   <keyValuePair key="mmcme2_adv" value="1" description="" />
407
-   <keyValuePair key="muxf7" value="3" description="" />
408
-   <keyValuePair key="obuf" value="43" description="" />
409
-   <keyValuePair key="vcc" value="8" description="" />
410
-  </section>
411
- </section>
412
- <section name="vivado_usage" level="1" order="9" description="">
413
-  <section name="java_command_handlers" level="2" order="1" description="">
414
-   <keyValuePair key="runbitgen" value="1" description="" />
415
-   <keyValuePair key="runimplementation" value="1" description="" />
416
-   <keyValuePair key="runsynthesis" value="1" description="" />
417
-  </section>
418
-  <section name="other_data" level="2" order="2" description="">
419
-   <keyValuePair key="guimode" value="1" description="" />
420
-  </section>
421
-  <section name="project_data" level="2" order="3" description="">
422
-   <keyValuePair key="constraintsetcount" value="1" description="" />
423
-   <keyValuePair key="core_container" value="false" description="" />
424
-   <keyValuePair key="currentimplrun" value="impl_1" description="" />
425
-   <keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
426
-   <keyValuePair key="default_library" value="xil_defaultlib" description="" />
427
-   <keyValuePair key="designmode" value="RTL" description="" />
428
-   <keyValuePair key="export_simulation_activehdl" value="0" description="" />
429
-   <keyValuePair key="export_simulation_ies" value="0" description="" />
430
-   <keyValuePair key="export_simulation_modelsim" value="0" description="" />
431
-   <keyValuePair key="export_simulation_questa" value="0" description="" />
432
-   <keyValuePair key="export_simulation_riviera" value="0" description="" />
433
-   <keyValuePair key="export_simulation_vcs" value="0" description="" />
434
-   <keyValuePair key="export_simulation_xsim" value="0" description="" />
435
-   <keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
436
-   <keyValuePair key="launch_simulation_activehdl" value="0" description="" />
437
-   <keyValuePair key="launch_simulation_ies" value="0" description="" />
438
-   <keyValuePair key="launch_simulation_modelsim" value="0" description="" />
439
-   <keyValuePair key="launch_simulation_questa" value="0" description="" />
440
-   <keyValuePair key="launch_simulation_riviera" value="0" description="" />
441
-   <keyValuePair key="launch_simulation_vcs" value="0" description="" />
442
-   <keyValuePair key="launch_simulation_xsim" value="0" description="" />
443
-   <keyValuePair key="simulator_language" value="Mixed" description="" />
444
-   <keyValuePair key="srcsetcount" value="9" description="" />
445
-   <keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
446
-   <keyValuePair key="target_language" value="VHDL" description="" />
447
-   <keyValuePair key="target_simulator" value="XSim" description="" />
448
-   <keyValuePair key="totalimplruns" value="1" description="" />
449
-   <keyValuePair key="totalsynthesisruns" value="1" description="" />
450
-  </section>
451
- </section>
452
-</section>
453
-</webTalkData>

+ 0
- 12
proj/GPIO.runs/impl_1/vivado.jou View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:19:20 2021
6
-# Process ID: 1988
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace

BIN
proj/GPIO.runs/impl_1/vivado.pb View File


+ 0
- 12
proj/GPIO.runs/impl_1/vivado_960.backup.jou View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:15:32 2021
6
-# Process ID: 960
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace

BIN
proj/GPIO.runs/impl_1/write_bitstream.pb View File


+ 0
- 0
proj/GPIO.runs/synth_1/.Vivado_Synthesis.queue.rst View File


+ 0
- 135
proj/GPIO.runs/synth_1/.Xil/GPIO_demo_propImpl.xdc View File

1
-set_property SRC_FILE_INFO {cfile:C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc rfile:../../../../src/constraints/Basys3_Master.xdc id:1} [current_design]
2
-set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
3
-set_property PACKAGE_PIN W5 [get_ports CLK]
4
-set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
5
-set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
6
-set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
7
-set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
8
-set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
9
-set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
10
-set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
11
-set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
12
-set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
13
-set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
14
-set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
15
-set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
16
-set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
17
-set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
18
-set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
19
-set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
20
-set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
21
-set_property PACKAGE_PIN V2 [get_ports {SW[8]}]
22
-set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
23
-set_property PACKAGE_PIN T3 [get_ports {SW[9]}]
24
-set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
25
-set_property PACKAGE_PIN T2 [get_ports {SW[10]}]
26
-set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
27
-set_property PACKAGE_PIN R3 [get_ports {SW[11]}]
28
-set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
29
-set_property PACKAGE_PIN W2 [get_ports {SW[12]}]
30
-set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
31
-set_property PACKAGE_PIN U1 [get_ports {SW[13]}]
32
-set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
33
-set_property PACKAGE_PIN T1 [get_ports {SW[14]}]
34
-set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
35
-set_property PACKAGE_PIN R2 [get_ports {SW[15]}]
36
-set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
37
-set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
38
-set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
39
-set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
40
-set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
41
-set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
42
-set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
43
-set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
44
-set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design]
45
-set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
46
-set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
47
-set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
48
-set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design]
49
-set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
50
-set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design]
51
-set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
52
-set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design]
53
-set_property PACKAGE_PIN V13 [get_ports {LED[8]}]
54
-set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
55
-set_property PACKAGE_PIN V3 [get_ports {LED[9]}]
56
-set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design]
57
-set_property PACKAGE_PIN W3 [get_ports {LED[10]}]
58
-set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]
59
-set_property PACKAGE_PIN U3 [get_ports {LED[11]}]
60
-set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design]
61
-set_property PACKAGE_PIN P3 [get_ports {LED[12]}]
62
-set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design]
63
-set_property PACKAGE_PIN N3 [get_ports {LED[13]}]
64
-set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design]
65
-set_property PACKAGE_PIN P1 [get_ports {LED[14]}]
66
-set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design]
67
-set_property PACKAGE_PIN L1 [get_ports {LED[15]}]
68
-set_property src_info {type:XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design]
69
-set_property PACKAGE_PIN W7 [get_ports {SSEG_CA[0]}]
70
-set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design]
71
-set_property PACKAGE_PIN W6 [get_ports {SSEG_CA[1]}]
72
-set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design]
73
-set_property PACKAGE_PIN U8 [get_ports {SSEG_CA[2]}]
74
-set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design]
75
-set_property PACKAGE_PIN V8 [get_ports {SSEG_CA[3]}]
76
-set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design]
77
-set_property PACKAGE_PIN U5 [get_ports {SSEG_CA[4]}]
78
-set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design]
79
-set_property PACKAGE_PIN V5 [get_ports {SSEG_CA[5]}]
80
-set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design]
81
-set_property PACKAGE_PIN U7 [get_ports {SSEG_CA[6]}]
82
-set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design]
83
-set_property PACKAGE_PIN V7 [get_ports {SSEG_CA[7]}]
84
-set_property src_info {type:XDC file:1 line:110 export:INPUT save:INPUT read:READ} [current_design]
85
-set_property PACKAGE_PIN U2 [get_ports {SSEG_AN[0]}]
86
-set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design]
87
-set_property PACKAGE_PIN U4 [get_ports {SSEG_AN[1]}]
88
-set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design]
89
-set_property PACKAGE_PIN V4 [get_ports {SSEG_AN[2]}]
90
-set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design]
91
-set_property PACKAGE_PIN W4 [get_ports {SSEG_AN[3]}]
92
-set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design]
93
-set_property PACKAGE_PIN U18 [get_ports {BTN[4]}]
94
-set_property src_info {type:XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design]
95
-set_property PACKAGE_PIN T18 [get_ports {BTN[0]}]
96
-set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design]
97
-set_property PACKAGE_PIN W19 [get_ports {BTN[1]}]
98
-set_property src_info {type:XDC file:1 line:134 export:INPUT save:INPUT read:READ} [current_design]
99
-set_property PACKAGE_PIN T17 [get_ports {BTN[2]}]
100
-set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design]
101
-set_property PACKAGE_PIN U17 [get_ports {BTN[3]}]
102
-set_property src_info {type:XDC file:1 line:255 export:INPUT save:INPUT read:READ} [current_design]
103
-set_property PACKAGE_PIN G19 [get_ports {VGA_RED[0]}]
104
-set_property src_info {type:XDC file:1 line:258 export:INPUT save:INPUT read:READ} [current_design]
105
-set_property PACKAGE_PIN H19 [get_ports {VGA_RED[1]}]
106
-set_property src_info {type:XDC file:1 line:261 export:INPUT save:INPUT read:READ} [current_design]
107
-set_property PACKAGE_PIN J19 [get_ports {VGA_RED[2]}]
108
-set_property src_info {type:XDC file:1 line:264 export:INPUT save:INPUT read:READ} [current_design]
109
-set_property PACKAGE_PIN N19 [get_ports {VGA_RED[3]}]
110
-set_property src_info {type:XDC file:1 line:267 export:INPUT save:INPUT read:READ} [current_design]
111
-set_property PACKAGE_PIN N18 [get_ports {VGA_BLUE[0]}]
112
-set_property src_info {type:XDC file:1 line:270 export:INPUT save:INPUT read:READ} [current_design]
113
-set_property PACKAGE_PIN L18 [get_ports {VGA_BLUE[1]}]
114
-set_property src_info {type:XDC file:1 line:273 export:INPUT save:INPUT read:READ} [current_design]
115
-set_property PACKAGE_PIN K18 [get_ports {VGA_BLUE[2]}]
116
-set_property src_info {type:XDC file:1 line:276 export:INPUT save:INPUT read:READ} [current_design]
117
-set_property PACKAGE_PIN J18 [get_ports {VGA_BLUE[3]}]
118
-set_property src_info {type:XDC file:1 line:279 export:INPUT save:INPUT read:READ} [current_design]
119
-set_property PACKAGE_PIN J17 [get_ports {VGA_GREEN[0]}]
120
-set_property src_info {type:XDC file:1 line:282 export:INPUT save:INPUT read:READ} [current_design]
121
-set_property PACKAGE_PIN H17 [get_ports {VGA_GREEN[1]}]
122
-set_property src_info {type:XDC file:1 line:285 export:INPUT save:INPUT read:READ} [current_design]
123
-set_property PACKAGE_PIN G17 [get_ports {VGA_GREEN[2]}]
124
-set_property src_info {type:XDC file:1 line:288 export:INPUT save:INPUT read:READ} [current_design]
125
-set_property PACKAGE_PIN D17 [get_ports {VGA_GREEN[3]}]
126
-set_property src_info {type:XDC file:1 line:291 export:INPUT save:INPUT read:READ} [current_design]
127
-set_property PACKAGE_PIN P19 [get_ports VGA_HS]
128
-set_property src_info {type:XDC file:1 line:294 export:INPUT save:INPUT read:READ} [current_design]
129
-set_property PACKAGE_PIN R19 [get_ports VGA_VS]
130
-set_property src_info {type:XDC file:1 line:303 export:INPUT save:INPUT read:READ} [current_design]
131
-set_property PACKAGE_PIN A18 [get_ports UART_TXD]
132
-set_property src_info {type:XDC file:1 line:310 export:INPUT save:INPUT read:READ} [current_design]
133
-set_property PACKAGE_PIN C17 [get_ports PS2_CLK]
134
-set_property src_info {type:XDC file:1 line:314 export:INPUT save:INPUT read:READ} [current_design]
135
-set_property PACKAGE_PIN B17 [get_ports PS2_DATA]

+ 0
- 5
proj/GPIO.runs/synth_1/.vivado.begin.rst View File

1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="7440">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/synth_1/.vivado.end.rst View File


BIN
proj/GPIO.runs/synth_1/GPIO_demo.dcp View File


+ 0
- 43
proj/GPIO.runs/synth_1/GPIO_demo.tcl View File

1
-# 
2
-# Synthesis run script generated by Vivado
3
-# 
4
-
5
-set_msg_config -id {HDL 9-1061} -limit 100000
6
-set_msg_config -id {HDL 9-1654} -limit 100000
7
-create_project -in_memory -part xc7a35tcpg236-1
8
-
9
-set_param project.singleFileAddWarning.threshold 0
10
-set_param project.compositeFile.enableAutoGeneration 0
11
-set_param synth.vivado.isSynthRun true
12
-set_property webtalk.parent_dir C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.cache/wt [current_project]
13
-set_property parent.project_path C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.xpr [current_project]
14
-set_property default_lib xil_defaultlib [current_project]
15
-set_property target_language VHDL [current_project]
16
-set_property board_part digilentinc.com:basys3:part0:1.1 [current_project]
17
-set_property ip_repo_paths c:/Users/Hp/Documents/Compteur8BitsBasys3/repo [current_project]
18
-set_property ip_output_repo c:/Users/Hp/Documents/Compteur8BitsBasys3/repo/cache [current_project]
19
-set_property ip_cache_permissions {read write} [current_project]
20
-read_vhdl -library xil_defaultlib {
21
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd
22
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd
23
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd
24
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd
25
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd
26
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd
27
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd
28
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd
29
-  C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd
30
-}
31
-foreach dcp [get_files -quiet -all *.dcp] {
32
-  set_property used_in_implementation false $dcp
33
-}
34
-read_xdc C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc
35
-set_property used_in_implementation false [get_files C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
36
-
37
-
38
-synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy none -directive RuntimeOptimized -fsm_extraction off
39
-
40
-
41
-write_checkpoint -force -noxdef GPIO_demo.dcp
42
-
43
-catch { report_utilization -file GPIO_demo_utilization_synth.rpt -pb GPIO_demo_utilization_synth.pb }

+ 0
- 803
proj/GPIO.runs/synth_1/GPIO_demo.vds View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:10:44 2021
6
-# Process ID: 9840
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1
8
-# Command line: vivado.exe -log GPIO_demo.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.vds
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace
13
-Command: synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy none -directive RuntimeOptimized -fsm_extraction off
14
-Starting synth_design
15
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
16
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
17
-INFO: Launching helper process for spawning children vivado processes
18
-INFO: Helper process launched with PID 3172 
19
----------------------------------------------------------------------------------
20
-Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 350.121 ; gain = 140.289
21
----------------------------------------------------------------------------------
22
-INFO: [Synth 8-638] synthesizing module 'GPIO_demo' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
23
-	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
24
-	Parameter PORT_WIDTH bound to: 5 - type: integer 
25
-INFO: [Synth 8-3491] module 'debouncer' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:42' bound to instance 'Inst_btn_debounce' of component 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:320]
26
-INFO: [Synth 8-638] synthesizing module 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
27
-	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
28
-	Parameter PORT_WIDTH bound to: 5 - type: integer 
29
-INFO: [Synth 8-256] done synthesizing module 'debouncer' (1#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
30
-INFO: [Synth 8-3491] module 'UART_TX_CTRL' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:42' bound to instance 'Inst_UART_TX_CTRL' of component 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:450]
31
-INFO: [Synth 8-638] synthesizing module 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
32
-INFO: [Synth 8-256] done synthesizing module 'UART_TX_CTRL' (2#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
33
-INFO: [Synth 8-3491] module 'vga_ctrl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:38' bound to instance 'Inst_vga_ctrl' of component 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:465]
34
-INFO: [Synth 8-638] synthesizing module 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
35
-INFO: [Synth 8-3491] module 'clk_wiz_0' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:74' bound to instance 'clk_wiz_0_inst' of component 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:197]
36
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
37
-INFO: [Synth 8-3491] module 'clk_wiz_0_clk_wiz' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:74' bound to instance 'U0' of component 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:98]
38
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
39
-	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
40
-	Parameter CLKFBOUT_MULT_F bound to: 10.125000 - type: float 
41
-	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
42
-	Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 
43
-	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
44
-	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
45
-	Parameter CLKOUT0_DIVIDE_F bound to: 9.375000 - type: float 
46
-	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
47
-	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
48
-	Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 
49
-	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
50
-	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
51
-	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
52
-	Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 
53
-	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
54
-	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
55
-	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
56
-	Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 
57
-	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
58
-	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
59
-	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
60
-	Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 
61
-	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
62
-	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
63
-	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
64
-	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
65
-	Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 
66
-	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
67
-	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
68
-	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
69
-	Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 
70
-	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
71
-	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
72
-	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
73
-	Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 
74
-	Parameter COMPENSATION bound to: ZHOLD - type: string 
75
-	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
76
-	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
77
-	Parameter IS_PSEN_INVERTED bound to: 1'b0 
78
-	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
79
-	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
80
-	Parameter IS_RST_INVERTED bound to: 1'b0 
81
-	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
82
-	Parameter REF_JITTER2 bound to: 0.000000 - type: float 
83
-	Parameter SS_EN bound to: FALSE - type: string 
84
-	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
85
-	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
86
-	Parameter STARTUP_WAIT bound to: 0 - type: bool 
87
-INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:125]
88
-INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:187]
89
-INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:194]
90
-INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (3#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
91
-INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (4#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
92
-	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
93
-	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
94
-	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
95
-INFO: [Synth 8-3491] module 'MouseCtl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:179' bound to instance 'Inst_MouseCtl' of component 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:207]
96
-INFO: [Synth 8-638] synthesizing module 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
97
-	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
98
-	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
99
-	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
100
-INFO: [Synth 8-3491] module 'Ps2Interface' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:152' bound to instance 'Inst_Ps2Interface' of component 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:370]
101
-INFO: [Synth 8-638] synthesizing module 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
102
-INFO: [Synth 8-256] done synthesizing module 'Ps2Interface' (5#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
103
-INFO: [Synth 8-256] done synthesizing module 'MouseCtl' (6#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
104
-INFO: [Synth 8-3491] module 'MouseDisplay' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:99' bound to instance 'Inst_MouseDisplay' of component 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:334]
105
-INFO: [Synth 8-638] synthesizing module 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
106
-WARNING: [Synth 8-614] signal 'ypos' is read in the process but is not in the sensitivity list [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:197]
107
-INFO: [Synth 8-256] done synthesizing module 'MouseDisplay' (7#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
108
-INFO: [Synth 8-256] done synthesizing module 'vga_ctrl' (8#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
109
-INFO: [Synth 8-256] done synthesizing module 'GPIO_demo' (9#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
110
----------------------------------------------------------------------------------
111
-Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 391.957 ; gain = 182.125
112
----------------------------------------------------------------------------------
113
-
114
-Report Check Netlist: 
115
-+------+------------------+-------+---------+-------+------------------+
116
-|      |Item              |Errors |Warnings |Status |Description       |
117
-+------+------------------+-------+---------+-------+------------------+
118
-|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
119
-+------+------------------+-------+---------+-------+------------------+
120
----------------------------------------------------------------------------------
121
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 391.957 ; gain = 182.125
122
----------------------------------------------------------------------------------
123
-INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
124
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
125
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
126
-INFO: [Project 1-570] Preparing netlist for logic optimization
127
-
128
-Processing XDC Constraints
129
-Initializing timing engine
130
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
131
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
132
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/GPIO_demo_propImpl.xdc].
133
-Resolution: To avoid this warning, move constraints listed in [.Xil/GPIO_demo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
134
-INFO: [Timing 38-2] Deriving generated clocks
135
-Completed Processing XDC Constraints
136
-
137
-INFO: [Project 1-111] Unisim Transformation Summary:
138
-No Unisim elements were transformed.
139
-
140
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 692.656 ; gain = 0.000
141
----------------------------------------------------------------------------------
142
-Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
143
----------------------------------------------------------------------------------
144
----------------------------------------------------------------------------------
145
-Start Loading Part and Timing Information
146
----------------------------------------------------------------------------------
147
-Loading part: xc7a35tcpg236-1
148
----------------------------------------------------------------------------------
149
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
150
----------------------------------------------------------------------------------
151
----------------------------------------------------------------------------------
152
-Start Applying 'set_property' XDC Constraints
153
----------------------------------------------------------------------------------
154
----------------------------------------------------------------------------------
155
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
156
----------------------------------------------------------------------------------
157
-INFO: [Synth 8-5544] ROM "READY" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
158
-INFO: [Synth 8-5545] ROM "txState" won't be mapped to RAM because address size (31) is larger than maximum supported(25)
159
-INFO: [Synth 8-5544] ROM "bitIndex" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
160
-INFO: [Synth 8-5546] ROM "busy" won't be mapped to RAM because it is too sparse
161
-INFO: [Synth 8-5546] ROM "delay_100us_counter_enable" won't be mapped to RAM because it is too sparse
162
-INFO: [Synth 8-5546] ROM "delay_20us_counter_enable" won't be mapped to RAM because it is too sparse
163
-INFO: [Synth 8-5546] ROM "delay_63clk_counter_enable" won't be mapped to RAM because it is too sparse
164
-INFO: [Synth 8-5546] ROM "reset_bit_count" won't be mapped to RAM because it is too sparse
165
-INFO: [Synth 8-5545] ROM "periodic_check_tick" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
166
-INFO: [Synth 8-5546] ROM "timeout" won't be mapped to RAM because it is too sparse
167
-INFO: [Synth 8-4471] merging register 'green_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:238]
168
-INFO: [Synth 8-4471] merging register 'blue_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:239]
169
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
170
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
171
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
172
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
173
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
174
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
175
-INFO: [Synth 8-4471] merging register 'sendStr_reg[15][7:0]' into 'sendStr_reg[3][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
176
-INFO: [Synth 8-4471] merging register 'sendStr_reg[25][7:0]' into 'sendStr_reg[24][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
177
-INFO: [Synth 8-5544] ROM "sendStr[0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
178
-INFO: [Synth 8-5544] ROM "sendStr[1]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
179
-INFO: [Synth 8-5544] ROM "sendStr[2]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
180
-INFO: [Synth 8-5544] ROM "sendStr[3]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
181
-INFO: [Synth 8-5544] ROM "sendStr[4]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
182
-INFO: [Synth 8-5544] ROM "sendStr[5]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
183
-INFO: [Synth 8-5544] ROM "sendStr[6]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
184
-INFO: [Synth 8-5544] ROM "sendStr[7]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
185
-INFO: [Synth 8-5544] ROM "sendStr[8]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
186
-INFO: [Synth 8-5544] ROM "sendStr[9]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
187
-INFO: [Synth 8-5544] ROM "sendStr[10]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
188
-INFO: [Synth 8-5544] ROM "sendStr[11]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
189
-INFO: [Synth 8-5544] ROM "sendStr[12]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
190
-INFO: [Synth 8-5544] ROM "sendStr[13]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
191
-INFO: [Synth 8-5544] ROM "sendStr[14]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
192
-INFO: [Synth 8-5544] ROM "sendStr[18]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
193
-INFO: [Synth 8-5544] ROM "sendStr[19]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
194
-INFO: [Synth 8-5544] ROM "sendStr[21]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
195
-INFO: [Synth 8-5544] ROM "sendStr[22]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
196
-INFO: [Synth 8-5544] ROM "sendStr[23]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
197
-INFO: [Synth 8-5544] ROM "sendStr[24]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
198
-INFO: [Synth 8-5544] ROM "strEnd" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
199
-INFO: [Synth 8-5544] ROM "strIndex" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
200
----------------------------------------------------------------------------------
201
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 692.656 ; gain = 482.824
202
----------------------------------------------------------------------------------
203
-
204
-Report RTL Partitions: 
205
-+-+--------------+------------+----------+
206
-| |RTL Partition |Replication |Instances |
207
-+-+--------------+------------+----------+
208
-+-+--------------+------------+----------+
209
----------------------------------------------------------------------------------
210
-Start RTL Component Statistics 
211
----------------------------------------------------------------------------------
212
-Detailed RTL Component Info : 
213
-+---Adders : 
214
-	   2 Input     26 Bit       Adders := 1     
215
-	   2 Input     24 Bit       Adders := 1     
216
-	   3 Input     13 Bit       Adders := 2     
217
-	   2 Input     12 Bit       Adders := 7     
218
-	   2 Input     11 Bit       Adders := 1     
219
-	   2 Input      8 Bit       Adders := 1     
220
-	   4 Input      8 Bit       Adders := 1     
221
-	   3 Input      8 Bit       Adders := 2     
222
-	   2 Input      7 Bit       Adders := 1     
223
-	   2 Input      4 Bit       Adders := 4     
224
-	   3 Input      4 Bit       Adders := 2     
225
-+---XORs : 
226
-	   2 Input      1 Bit         XORs := 5     
227
-+---Registers : 
228
-	               31 Bit    Registers := 1     
229
-	               26 Bit    Registers := 1     
230
-	               24 Bit    Registers := 1     
231
-	               12 Bit    Registers := 10    
232
-	               11 Bit    Registers := 2     
233
-	               10 Bit    Registers := 1     
234
-	                8 Bit    Registers := 30    
235
-	                7 Bit    Registers := 1     
236
-	                6 Bit    Registers := 1     
237
-	                5 Bit    Registers := 2     
238
-	                4 Bit    Registers := 16    
239
-	                3 Bit    Registers := 1     
240
-	                2 Bit    Registers := 2     
241
-	                1 Bit    Registers := 42    
242
-+---Muxes : 
243
-	   3 Input     31 Bit        Muxes := 1     
244
-	   2 Input     26 Bit        Muxes := 1     
245
-	   2 Input     24 Bit        Muxes := 1     
246
-	   2 Input     16 Bit        Muxes := 1     
247
-	   2 Input     12 Bit        Muxes := 10    
248
-	   2 Input     11 Bit        Muxes := 1     
249
-	   2 Input      9 Bit        Muxes := 2     
250
-	  38 Input      8 Bit        Muxes := 1     
251
-	   3 Input      8 Bit        Muxes := 20    
252
-	   2 Input      7 Bit        Muxes := 10    
253
-	   3 Input      6 Bit        Muxes := 2     
254
-	   2 Input      6 Bit        Muxes := 13    
255
-	   4 Input      6 Bit        Muxes := 2     
256
-	   5 Input      6 Bit        Muxes := 1     
257
-	   3 Input      5 Bit        Muxes := 2     
258
-	   2 Input      5 Bit        Muxes := 4     
259
-	   4 Input      5 Bit        Muxes := 6     
260
-	   5 Input      5 Bit        Muxes := 1     
261
-	   2 Input      4 Bit        Muxes := 9     
262
-	   3 Input      4 Bit        Muxes := 3     
263
-	   4 Input      4 Bit        Muxes := 3     
264
-	   3 Input      3 Bit        Muxes := 3     
265
-	   4 Input      3 Bit        Muxes := 1     
266
-	   2 Input      3 Bit        Muxes := 1     
267
-	   9 Input      3 Bit        Muxes := 1     
268
-	   4 Input      2 Bit        Muxes := 1     
269
-	   2 Input      2 Bit        Muxes := 4     
270
-	  18 Input      2 Bit        Muxes := 1     
271
-	   3 Input      2 Bit        Muxes := 2     
272
-	  38 Input      2 Bit        Muxes := 6     
273
-	   2 Input      1 Bit        Muxes := 24    
274
-	   4 Input      1 Bit        Muxes := 2     
275
-	  18 Input      1 Bit        Muxes := 5     
276
-	  38 Input      1 Bit        Muxes := 5     
277
-	   3 Input      1 Bit        Muxes := 6     
278
-	   8 Input      1 Bit        Muxes := 1     
279
----------------------------------------------------------------------------------
280
-Finished RTL Component Statistics 
281
----------------------------------------------------------------------------------
282
----------------------------------------------------------------------------------
283
-Start RTL Hierarchical Component Statistics 
284
----------------------------------------------------------------------------------
285
-Hierarchical RTL Component report 
286
-Module GPIO_demo 
287
-Detailed RTL Component Info : 
288
-+---Adders : 
289
-	   2 Input      4 Bit       Adders := 1     
290
-+---Registers : 
291
-	               31 Bit    Registers := 1     
292
-	                8 Bit    Registers := 26    
293
-	                4 Bit    Registers := 2     
294
-	                3 Bit    Registers := 1     
295
-	                1 Bit    Registers := 1     
296
-+---Muxes : 
297
-	   3 Input     31 Bit        Muxes := 1     
298
-	   2 Input     16 Bit        Muxes := 1     
299
-	   3 Input      8 Bit        Muxes := 20    
300
-	   2 Input      7 Bit        Muxes := 10    
301
-	   2 Input      6 Bit        Muxes := 10    
302
-	   2 Input      4 Bit        Muxes := 1     
303
-	   9 Input      3 Bit        Muxes := 1     
304
-	   2 Input      2 Bit        Muxes := 1     
305
-	   2 Input      1 Bit        Muxes := 3     
306
-	   8 Input      1 Bit        Muxes := 1     
307
-Module debouncer 
308
-Detailed RTL Component Info : 
309
-+---XORs : 
310
-	   2 Input      1 Bit         XORs := 5     
311
-+---Registers : 
312
-	                5 Bit    Registers := 1     
313
-+---Muxes : 
314
-	   2 Input      1 Bit        Muxes := 5     
315
-Module UART_TX_CTRL 
316
-Detailed RTL Component Info : 
317
-+---Registers : 
318
-	               10 Bit    Registers := 1     
319
-	                2 Bit    Registers := 1     
320
-	                1 Bit    Registers := 1     
321
-+---Muxes : 
322
-	   4 Input      2 Bit        Muxes := 1     
323
-	   2 Input      1 Bit        Muxes := 4     
324
-	   4 Input      1 Bit        Muxes := 1     
325
-Module Ps2Interface 
326
-Detailed RTL Component Info : 
327
-+---Adders : 
328
-	   2 Input     11 Bit       Adders := 1     
329
-	   2 Input      7 Bit       Adders := 1     
330
-	   2 Input      4 Bit       Adders := 3     
331
-+---Registers : 
332
-	               11 Bit    Registers := 2     
333
-	                8 Bit    Registers := 1     
334
-	                7 Bit    Registers := 1     
335
-	                5 Bit    Registers := 1     
336
-	                4 Bit    Registers := 3     
337
-	                1 Bit    Registers := 17    
338
-+---Muxes : 
339
-	   2 Input     11 Bit        Muxes := 1     
340
-	   3 Input      5 Bit        Muxes := 1     
341
-	   2 Input      5 Bit        Muxes := 1     
342
-	   2 Input      4 Bit        Muxes := 4     
343
-	   3 Input      4 Bit        Muxes := 2     
344
-	   3 Input      3 Bit        Muxes := 2     
345
-	   2 Input      2 Bit        Muxes := 2     
346
-	  18 Input      2 Bit        Muxes := 1     
347
-	  18 Input      1 Bit        Muxes := 5     
348
-	   2 Input      1 Bit        Muxes := 7     
349
-	   4 Input      1 Bit        Muxes := 1     
350
-Module MouseCtl 
351
-Detailed RTL Component Info : 
352
-+---Adders : 
353
-	   2 Input     26 Bit       Adders := 1     
354
-	   2 Input     24 Bit       Adders := 1     
355
-	   2 Input     12 Bit       Adders := 4     
356
-	   2 Input      8 Bit       Adders := 1     
357
-+---Registers : 
358
-	               26 Bit    Registers := 1     
359
-	               24 Bit    Registers := 1     
360
-	               12 Bit    Registers := 6     
361
-	                8 Bit    Registers := 3     
362
-	                6 Bit    Registers := 1     
363
-	                4 Bit    Registers := 1     
364
-	                1 Bit    Registers := 17    
365
-+---Muxes : 
366
-	   2 Input     26 Bit        Muxes := 1     
367
-	   2 Input     24 Bit        Muxes := 1     
368
-	   2 Input     12 Bit        Muxes := 10    
369
-	   2 Input      9 Bit        Muxes := 2     
370
-	  38 Input      8 Bit        Muxes := 1     
371
-	   3 Input      6 Bit        Muxes := 2     
372
-	   2 Input      6 Bit        Muxes := 3     
373
-	   4 Input      6 Bit        Muxes := 2     
374
-	   5 Input      6 Bit        Muxes := 1     
375
-	   3 Input      5 Bit        Muxes := 1     
376
-	   4 Input      5 Bit        Muxes := 6     
377
-	   5 Input      5 Bit        Muxes := 1     
378
-	   2 Input      5 Bit        Muxes := 3     
379
-	   3 Input      4 Bit        Muxes := 1     
380
-	   4 Input      4 Bit        Muxes := 3     
381
-	   2 Input      4 Bit        Muxes := 1     
382
-	   3 Input      3 Bit        Muxes := 1     
383
-	   4 Input      3 Bit        Muxes := 1     
384
-	   2 Input      3 Bit        Muxes := 1     
385
-	   3 Input      2 Bit        Muxes := 2     
386
-	   2 Input      2 Bit        Muxes := 1     
387
-	  38 Input      2 Bit        Muxes := 6     
388
-	  38 Input      1 Bit        Muxes := 5     
389
-	   2 Input      1 Bit        Muxes := 5     
390
-	   3 Input      1 Bit        Muxes := 6     
391
-Module MouseDisplay 
392
-Detailed RTL Component Info : 
393
-+---Adders : 
394
-	   3 Input     13 Bit       Adders := 2     
395
-	   2 Input     12 Bit       Adders := 3     
396
-	   3 Input      4 Bit       Adders := 2     
397
-+---Registers : 
398
-	                4 Bit    Registers := 1     
399
-	                2 Bit    Registers := 1     
400
-	                1 Bit    Registers := 1     
401
-Module vga_ctrl 
402
-Detailed RTL Component Info : 
403
-+---Adders : 
404
-	   4 Input      8 Bit       Adders := 1     
405
-	   3 Input      8 Bit       Adders := 2     
406
-+---Registers : 
407
-	               12 Bit    Registers := 4     
408
-	                4 Bit    Registers := 9     
409
-	                1 Bit    Registers := 5     
410
-+---Muxes : 
411
-	   2 Input      4 Bit        Muxes := 3     
412
----------------------------------------------------------------------------------
413
-Finished RTL Hierarchical Component Statistics
414
----------------------------------------------------------------------------------
415
----------------------------------------------------------------------------------
416
-Start Part Resource Summary
417
----------------------------------------------------------------------------------
418
-Part Resources:
419
-DSPs: 90 (col length:60)
420
-BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
421
----------------------------------------------------------------------------------
422
-Finished Part Resource Summary
423
----------------------------------------------------------------------------------
424
----------------------------------------------------------------------------------
425
-Start Cross Boundary and Area Optimization
426
----------------------------------------------------------------------------------
427
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
428
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
429
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
430
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
431
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
432
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
433
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
434
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
435
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[8]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
436
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[9]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
437
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[10]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
438
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[11]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
439
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
440
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
441
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
442
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
443
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
444
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
445
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
446
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
447
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[8]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
448
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[10]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
449
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_vga_ctrl/Inst_MouseCtl/\y_max_reg[11] )
450
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[0]' (FDSE) to 'strEnd_reg[1]'
451
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[2]' (FDRE) to 'strEnd_reg[5]'
452
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[3]' (FDSE) to 'strEnd_reg[4]'
453
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\strEnd_reg[4] )
454
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[5]' (FDRE) to 'strEnd_reg[6]'
455
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[6]' (FDRE) to 'strEnd_reg[7]'
456
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[7]' (FDRE) to 'strEnd_reg[8]'
457
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[8]' (FDRE) to 'strEnd_reg[9]'
458
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[9]' (FDRE) to 'strEnd_reg[10]'
459
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[10]' (FDRE) to 'strEnd_reg[11]'
460
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[11]' (FDRE) to 'strEnd_reg[12]'
461
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[12]' (FDRE) to 'strEnd_reg[13]'
462
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[13]' (FDRE) to 'strEnd_reg[14]'
463
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[14]' (FDRE) to 'strEnd_reg[15]'
464
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[15]' (FDRE) to 'strEnd_reg[16]'
465
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[16]' (FDRE) to 'strEnd_reg[17]'
466
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[17]' (FDRE) to 'strEnd_reg[18]'
467
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[18]' (FDRE) to 'strEnd_reg[19]'
468
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[19]' (FDRE) to 'strEnd_reg[20]'
469
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[20]' (FDRE) to 'strEnd_reg[21]'
470
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[21]' (FDRE) to 'strEnd_reg[22]'
471
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[22]' (FDRE) to 'strEnd_reg[23]'
472
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[23]' (FDRE) to 'strEnd_reg[24]'
473
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[24]' (FDRE) to 'strEnd_reg[25]'
474
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[25]' (FDRE) to 'strEnd_reg[26]'
475
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[26]' (FDRE) to 'strEnd_reg[27]'
476
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[27]' (FDRE) to 'strEnd_reg[28]'
477
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[28]' (FDRE) to 'strEnd_reg[29]'
478
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[29]' (FDRE) to 'strEnd_reg[30]'
479
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\strEnd_reg[30] )
480
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][7]' (FDRE) to 'sendStr_reg[26][1]'
481
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][7]' (FDRE) to 'sendStr_reg[26][1]'
482
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][7]' (FDRE) to 'sendStr_reg[23][6]'
483
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][7]' (FDRE) to 'sendStr_reg[22][5]'
484
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][7]' (FDRE) to 'sendStr_reg[21][4]'
485
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][7]' (FDRE) to 'sendStr_reg[19][7]'
486
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][7]' (FDRE) to 'sendStr_reg[19][4]'
487
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][7]' (FDRE) to 'sendStr_reg[18][3]'
488
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][7]' (FDRE) to 'sendStr_reg[5][7]'
489
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][7]' (FDRE) to 'sendStr_reg[5][7]'
490
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][7]' (FDRE) to 'sendStr_reg[14][3]'
491
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[13][7]' (FDRE) to 'sendStr_reg[13][4]'
492
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][7]' (FDRE) to 'sendStr_reg[12][4]'
493
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][7]' (FDRE) to 'sendStr_reg[11][2]'
494
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][7]' (FDRE) to 'sendStr_reg[10][3]'
495
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][7]' (FDRE) to 'sendStr_reg[9][4]'
496
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][7]' (FDRE) to 'sendStr_reg[8][3]'
497
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[7][7]' (FDRE) to 'sendStr_reg[7][3]'
498
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][7]' (FDRE) to 'sendStr_reg[6][3]'
499
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][7]' (FDRE) to 'sendStr_reg[17][3]'
500
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[4][7] )
501
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[3][7]' (FDRE) to 'sendStr_reg[3][3]'
502
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[2][7]' (FDRE) to 'sendStr_reg[2][3]'
503
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][7]' (FDRE) to 'sendStr_reg[1][1]'
504
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[0][7]' (FDRE) to 'sendStr_reg[0][5]'
505
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][6]' (FDRE) to 'sendStr_reg[26][1]'
506
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][6]' (FDRE) to 'sendStr_reg[26][1]'
507
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][6]' (FDRE) to 'sendStr_reg[23][4]'
508
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][6]' (FDSE) to 'sendStr_reg[22][2]'
509
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][6]' (FDSE) to 'sendStr_reg[21][3]'
510
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][6]' (FDSE) to 'sendStr_reg[19][6]'
511
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][6]' (FDSE) to 'sendStr_reg[19][2]'
512
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][6]' (FDRE) to 'sendStr_reg[18][4]'
513
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][6]' (FDSE) to 'sendStr_reg[5][6]'
514
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][6]' (FDSE) to 'sendStr_reg[5][6]'
515
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][6]' (FDSE) to 'sendStr_reg[14][2]'
516
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][6]' (FDSE) to 'sendStr_reg[12][3]'
517
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][6]' (FDSE) to 'sendStr_reg[11][0]'
518
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][6]' (FDSE) to 'sendStr_reg[10][4]'
519
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][6]' (FDSE) to 'sendStr_reg[9][2]'
520
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][6]' (FDRE) to 'sendStr_reg[8][4]'
521
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][6]' (FDSE) to 'sendStr_reg[6][4]'
522
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][6]' (FDSE) to 'sendStr_reg[5][3]'
523
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[4][6]' (FDSE) to 'sendStr_reg[4][1]'
524
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[3][6] )
525
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[2][6] )
526
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][6]' (FDRE) to 'sendStr_reg[1][5]'
527
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][5]' (FDRE) to 'sendStr_reg[26][1]'
528
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][5]' (FDRE) to 'sendStr_reg[26][1]'
529
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][5]' (FDRE) to 'sendStr_reg[22][4]'
530
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][5]' (FDRE) to 'sendStr_reg[19][5]'
531
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][5]' (FDRE) to 'sendStr_reg[19][0]'
532
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[18][5] )
533
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][5]' (FDRE) to 'sendStr_reg[5][5]'
534
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
535
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[8][5] )
536
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[22][4] )
537
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[13][4] )
538
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[12][4] )
539
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[10][4] )
540
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[7][4] )
541
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[16][3] )
542
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[9][3] )
543
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[5][3] )
544
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[19][2] )
545
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[13][2] )
546
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[11][2] )
547
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[10][2] )
548
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[7][2] )
549
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[6][2] )
550
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[23][1] )
551
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[22][1] )
552
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[21][1] )
553
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[19][1] )
554
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[14][1] )
555
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[3][1] )
556
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[1][1] )
557
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[0][1] )
558
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[26][0] )
559
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[24][0] )
560
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[23][0] )
561
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[21][0] )
562
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[18][0] )
563
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[14][0] )
564
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[11][0] )
565
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[9][0] )
566
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[8][0] )
567
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[4][0] )
568
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[2][0] )
569
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[1][0] )
570
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[0][0] )
571
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (Inst_UART_TX_CTRL/\txData_reg[9] )
572
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[0] )
573
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uartData_reg[7] )
574
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[8] )
575
-WARNING: [Synth 8-3332] Sequential element (txData_reg[9]) is unused and will be removed from module UART_TX_CTRL.
576
-WARNING: [Synth 8-3332] Sequential element (txData_reg[8]) is unused and will be removed from module UART_TX_CTRL.
577
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[3]) is unused and will be removed from module MouseCtl.
578
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[2]) is unused and will be removed from module MouseCtl.
579
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[1]) is unused and will be removed from module MouseCtl.
580
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[0]) is unused and will be removed from module MouseCtl.
581
-WARNING: [Synth 8-3332] Sequential element (left_down_reg) is unused and will be removed from module MouseCtl.
582
-WARNING: [Synth 8-3332] Sequential element (left_reg) is unused and will be removed from module MouseCtl.
583
-WARNING: [Synth 8-3332] Sequential element (middle_down_reg) is unused and will be removed from module MouseCtl.
584
-WARNING: [Synth 8-3332] Sequential element (middle_reg) is unused and will be removed from module MouseCtl.
585
-WARNING: [Synth 8-3332] Sequential element (right_down_reg) is unused and will be removed from module MouseCtl.
586
-WARNING: [Synth 8-3332] Sequential element (right_reg) is unused and will be removed from module MouseCtl.
587
-WARNING: [Synth 8-3332] Sequential element (new_event_reg) is unused and will be removed from module MouseCtl.
588
-WARNING: [Synth 8-3332] Sequential element (y_max_reg[11]) is unused and will be removed from module MouseCtl.
589
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[9]) is unused and will be removed from module vga_ctrl.
590
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[8]) is unused and will be removed from module vga_ctrl.
591
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
592
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
593
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
594
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
595
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
596
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
597
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
598
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
599
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
600
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
601
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
602
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
603
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
604
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
605
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
606
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
607
-WARNING: [Synth 8-3332] Sequential element (strEnd_reg[30]) is unused and will be removed from module GPIO_demo.
608
-WARNING: [Synth 8-3332] Sequential element (strEnd_reg[4]) is unused and will be removed from module GPIO_demo.
609
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][1]) is unused and will be removed from module GPIO_demo.
610
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][0]) is unused and will be removed from module GPIO_demo.
611
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][1]) is unused and will be removed from module GPIO_demo.
612
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][0]) is unused and will be removed from module GPIO_demo.
613
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][6]) is unused and will be removed from module GPIO_demo.
614
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][0]) is unused and will be removed from module GPIO_demo.
615
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][6]) is unused and will be removed from module GPIO_demo.
616
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][1]) is unused and will be removed from module GPIO_demo.
617
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][7]) is unused and will be removed from module GPIO_demo.
618
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][0]) is unused and will be removed from module GPIO_demo.
619
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[6][2]) is unused and will be removed from module GPIO_demo.
620
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][4]) is unused and will be removed from module GPIO_demo.
621
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][2]) is unused and will be removed from module GPIO_demo.
622
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][5]) is unused and will be removed from module GPIO_demo.
623
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][0]) is unused and will be removed from module GPIO_demo.
624
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][3]) is unused and will be removed from module GPIO_demo.
625
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][0]) is unused and will be removed from module GPIO_demo.
626
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][4]) is unused and will be removed from module GPIO_demo.
627
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][2]) is unused and will be removed from module GPIO_demo.
628
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][2]) is unused and will be removed from module GPIO_demo.
629
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][0]) is unused and will be removed from module GPIO_demo.
630
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[12][4]) is unused and will be removed from module GPIO_demo.
631
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][4]) is unused and will be removed from module GPIO_demo.
632
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][2]) is unused and will be removed from module GPIO_demo.
633
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][1]) is unused and will be removed from module GPIO_demo.
634
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][0]) is unused and will be removed from module GPIO_demo.
635
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][5]) is unused and will be removed from module GPIO_demo.
636
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][0]) is unused and will be removed from module GPIO_demo.
637
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][1]) is unused and will be removed from module GPIO_demo.
638
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][0]) is unused and will be removed from module GPIO_demo.
639
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][4]) is unused and will be removed from module GPIO_demo.
640
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][1]) is unused and will be removed from module GPIO_demo.
641
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][1]) is unused and will be removed from module GPIO_demo.
642
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][0]) is unused and will be removed from module GPIO_demo.
643
-WARNING: [Synth 8-3332] Sequential element (uartData_reg[7]) is unused and will be removed from module GPIO_demo.
644
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][2]) is unused and will be removed from module GPIO_demo.
645
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[5][3]) is unused and will be removed from module GPIO_demo.
646
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[26][0]) is unused and will be removed from module GPIO_demo.
647
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[16][3]) is unused and will be removed from module GPIO_demo.
648
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[24][0]) is unused and will be removed from module GPIO_demo.
649
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][1]) is unused and will be removed from module GPIO_demo.
650
-WARNING: [Synth 8-3332] Sequential element (y_max_reg[9]) is unused and will be removed from module MouseCtl.
651
----------------------------------------------------------------------------------
652
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 692.656 ; gain = 482.824
653
----------------------------------------------------------------------------------
654
----------------------------------------------------------------------------------
655
-Start ROM, RAM, DSP and Shift Register Reporting
656
----------------------------------------------------------------------------------
657
-
658
-ROM:
659
-+-------------+-------------+---------------+----------------+
660
-|Module Name  | RTL Object  | Depth x Width | Implemented As | 
661
-+-------------+-------------+---------------+----------------+
662
-|MouseCtl     | write_data  | 64x1          | LUT            | 
663
-|MouseDisplay | mouserom[0] | 256x2         | LUT            | 
664
-+-------------+-------------+---------------+----------------+
665
-
666
----------------------------------------------------------------------------------
667
-Finished ROM, RAM, DSP and Shift Register Reporting
668
----------------------------------------------------------------------------------
669
-
670
-Report RTL Partitions: 
671
-+-+--------------+------------+----------+
672
-| |RTL Partition |Replication |Instances |
673
-+-+--------------+------------+----------+
674
-+-+--------------+------------+----------+
675
----------------------------------------------------------------------------------
676
-Start Applying XDC Timing Constraints
677
----------------------------------------------------------------------------------
678
----------------------------------------------------------------------------------
679
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 692.656 ; gain = 482.824
680
----------------------------------------------------------------------------------
681
-
682
-Report RTL Partitions: 
683
-+-+--------------+------------+----------+
684
-| |RTL Partition |Replication |Instances |
685
-+-+--------------+------------+----------+
686
-+-+--------------+------------+----------+
687
----------------------------------------------------------------------------------
688
-Start Technology Mapping
689
----------------------------------------------------------------------------------
690
----------------------------------------------------------------------------------
691
-Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
692
----------------------------------------------------------------------------------
693
-
694
-Report RTL Partitions: 
695
-+-+--------------+------------+----------+
696
-| |RTL Partition |Replication |Instances |
697
-+-+--------------+------------+----------+
698
-+-+--------------+------------+----------+
699
----------------------------------------------------------------------------------
700
-Start IO Insertion
701
----------------------------------------------------------------------------------
702
----------------------------------------------------------------------------------
703
-Start Final Netlist Cleanup
704
----------------------------------------------------------------------------------
705
-INFO: [Synth 8-5365] Flop ps2_data_h_reg is being inverted and renamed to ps2_data_h_reg_inv.
706
----------------------------------------------------------------------------------
707
-Finished Final Netlist Cleanup
708
----------------------------------------------------------------------------------
709
----------------------------------------------------------------------------------
710
-Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
711
----------------------------------------------------------------------------------
712
-
713
-Report Check Netlist: 
714
-+------+------------------+-------+---------+-------+------------------+
715
-|      |Item              |Errors |Warnings |Status |Description       |
716
-+------+------------------+-------+---------+-------+------------------+
717
-|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
718
-+------+------------------+-------+---------+-------+------------------+
719
----------------------------------------------------------------------------------
720
-Start Renaming Generated Instances
721
----------------------------------------------------------------------------------
722
----------------------------------------------------------------------------------
723
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
724
----------------------------------------------------------------------------------
725
-
726
-Report RTL Partitions: 
727
-+-+--------------+------------+----------+
728
-| |RTL Partition |Replication |Instances |
729
-+-+--------------+------------+----------+
730
-+-+--------------+------------+----------+
731
----------------------------------------------------------------------------------
732
-Start Handling Custom Attributes
733
----------------------------------------------------------------------------------
734
----------------------------------------------------------------------------------
735
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
736
----------------------------------------------------------------------------------
737
----------------------------------------------------------------------------------
738
-Start Writing Synthesis Report
739
----------------------------------------------------------------------------------
740
-
741
-Report BlackBoxes: 
742
-+-+--------------+----------+
743
-| |BlackBox name |Instances |
744
-+-+--------------+----------+
745
-+-+--------------+----------+
746
-
747
-Report Cell Usage: 
748
-+------+-----------+------+
749
-|      |Cell       |Count |
750
-+------+-----------+------+
751
-|1     |BUFG       |     3|
752
-|2     |CARRY4     |   132|
753
-|3     |LUT1       |   368|
754
-|4     |LUT2       |   207|
755
-|5     |LUT3       |    91|
756
-|6     |LUT4       |   138|
757
-|7     |LUT5       |    73|
758
-|8     |LUT6       |   157|
759
-|9     |MMCME2_ADV |     1|
760
-|10    |MUXF7      |     3|
761
-|11    |FDRE       |   579|
762
-|12    |FDSE       |     2|
763
-|13    |IBUF       |    22|
764
-|14    |IOBUF      |     2|
765
-|15    |OBUF       |    43|
766
-+------+-----------+------+
767
-
768
-Report Instance Areas: 
769
-+------+------------------------+------------------+------+
770
-|      |Instance                |Module            |Cells |
771
-+------+------------------------+------------------+------+
772
-|1     |top                     |                  |  1821|
773
-|2     |  Inst_btn_debounce     |debouncer         |   215|
774
-|3     |  Inst_UART_TX_CTRL     |UART_TX_CTRL      |   133|
775
-|4     |  Inst_vga_ctrl         |vga_ctrl          |  1100|
776
-|5     |    clk_wiz_0_inst      |clk_wiz_0         |     3|
777
-|6     |      U0                |clk_wiz_0_clk_wiz |     3|
778
-|7     |    Inst_MouseCtl       |MouseCtl          |   680|
779
-|8     |      Inst_Ps2Interface |Ps2Interface      |   211|
780
-|9     |    Inst_MouseDisplay   |MouseDisplay      |   124|
781
-+------+------------------------+------------------+------+
782
----------------------------------------------------------------------------------
783
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
784
----------------------------------------------------------------------------------
785
-Synthesis finished with 0 errors, 0 critical warnings and 76 warnings.
786
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 692.656 ; gain = 116.863
787
-Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 692.656 ; gain = 482.824
788
-INFO: [Project 1-571] Translating synthesized netlist
789
-INFO: [Netlist 29-17] Analyzing 157 Unisim elements for replacement
790
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
791
-INFO: [Project 1-570] Preparing netlist for logic optimization
792
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
793
-INFO: [Project 1-111] Unisim Transformation Summary:
794
-  A total of 2 instances were transformed.
795
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
796
-
797
-INFO: [Common 17-83] Releasing license: Synthesis
798
-245 Infos, 77 Warnings, 0 Critical Warnings and 0 Errors encountered.
799
-synth_design completed successfully
800
-synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 692.656 ; gain = 424.176
801
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.dcp' has been generated.
802
-report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 692.656 ; gain = 0.000
803
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:11:26 2021...

BIN
proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.pb View File


+ 0
- 185
proj/GPIO.runs/synth_1/GPIO_demo_utilization_synth.rpt View File

1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
--------------------------------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:11:26 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_utilization -file GPIO_demo_utilization_synth.rpt -pb GPIO_demo_utilization_synth.pb
7
-| Design       : GPIO_demo
8
-| Device       : 7a35tcpg236-1
9
-| Design State : Synthesized
10
--------------------------------------------------------------------------------------------------------------
11
-
12
-Utilization Design Information
13
-
14
-Table of Contents
15
------------------
16
-1. Slice Logic
17
-1.1 Summary of Registers by Type
18
-2. Memory
19
-3. DSP
20
-4. IO and GT Specific
21
-5. Clocking
22
-6. Specific Feature
23
-7. Primitives
24
-8. Black Boxes
25
-9. Instantiated Netlists
26
-
27
-1. Slice Logic
28
---------------
29
-
30
-+-------------------------+------+-------+-----------+-------+
31
-|        Site Type        | Used | Fixed | Available | Util% |
32
-+-------------------------+------+-------+-----------+-------+
33
-| Slice LUTs*             |  903 |     0 |     20800 |  4.34 |
34
-|   LUT as Logic          |  903 |     0 |     20800 |  4.34 |
35
-|   LUT as Memory         |    0 |     0 |      9600 |  0.00 |
36
-| Slice Registers         |  581 |     0 |     41600 |  1.40 |
37
-|   Register as Flip Flop |  581 |     0 |     41600 |  1.40 |
38
-|   Register as Latch     |    0 |     0 |     41600 |  0.00 |
39
-| F7 Muxes                |    3 |     0 |     16300 |  0.02 |
40
-| F8 Muxes                |    0 |     0 |      8150 |  0.00 |
41
-+-------------------------+------+-------+-----------+-------+
42
-* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
43
-
44
-
45
-1.1 Summary of Registers by Type
46
---------------------------------
47
-
48
-+-------+--------------+-------------+--------------+
49
-| Total | Clock Enable | Synchronous | Asynchronous |
50
-+-------+--------------+-------------+--------------+
51
-| 0     |            _ |           - |            - |
52
-| 0     |            _ |           - |          Set |
53
-| 0     |            _ |           - |        Reset |
54
-| 0     |            _ |         Set |            - |
55
-| 0     |            _ |       Reset |            - |
56
-| 0     |          Yes |           - |            - |
57
-| 0     |          Yes |           - |          Set |
58
-| 0     |          Yes |           - |        Reset |
59
-| 2     |          Yes |         Set |            - |
60
-| 579   |          Yes |       Reset |            - |
61
-+-------+--------------+-------------+--------------+
62
-
63
-
64
-2. Memory
65
----------
66
-
67
-+----------------+------+-------+-----------+-------+
68
-|    Site Type   | Used | Fixed | Available | Util% |
69
-+----------------+------+-------+-----------+-------+
70
-| Block RAM Tile |    0 |     0 |        50 |  0.00 |
71
-|   RAMB36/FIFO* |    0 |     0 |        50 |  0.00 |
72
-|   RAMB18       |    0 |     0 |       100 |  0.00 |
73
-+----------------+------+-------+-----------+-------+
74
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
75
-
76
-
77
-3. DSP
78
-------
79
-
80
-+-----------+------+-------+-----------+-------+
81
-| Site Type | Used | Fixed | Available | Util% |
82
-+-----------+------+-------+-----------+-------+
83
-| DSPs      |    0 |     0 |        90 |  0.00 |
84
-+-----------+------+-------+-----------+-------+
85
-
86
-
87
-4. IO and GT Specific
88
----------------------
89
-
90
-+-----------------------------+------+-------+-----------+-------+
91
-|          Site Type          | Used | Fixed | Available | Util% |
92
-+-----------------------------+------+-------+-----------+-------+
93
-| Bonded IOB                  |   67 |     0 |       106 | 63.21 |
94
-| Bonded IPADs                |    0 |     0 |        10 |  0.00 |
95
-| Bonded OPADs                |    0 |     0 |         4 |  0.00 |
96
-| PHY_CONTROL                 |    0 |     0 |         5 |  0.00 |
97
-| PHASER_REF                  |    0 |     0 |         5 |  0.00 |
98
-| OUT_FIFO                    |    0 |     0 |        20 |  0.00 |
99
-| IN_FIFO                     |    0 |     0 |        20 |  0.00 |
100
-| IDELAYCTRL                  |    0 |     0 |         5 |  0.00 |
101
-| IBUFDS                      |    0 |     0 |       104 |  0.00 |
102
-| GTPE2_CHANNEL               |    0 |     0 |         2 |  0.00 |
103
-| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        20 |  0.00 |
104
-| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        20 |  0.00 |
105
-| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       250 |  0.00 |
106
-| IBUFDS_GTE2                 |    0 |     0 |         2 |  0.00 |
107
-| ILOGIC                      |    0 |     0 |       106 |  0.00 |
108
-| OLOGIC                      |    0 |     0 |       106 |  0.00 |
109
-+-----------------------------+------+-------+-----------+-------+
110
-
111
-
112
-5. Clocking
113
------------
114
-
115
-+------------+------+-------+-----------+-------+
116
-|  Site Type | Used | Fixed | Available | Util% |
117
-+------------+------+-------+-----------+-------+
118
-| BUFGCTRL   |    3 |     0 |        32 |  9.38 |
119
-| BUFIO      |    0 |     0 |        20 |  0.00 |
120
-| MMCME2_ADV |    1 |     0 |         5 | 20.00 |
121
-| PLLE2_ADV  |    0 |     0 |         5 |  0.00 |
122
-| BUFMRCE    |    0 |     0 |        10 |  0.00 |
123
-| BUFHCE     |    0 |     0 |        72 |  0.00 |
124
-| BUFR       |    0 |     0 |        20 |  0.00 |
125
-+------------+------+-------+-----------+-------+
126
-
127
-
128
-6. Specific Feature
129
--------------------
130
-
131
-+-------------+------+-------+-----------+-------+
132
-|  Site Type  | Used | Fixed | Available | Util% |
133
-+-------------+------+-------+-----------+-------+
134
-| BSCANE2     |    0 |     0 |         4 |  0.00 |
135
-| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
136
-| DNA_PORT    |    0 |     0 |         1 |  0.00 |
137
-| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
138
-| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
139
-| ICAPE2      |    0 |     0 |         2 |  0.00 |
140
-| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
141
-| STARTUPE2   |    0 |     0 |         1 |  0.00 |
142
-| XADC        |    0 |     0 |         1 |  0.00 |
143
-+-------------+------+-------+-----------+-------+
144
-
145
-
146
-7. Primitives
147
--------------
148
-
149
-+------------+------+---------------------+
150
-|  Ref Name  | Used | Functional Category |
151
-+------------+------+---------------------+
152
-| FDRE       |  579 |        Flop & Latch |
153
-| LUT1       |  368 |                 LUT |
154
-| LUT2       |  207 |                 LUT |
155
-| LUT6       |  157 |                 LUT |
156
-| LUT4       |  138 |                 LUT |
157
-| CARRY4     |  132 |          CarryLogic |
158
-| LUT3       |   91 |                 LUT |
159
-| LUT5       |   73 |                 LUT |
160
-| OBUF       |   43 |                  IO |
161
-| IBUF       |   24 |                  IO |
162
-| MUXF7      |    3 |               MuxFx |
163
-| BUFG       |    3 |               Clock |
164
-| OBUFT      |    2 |                  IO |
165
-| FDSE       |    2 |        Flop & Latch |
166
-| MMCME2_ADV |    1 |               Clock |
167
-+------------+------+---------------------+
168
-
169
-
170
-8. Black Boxes
171
---------------
172
-
173
-+----------+------+
174
-| Ref Name | Used |
175
-+----------+------+
176
-
177
-
178
-9. Instantiated Netlists
179
-------------------------
180
-
181
-+----------+------+
182
-| Ref Name | Used |
183
-+----------+------+
184
-
185
-

+ 0
- 244
proj/GPIO.runs/synth_1/ISEWrap.js View File

1
-//
2
-//  Vivado(TM)
3
-//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
4
-//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
5
-//
6
-
7
-// GLOBAL VARIABLES
8
-var ISEShell = new ActiveXObject( "WScript.Shell" );
9
-var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
10
-var ISERunDir = "";
11
-var ISELogFile = "runme.log";
12
-var ISELogFileStr = null;
13
-var ISELogEcho = true;
14
-var ISEOldVersionWSH = false;
15
-
16
-
17
-
18
-// BOOTSTRAP
19
-ISEInit();
20
-
21
-
22
-
23
-//
24
-// ISE FUNCTIONS
25
-//
26
-function ISEInit() {
27
-
28
-  // 1. RUN DIR setup
29
-  var ISEScrFP = WScript.ScriptFullName;
30
-  var ISEScrN = WScript.ScriptName;
31
-  ISERunDir = 
32
-    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
33
-
34
-  // 2. LOG file setup
35
-  ISELogFileStr = ISEOpenFile( ISELogFile );
36
-
37
-  // 3. LOG echo?
38
-  var ISEScriptArgs = WScript.Arguments;
39
-  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
40
-    if ( ISEScriptArgs(loopi) == "-quiet" ) {
41
-      ISELogEcho = false;
42
-      break;
43
-    }
44
-  }
45
-
46
-  // 4. WSH version check
47
-  var ISEOptimalVersionWSH = 5.6;
48
-  var ISECurrentVersionWSH = WScript.Version;
49
-  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
50
-
51
-    ISEStdErr( "" );
52
-    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
53
-	       ISEOptimalVersionWSH + " or higher. Downloads" );
54
-    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
55
-    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
56
-    ISEStdErr( "" );
57
-
58
-    ISEOldVersionWSH = true;
59
-  }
60
-
61
-}
62
-
63
-function ISEStep( ISEProg, ISEArgs ) {
64
-
65
-  // CHECK for a STOP FILE
66
-  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
67
-    ISEStdErr( "" );
68
-    ISEStdErr( "*** Halting run - EA reset detected ***" );
69
-    ISEStdErr( "" );
70
-    WScript.Quit( 1 );
71
-  }
72
-
73
-  // WRITE STEP HEADER to LOG
74
-  ISEStdOut( "" );
75
-  ISEStdOut( "*** Running " + ISEProg );
76
-  ISEStdOut( "    with args " + ISEArgs );
77
-  ISEStdOut( "" );
78
-
79
-  // LAUNCH!
80
-  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
81
-  if ( ISEExitCode != 0 ) {
82
-    WScript.Quit( ISEExitCode );
83
-  }
84
-
85
-}
86
-
87
-function ISEExec( ISEProg, ISEArgs ) {
88
-
89
-  var ISEStep = ISEProg;
90
-  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
91
-    ISEProg += ".bat";
92
-  }
93
-
94
-  var ISECmdLine = ISEProg + " " + ISEArgs;
95
-  var ISEExitCode = 1;
96
-
97
-  if ( ISEOldVersionWSH ) { // WSH 5.1
98
-
99
-    // BEGIN file creation
100
-    ISETouchFile( ISEStep, "begin" );
101
-
102
-    // LAUNCH!
103
-    ISELogFileStr.Close();
104
-    ISECmdLine = 
105
-      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
106
-    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
107
-    ISELogFileStr = ISEOpenFile( ISELogFile );
108
-
109
-  } else {  // WSH 5.6
110
-
111
-    // LAUNCH!
112
-    ISEShell.CurrentDirectory = ISERunDir;
113
-
114
-    // Redirect STDERR to STDOUT
115
-    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
116
-    var ISEProcess = ISEShell.Exec( ISECmdLine );
117
-    
118
-    // BEGIN file creation
119
-    var ISENetwork = WScript.CreateObject( "WScript.Network" );
120
-    var ISEHost = ISENetwork.ComputerName;
121
-    var ISEUser = ISENetwork.UserName;
122
-    var ISEPid = ISEProcess.ProcessID;
123
-    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
124
-    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
125
-    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
126
-    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
127
-			    "\" Owner=\"" + ISEUser + 
128
-			    "\" Host=\"" + ISEHost + 
129
-			    "\" Pid=\"" + ISEPid +
130
-			    "\">" );
131
-    ISEBeginFile.WriteLine( "    </Process>" );
132
-    ISEBeginFile.WriteLine( "</ProcessHandle>" );
133
-    ISEBeginFile.Close();
134
-    
135
-    var ISEOutStr = ISEProcess.StdOut;
136
-    var ISEErrStr = ISEProcess.StdErr;
137
-    
138
-    // WAIT for ISEStep to finish
139
-    while ( ISEProcess.Status == 0 ) {
140
-      
141
-      // dump stdout then stderr - feels a little arbitrary
142
-      while ( !ISEOutStr.AtEndOfStream ) {
143
-        ISEStdOut( ISEOutStr.ReadLine() );
144
-      }  
145
-      
146
-      WScript.Sleep( 100 );
147
-    }
148
-
149
-    ISEExitCode = ISEProcess.ExitCode;
150
-  }
151
-
152
-  ISELogFileStr.Close();
153
-
154
-  // END/ERROR file creation
155
-  if ( ISEExitCode != 0 ) {    
156
-    ISETouchFile( ISEStep, "error" );
157
-    
158
-  } else {
159
-    ISETouchFile( ISEStep, "end" );
160
-  }
161
-
162
-  return ISEExitCode;
163
-}
164
-
165
-
166
-//
167
-// UTILITIES
168
-//
169
-function ISEStdOut( ISELine ) {
170
-
171
-  ISELogFileStr.WriteLine( ISELine );
172
-  
173
-  if ( ISELogEcho ) {
174
-    WScript.StdOut.WriteLine( ISELine );
175
-  }
176
-}
177
-
178
-function ISEStdErr( ISELine ) {
179
-  
180
-  ISELogFileStr.WriteLine( ISELine );
181
-
182
-  if ( ISELogEcho ) {
183
-    WScript.StdErr.WriteLine( ISELine );
184
-  }
185
-}
186
-
187
-function ISETouchFile( ISERoot, ISEStatus ) {
188
-
189
-  var ISETFile = 
190
-    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
191
-  ISETFile.Close();
192
-}
193
-
194
-function ISEOpenFile( ISEFilename ) {
195
-
196
-  // This function has been updated to deal with a problem seen in CR #870871.
197
-  // In that case the user runs a script that runs impl_1, and then turns around
198
-  // and runs impl_1 -to_step write_bitstream. That second run takes place in
199
-  // the same directory, which means we may hit some of the same files, and in
200
-  // particular, we will open the runme.log file. Even though this script closes
201
-  // the file (now), we see cases where a subsequent attempt to open the file
202
-  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
203
-  // play? In any case, we try to work around this by first waiting if the file
204
-  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
205
-  // and try to open the file 10 times with a one second delay after each attempt.
206
-  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
207
-  // If there is an unrecognized exception when trying to open the file, we output
208
-  // an error message and write details to an exception.log file.
209
-  var ISEFullPath = ISERunDir + "/" + ISEFilename;
210
-  if (ISEFileSys.FileExists(ISEFullPath)) {
211
-    // File is already there. This could be a problem. Wait in case it is still in use.
212
-    WScript.Sleep(5000);
213
-  }
214
-  var i;
215
-  for (i = 0; i < 10; ++i) {
216
-    try {
217
-      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
218
-    } catch (exception) {
219
-      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
220
-      if (error_code == 52) { // 52 is bad file name or number.
221
-        // Wait a second and try again.
222
-        WScript.Sleep(1000);
223
-        continue;
224
-      } else {
225
-        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
226
-        var exceptionFilePath = ISERunDir + "/exception.log";
227
-        if (!ISEFileSys.FileExists(exceptionFilePath)) {
228
-          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
229
-          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
230
-          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
231
-          exceptionFile.WriteLine("\tException name: " + exception.name);
232
-          exceptionFile.WriteLine("\tException error code: " + error_code);
233
-          exceptionFile.WriteLine("\tException message: " + exception.message);
234
-          exceptionFile.Close();
235
-        }
236
-        throw exception;
237
-      }
238
-    }
239
-  }
240
-  // If we reached this point, we failed to open the file after 10 attempts.
241
-  // We need to error out.
242
-  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
243
-  WScript.Quit(1);
244
-}

+ 0
- 63
proj/GPIO.runs/synth_1/ISEWrap.sh View File

1
-#!/bin/sh
2
-
3
-#
4
-#  Vivado(TM)
5
-#  ISEWrap.sh: Vivado Runs Script for UNIX
6
-#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
7
-#
8
-
9
-HD_LOG=$1
10
-shift
11
-
12
-# CHECK for a STOP FILE
13
-if [ -f .stop.rst ]
14
-then
15
-echo ""                                        >> $HD_LOG
16
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
17
-echo ""                                        >> $HD_LOG
18
-exit 1
19
-fi
20
-
21
-ISE_STEP=$1
22
-shift
23
-
24
-# WRITE STEP HEADER to LOG
25
-echo ""                      >> $HD_LOG
26
-echo "*** Running $ISE_STEP" >> $HD_LOG
27
-echo "    with args $@"      >> $HD_LOG
28
-echo ""                      >> $HD_LOG
29
-
30
-# LAUNCH!
31
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
32
-
33
-# BEGIN file creation
34
-ISE_PID=$!
35
-if [ X != X$HOSTNAME ]
36
-then
37
-ISE_HOST=$HOSTNAME #bash
38
-else
39
-ISE_HOST=$HOST     #csh
40
-fi
41
-ISE_USER=$USER
42
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
43
-/bin/touch $ISE_BEGINFILE
44
-echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
45
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
46
-echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
47
-echo "    </Process>"                                                                              >> $ISE_BEGINFILE
48
-echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
49
-
50
-# WAIT for ISEStep to finish
51
-wait $ISE_PID
52
-
53
-# END/ERROR file creation
54
-RETVAL=$?
55
-if [ $RETVAL -eq 0 ]
56
-then
57
-    /bin/touch .$ISE_STEP.end.rst
58
-else
59
-    /bin/touch .$ISE_STEP.error.rst
60
-fi
61
-
62
-exit $RETVAL
63
-

+ 0
- 95
proj/GPIO.runs/synth_1/gen_run.xml View File

1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1618002642">
3
-  <File Type="RDS-PROPCONSTRS" Name="GPIO_demo_drc_synth.rpt"/>
4
-  <File Type="PA-TCL" Name="GPIO_demo.tcl"/>
5
-  <File Type="RDS-RDS" Name="GPIO_demo.vds"/>
6
-  <File Type="RDS-UTIL" Name="GPIO_demo_utilization_synth.rpt"/>
7
-  <File Type="RDS-UTIL-PB" Name="GPIO_demo_utilization_synth.pb"/>
8
-  <File Type="RDS-DCP" Name="GPIO_demo.dcp"/>
9
-  <File Type="VDS-TIMINGSUMMARY" Name="GPIO_demo_timing_summary_synth.rpt"/>
10
-  <File Type="VDS-TIMING-PB" Name="GPIO_demo_timing_summary_synth.pb"/>
11
-  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
12
-    <Filter Type="Srcs"/>
13
-    <File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
14
-      <FileInfo>
15
-        <Attr Name="UsedIn" Val="synthesis"/>
16
-        <Attr Name="UsedIn" Val="simulation"/>
17
-      </FileInfo>
18
-    </File>
19
-    <File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
20
-      <FileInfo>
21
-        <Attr Name="UsedIn" Val="synthesis"/>
22
-        <Attr Name="UsedIn" Val="simulation"/>
23
-      </FileInfo>
24
-    </File>
25
-    <File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
26
-      <FileInfo>
27
-        <Attr Name="UsedIn" Val="synthesis"/>
28
-        <Attr Name="UsedIn" Val="simulation"/>
29
-      </FileInfo>
30
-    </File>
31
-    <File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
32
-      <FileInfo>
33
-        <Attr Name="UsedIn" Val="synthesis"/>
34
-        <Attr Name="UsedIn" Val="simulation"/>
35
-      </FileInfo>
36
-    </File>
37
-    <File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
38
-      <FileInfo>
39
-        <Attr Name="UsedIn" Val="synthesis"/>
40
-        <Attr Name="UsedIn" Val="simulation"/>
41
-      </FileInfo>
42
-    </File>
43
-    <File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
44
-      <FileInfo>
45
-        <Attr Name="UsedIn" Val="synthesis"/>
46
-        <Attr Name="UsedIn" Val="simulation"/>
47
-      </FileInfo>
48
-    </File>
49
-    <File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
50
-      <FileInfo>
51
-        <Attr Name="UsedIn" Val="synthesis"/>
52
-        <Attr Name="UsedIn" Val="simulation"/>
53
-      </FileInfo>
54
-    </File>
55
-    <File Path="$PPRDIR/../src/hdl/debouncer.vhd">
56
-      <FileInfo>
57
-        <Attr Name="UsedIn" Val="synthesis"/>
58
-        <Attr Name="UsedIn" Val="simulation"/>
59
-      </FileInfo>
60
-    </File>
61
-    <File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
62
-      <FileInfo>
63
-        <Attr Name="UsedIn" Val="synthesis"/>
64
-        <Attr Name="UsedIn" Val="simulation"/>
65
-      </FileInfo>
66
-    </File>
67
-    <Config>
68
-      <Option Name="DesignMode" Val="RTL"/>
69
-      <Option Name="TopModule" Val="GPIO_demo"/>
70
-      <Option Name="TopAutoSet" Val="TRUE"/>
71
-    </Config>
72
-  </FileSet>
73
-  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
74
-    <Filter Type="Constrs"/>
75
-    <File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
76
-      <FileInfo>
77
-        <Attr Name="UsedIn" Val="synthesis"/>
78
-        <Attr Name="UsedIn" Val="implementation"/>
79
-      </FileInfo>
80
-    </File>
81
-    <Config>
82
-      <Option Name="ConstrsType" Val="XDC"/>
83
-    </Config>
84
-  </FileSet>
85
-  <Strategy Version="1" Minor="2">
86
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015">
87
-      <Desc>Vivado Synthesis Defaults</Desc>
88
-    </StratHandle>
89
-    <Step Id="synth_design">
90
-      <Option Id="FlattenHierarchy">1</Option>
91
-      <Option Id="Directive">0</Option>
92
-      <Option Id="FsmExtraction">0</Option>
93
-    </Step>
94
-  </Strategy>
95
-</GenRun>

+ 0
- 9
proj/GPIO.runs/synth_1/htr.txt View File

1
-REM
2
-REM Vivado(TM)
3
-REM htr.txt: a Vivado-generated description of how-to-repeat the
4
-REM          the basic steps of a run.  Note that runme.bat/sh needs
5
-REM          to be invoked for Vivado to track run status.
6
-REM Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
7
-REM
8
-
9
-vivado -log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl

+ 0
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proj/GPIO.runs/synth_1/project.wdf View File

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-version:1
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
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-5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3031333866366637386234623465663361303338333762383461653364333333:506172656e742050412070726f6a656374204944:00
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-eof:1785114370

+ 0
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proj/GPIO.runs/synth_1/rundef.js View File

1
-//
2
-// Vivado(TM)
3
-// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
4
-// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
5
-//
6
-
7
-var WshShell = new ActiveXObject( "WScript.Shell" );
8
-var ProcEnv = WshShell.Environment( "Process" );
9
-var PathVal = ProcEnv("PATH");
10
-if ( PathVal.length == 0 ) {
11
-  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;";
12
-} else {
13
-  PathVal = "C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2016.4/bin;" + PathVal;
14
-}
15
-
16
-ProcEnv("PATH") = PathVal;
17
-
18
-var RDScrFP = WScript.ScriptFullName;
19
-var RDScrN = WScript.ScriptName;
20
-var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
21
-var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
22
-eval( EAInclude(ISEJScriptLib) );
23
-
24
-
25
-ISEStep( "vivado",
26
-         "-log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl" );
27
-
28
-
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-
30
-function EAInclude( EAInclFilename ) {
31
-  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
32
-  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
33
-  var EAIFContents = EAInclFile.ReadAll();
34
-  EAInclFile.Close();
35
-  return EAIFContents;
36
-}

+ 0
- 10
proj/GPIO.runs/synth_1/runme.bat View File

1
-@echo off
2
-
3
-rem  Vivado (TM)
4
-rem  runme.bat: a Vivado-generated Script
5
-rem  Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
6
-
7
-
8
-set HD_SDIR=%~dp0
9
-cd /d "%HD_SDIR%"
10
-cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

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- 802
proj/GPIO.runs/synth_1/runme.log View File

1
-
2
-*** Running vivado
3
-    with args -log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
4
-
5
-
6
-****** Vivado v2016.4 (64-bit)
7
-  **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
8
-  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
9
-    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
10
-
11
-source GPIO_demo.tcl -notrace
12
-Command: synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy none -directive RuntimeOptimized -fsm_extraction off
13
-Starting synth_design
14
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
15
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
16
-INFO: Launching helper process for spawning children vivado processes
17
-INFO: Helper process launched with PID 3172 
18
----------------------------------------------------------------------------------
19
-Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 350.121 ; gain = 140.289
20
----------------------------------------------------------------------------------
21
-INFO: [Synth 8-638] synthesizing module 'GPIO_demo' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
22
-	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
23
-	Parameter PORT_WIDTH bound to: 5 - type: integer 
24
-INFO: [Synth 8-3491] module 'debouncer' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:42' bound to instance 'Inst_btn_debounce' of component 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:320]
25
-INFO: [Synth 8-638] synthesizing module 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
26
-	Parameter DEBNC_CLOCKS bound to: 65536 - type: integer 
27
-	Parameter PORT_WIDTH bound to: 5 - type: integer 
28
-INFO: [Synth 8-256] done synthesizing module 'debouncer' (1#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50]
29
-INFO: [Synth 8-3491] module 'UART_TX_CTRL' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:42' bound to instance 'Inst_UART_TX_CTRL' of component 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:450]
30
-INFO: [Synth 8-638] synthesizing module 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
31
-INFO: [Synth 8-256] done synthesizing module 'UART_TX_CTRL' (2#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50]
32
-INFO: [Synth 8-3491] module 'vga_ctrl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:38' bound to instance 'Inst_vga_ctrl' of component 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:465]
33
-INFO: [Synth 8-638] synthesizing module 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
34
-INFO: [Synth 8-3491] module 'clk_wiz_0' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:74' bound to instance 'clk_wiz_0_inst' of component 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:197]
35
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
36
-INFO: [Synth 8-3491] module 'clk_wiz_0_clk_wiz' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:74' bound to instance 'U0' of component 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:98]
37
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
38
-	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
39
-	Parameter CLKFBOUT_MULT_F bound to: 10.125000 - type: float 
40
-	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
41
-	Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 
42
-	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
43
-	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
44
-	Parameter CLKOUT0_DIVIDE_F bound to: 9.375000 - type: float 
45
-	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
46
-	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
47
-	Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 
48
-	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
49
-	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
50
-	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
51
-	Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 
52
-	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
53
-	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
54
-	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
55
-	Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 
56
-	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
57
-	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
58
-	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
59
-	Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 
60
-	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
61
-	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
62
-	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
63
-	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
64
-	Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 
65
-	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
66
-	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
67
-	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
68
-	Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 
69
-	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
70
-	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
71
-	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
72
-	Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 
73
-	Parameter COMPENSATION bound to: ZHOLD - type: string 
74
-	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
75
-	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
76
-	Parameter IS_PSEN_INVERTED bound to: 1'b0 
77
-	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
78
-	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
79
-	Parameter IS_RST_INVERTED bound to: 1'b0 
80
-	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
81
-	Parameter REF_JITTER2 bound to: 0.000000 - type: float 
82
-	Parameter SS_EN bound to: FALSE - type: string 
83
-	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
84
-	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
85
-	Parameter STARTUP_WAIT bound to: 0 - type: bool 
86
-INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:125]
87
-INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:187]
88
-INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:194]
89
-INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (3#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83]
90
-INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (4#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83]
91
-	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
92
-	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
93
-	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
94
-INFO: [Synth 8-3491] module 'MouseCtl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:179' bound to instance 'Inst_MouseCtl' of component 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:207]
95
-INFO: [Synth 8-638] synthesizing module 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
96
-	Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer 
97
-	Parameter CHECK_PERIOD_MS bound to: 500 - type: integer 
98
-	Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer 
99
-INFO: [Synth 8-3491] module 'Ps2Interface' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:152' bound to instance 'Inst_Ps2Interface' of component 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:370]
100
-INFO: [Synth 8-638] synthesizing module 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
101
-INFO: [Synth 8-256] done synthesizing module 'Ps2Interface' (5#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180]
102
-INFO: [Synth 8-256] done synthesizing module 'MouseCtl' (6#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208]
103
-INFO: [Synth 8-3491] module 'MouseDisplay' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:99' bound to instance 'Inst_MouseDisplay' of component 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:334]
104
-INFO: [Synth 8-638] synthesizing module 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
105
-WARNING: [Synth 8-614] signal 'ypos' is read in the process but is not in the sensitivity list [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:197]
106
-INFO: [Synth 8-256] done synthesizing module 'MouseDisplay' (7#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129]
107
-INFO: [Synth 8-256] done synthesizing module 'vga_ctrl' (8#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50]
108
-INFO: [Synth 8-256] done synthesizing module 'GPIO_demo' (9#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70]
109
----------------------------------------------------------------------------------
110
-Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 391.957 ; gain = 182.125
111
----------------------------------------------------------------------------------
112
-
113
-Report Check Netlist: 
114
-+------+------------------+-------+---------+-------+------------------+
115
-|      |Item              |Errors |Warnings |Status |Description       |
116
-+------+------------------+-------+---------+-------+------------------+
117
-|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
118
-+------+------------------+-------+---------+-------+------------------+
119
----------------------------------------------------------------------------------
120
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 391.957 ; gain = 182.125
121
----------------------------------------------------------------------------------
122
-INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
123
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
124
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
125
-INFO: [Project 1-570] Preparing netlist for logic optimization
126
-
127
-Processing XDC Constraints
128
-Initializing timing engine
129
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
130
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
131
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/GPIO_demo_propImpl.xdc].
132
-Resolution: To avoid this warning, move constraints listed in [.Xil/GPIO_demo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
133
-INFO: [Timing 38-2] Deriving generated clocks
134
-Completed Processing XDC Constraints
135
-
136
-INFO: [Project 1-111] Unisim Transformation Summary:
137
-No Unisim elements were transformed.
138
-
139
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 692.656 ; gain = 0.000
140
----------------------------------------------------------------------------------
141
-Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
142
----------------------------------------------------------------------------------
143
----------------------------------------------------------------------------------
144
-Start Loading Part and Timing Information
145
----------------------------------------------------------------------------------
146
-Loading part: xc7a35tcpg236-1
147
----------------------------------------------------------------------------------
148
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
149
----------------------------------------------------------------------------------
150
----------------------------------------------------------------------------------
151
-Start Applying 'set_property' XDC Constraints
152
----------------------------------------------------------------------------------
153
----------------------------------------------------------------------------------
154
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824
155
----------------------------------------------------------------------------------
156
-INFO: [Synth 8-5544] ROM "READY" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
157
-INFO: [Synth 8-5545] ROM "txState" won't be mapped to RAM because address size (31) is larger than maximum supported(25)
158
-INFO: [Synth 8-5544] ROM "bitIndex" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
159
-INFO: [Synth 8-5546] ROM "busy" won't be mapped to RAM because it is too sparse
160
-INFO: [Synth 8-5546] ROM "delay_100us_counter_enable" won't be mapped to RAM because it is too sparse
161
-INFO: [Synth 8-5546] ROM "delay_20us_counter_enable" won't be mapped to RAM because it is too sparse
162
-INFO: [Synth 8-5546] ROM "delay_63clk_counter_enable" won't be mapped to RAM because it is too sparse
163
-INFO: [Synth 8-5546] ROM "reset_bit_count" won't be mapped to RAM because it is too sparse
164
-INFO: [Synth 8-5545] ROM "periodic_check_tick" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
165
-INFO: [Synth 8-5546] ROM "timeout" won't be mapped to RAM because it is too sparse
166
-INFO: [Synth 8-4471] merging register 'green_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:238]
167
-INFO: [Synth 8-4471] merging register 'blue_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:239]
168
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
169
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
170
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
171
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
172
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213]
173
-INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214]
174
-INFO: [Synth 8-4471] merging register 'sendStr_reg[15][7:0]' into 'sendStr_reg[3][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
175
-INFO: [Synth 8-4471] merging register 'sendStr_reg[25][7:0]' into 'sendStr_reg[24][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414]
176
-INFO: [Synth 8-5544] ROM "sendStr[0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
177
-INFO: [Synth 8-5544] ROM "sendStr[1]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
178
-INFO: [Synth 8-5544] ROM "sendStr[2]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
179
-INFO: [Synth 8-5544] ROM "sendStr[3]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
180
-INFO: [Synth 8-5544] ROM "sendStr[4]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
181
-INFO: [Synth 8-5544] ROM "sendStr[5]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
182
-INFO: [Synth 8-5544] ROM "sendStr[6]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
183
-INFO: [Synth 8-5544] ROM "sendStr[7]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
184
-INFO: [Synth 8-5544] ROM "sendStr[8]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
185
-INFO: [Synth 8-5544] ROM "sendStr[9]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
186
-INFO: [Synth 8-5544] ROM "sendStr[10]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
187
-INFO: [Synth 8-5544] ROM "sendStr[11]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
188
-INFO: [Synth 8-5544] ROM "sendStr[12]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
189
-INFO: [Synth 8-5544] ROM "sendStr[13]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
190
-INFO: [Synth 8-5544] ROM "sendStr[14]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
191
-INFO: [Synth 8-5544] ROM "sendStr[18]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
192
-INFO: [Synth 8-5544] ROM "sendStr[19]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
193
-INFO: [Synth 8-5544] ROM "sendStr[21]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
194
-INFO: [Synth 8-5544] ROM "sendStr[22]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
195
-INFO: [Synth 8-5544] ROM "sendStr[23]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
196
-INFO: [Synth 8-5544] ROM "sendStr[24]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
197
-INFO: [Synth 8-5544] ROM "strEnd" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
198
-INFO: [Synth 8-5544] ROM "strIndex" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
199
----------------------------------------------------------------------------------
200
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 692.656 ; gain = 482.824
201
----------------------------------------------------------------------------------
202
-
203
-Report RTL Partitions: 
204
-+-+--------------+------------+----------+
205
-| |RTL Partition |Replication |Instances |
206
-+-+--------------+------------+----------+
207
-+-+--------------+------------+----------+
208
----------------------------------------------------------------------------------
209
-Start RTL Component Statistics 
210
----------------------------------------------------------------------------------
211
-Detailed RTL Component Info : 
212
-+---Adders : 
213
-	   2 Input     26 Bit       Adders := 1     
214
-	   2 Input     24 Bit       Adders := 1     
215
-	   3 Input     13 Bit       Adders := 2     
216
-	   2 Input     12 Bit       Adders := 7     
217
-	   2 Input     11 Bit       Adders := 1     
218
-	   2 Input      8 Bit       Adders := 1     
219
-	   4 Input      8 Bit       Adders := 1     
220
-	   3 Input      8 Bit       Adders := 2     
221
-	   2 Input      7 Bit       Adders := 1     
222
-	   2 Input      4 Bit       Adders := 4     
223
-	   3 Input      4 Bit       Adders := 2     
224
-+---XORs : 
225
-	   2 Input      1 Bit         XORs := 5     
226
-+---Registers : 
227
-	               31 Bit    Registers := 1     
228
-	               26 Bit    Registers := 1     
229
-	               24 Bit    Registers := 1     
230
-	               12 Bit    Registers := 10    
231
-	               11 Bit    Registers := 2     
232
-	               10 Bit    Registers := 1     
233
-	                8 Bit    Registers := 30    
234
-	                7 Bit    Registers := 1     
235
-	                6 Bit    Registers := 1     
236
-	                5 Bit    Registers := 2     
237
-	                4 Bit    Registers := 16    
238
-	                3 Bit    Registers := 1     
239
-	                2 Bit    Registers := 2     
240
-	                1 Bit    Registers := 42    
241
-+---Muxes : 
242
-	   3 Input     31 Bit        Muxes := 1     
243
-	   2 Input     26 Bit        Muxes := 1     
244
-	   2 Input     24 Bit        Muxes := 1     
245
-	   2 Input     16 Bit        Muxes := 1     
246
-	   2 Input     12 Bit        Muxes := 10    
247
-	   2 Input     11 Bit        Muxes := 1     
248
-	   2 Input      9 Bit        Muxes := 2     
249
-	  38 Input      8 Bit        Muxes := 1     
250
-	   3 Input      8 Bit        Muxes := 20    
251
-	   2 Input      7 Bit        Muxes := 10    
252
-	   3 Input      6 Bit        Muxes := 2     
253
-	   2 Input      6 Bit        Muxes := 13    
254
-	   4 Input      6 Bit        Muxes := 2     
255
-	   5 Input      6 Bit        Muxes := 1     
256
-	   3 Input      5 Bit        Muxes := 2     
257
-	   2 Input      5 Bit        Muxes := 4     
258
-	   4 Input      5 Bit        Muxes := 6     
259
-	   5 Input      5 Bit        Muxes := 1     
260
-	   2 Input      4 Bit        Muxes := 9     
261
-	   3 Input      4 Bit        Muxes := 3     
262
-	   4 Input      4 Bit        Muxes := 3     
263
-	   3 Input      3 Bit        Muxes := 3     
264
-	   4 Input      3 Bit        Muxes := 1     
265
-	   2 Input      3 Bit        Muxes := 1     
266
-	   9 Input      3 Bit        Muxes := 1     
267
-	   4 Input      2 Bit        Muxes := 1     
268
-	   2 Input      2 Bit        Muxes := 4     
269
-	  18 Input      2 Bit        Muxes := 1     
270
-	   3 Input      2 Bit        Muxes := 2     
271
-	  38 Input      2 Bit        Muxes := 6     
272
-	   2 Input      1 Bit        Muxes := 24    
273
-	   4 Input      1 Bit        Muxes := 2     
274
-	  18 Input      1 Bit        Muxes := 5     
275
-	  38 Input      1 Bit        Muxes := 5     
276
-	   3 Input      1 Bit        Muxes := 6     
277
-	   8 Input      1 Bit        Muxes := 1     
278
----------------------------------------------------------------------------------
279
-Finished RTL Component Statistics 
280
----------------------------------------------------------------------------------
281
----------------------------------------------------------------------------------
282
-Start RTL Hierarchical Component Statistics 
283
----------------------------------------------------------------------------------
284
-Hierarchical RTL Component report 
285
-Module GPIO_demo 
286
-Detailed RTL Component Info : 
287
-+---Adders : 
288
-	   2 Input      4 Bit       Adders := 1     
289
-+---Registers : 
290
-	               31 Bit    Registers := 1     
291
-	                8 Bit    Registers := 26    
292
-	                4 Bit    Registers := 2     
293
-	                3 Bit    Registers := 1     
294
-	                1 Bit    Registers := 1     
295
-+---Muxes : 
296
-	   3 Input     31 Bit        Muxes := 1     
297
-	   2 Input     16 Bit        Muxes := 1     
298
-	   3 Input      8 Bit        Muxes := 20    
299
-	   2 Input      7 Bit        Muxes := 10    
300
-	   2 Input      6 Bit        Muxes := 10    
301
-	   2 Input      4 Bit        Muxes := 1     
302
-	   9 Input      3 Bit        Muxes := 1     
303
-	   2 Input      2 Bit        Muxes := 1     
304
-	   2 Input      1 Bit        Muxes := 3     
305
-	   8 Input      1 Bit        Muxes := 1     
306
-Module debouncer 
307
-Detailed RTL Component Info : 
308
-+---XORs : 
309
-	   2 Input      1 Bit         XORs := 5     
310
-+---Registers : 
311
-	                5 Bit    Registers := 1     
312
-+---Muxes : 
313
-	   2 Input      1 Bit        Muxes := 5     
314
-Module UART_TX_CTRL 
315
-Detailed RTL Component Info : 
316
-+---Registers : 
317
-	               10 Bit    Registers := 1     
318
-	                2 Bit    Registers := 1     
319
-	                1 Bit    Registers := 1     
320
-+---Muxes : 
321
-	   4 Input      2 Bit        Muxes := 1     
322
-	   2 Input      1 Bit        Muxes := 4     
323
-	   4 Input      1 Bit        Muxes := 1     
324
-Module Ps2Interface 
325
-Detailed RTL Component Info : 
326
-+---Adders : 
327
-	   2 Input     11 Bit       Adders := 1     
328
-	   2 Input      7 Bit       Adders := 1     
329
-	   2 Input      4 Bit       Adders := 3     
330
-+---Registers : 
331
-	               11 Bit    Registers := 2     
332
-	                8 Bit    Registers := 1     
333
-	                7 Bit    Registers := 1     
334
-	                5 Bit    Registers := 1     
335
-	                4 Bit    Registers := 3     
336
-	                1 Bit    Registers := 17    
337
-+---Muxes : 
338
-	   2 Input     11 Bit        Muxes := 1     
339
-	   3 Input      5 Bit        Muxes := 1     
340
-	   2 Input      5 Bit        Muxes := 1     
341
-	   2 Input      4 Bit        Muxes := 4     
342
-	   3 Input      4 Bit        Muxes := 2     
343
-	   3 Input      3 Bit        Muxes := 2     
344
-	   2 Input      2 Bit        Muxes := 2     
345
-	  18 Input      2 Bit        Muxes := 1     
346
-	  18 Input      1 Bit        Muxes := 5     
347
-	   2 Input      1 Bit        Muxes := 7     
348
-	   4 Input      1 Bit        Muxes := 1     
349
-Module MouseCtl 
350
-Detailed RTL Component Info : 
351
-+---Adders : 
352
-	   2 Input     26 Bit       Adders := 1     
353
-	   2 Input     24 Bit       Adders := 1     
354
-	   2 Input     12 Bit       Adders := 4     
355
-	   2 Input      8 Bit       Adders := 1     
356
-+---Registers : 
357
-	               26 Bit    Registers := 1     
358
-	               24 Bit    Registers := 1     
359
-	               12 Bit    Registers := 6     
360
-	                8 Bit    Registers := 3     
361
-	                6 Bit    Registers := 1     
362
-	                4 Bit    Registers := 1     
363
-	                1 Bit    Registers := 17    
364
-+---Muxes : 
365
-	   2 Input     26 Bit        Muxes := 1     
366
-	   2 Input     24 Bit        Muxes := 1     
367
-	   2 Input     12 Bit        Muxes := 10    
368
-	   2 Input      9 Bit        Muxes := 2     
369
-	  38 Input      8 Bit        Muxes := 1     
370
-	   3 Input      6 Bit        Muxes := 2     
371
-	   2 Input      6 Bit        Muxes := 3     
372
-	   4 Input      6 Bit        Muxes := 2     
373
-	   5 Input      6 Bit        Muxes := 1     
374
-	   3 Input      5 Bit        Muxes := 1     
375
-	   4 Input      5 Bit        Muxes := 6     
376
-	   5 Input      5 Bit        Muxes := 1     
377
-	   2 Input      5 Bit        Muxes := 3     
378
-	   3 Input      4 Bit        Muxes := 1     
379
-	   4 Input      4 Bit        Muxes := 3     
380
-	   2 Input      4 Bit        Muxes := 1     
381
-	   3 Input      3 Bit        Muxes := 1     
382
-	   4 Input      3 Bit        Muxes := 1     
383
-	   2 Input      3 Bit        Muxes := 1     
384
-	   3 Input      2 Bit        Muxes := 2     
385
-	   2 Input      2 Bit        Muxes := 1     
386
-	  38 Input      2 Bit        Muxes := 6     
387
-	  38 Input      1 Bit        Muxes := 5     
388
-	   2 Input      1 Bit        Muxes := 5     
389
-	   3 Input      1 Bit        Muxes := 6     
390
-Module MouseDisplay 
391
-Detailed RTL Component Info : 
392
-+---Adders : 
393
-	   3 Input     13 Bit       Adders := 2     
394
-	   2 Input     12 Bit       Adders := 3     
395
-	   3 Input      4 Bit       Adders := 2     
396
-+---Registers : 
397
-	                4 Bit    Registers := 1     
398
-	                2 Bit    Registers := 1     
399
-	                1 Bit    Registers := 1     
400
-Module vga_ctrl 
401
-Detailed RTL Component Info : 
402
-+---Adders : 
403
-	   4 Input      8 Bit       Adders := 1     
404
-	   3 Input      8 Bit       Adders := 2     
405
-+---Registers : 
406
-	               12 Bit    Registers := 4     
407
-	                4 Bit    Registers := 9     
408
-	                1 Bit    Registers := 5     
409
-+---Muxes : 
410
-	   2 Input      4 Bit        Muxes := 3     
411
----------------------------------------------------------------------------------
412
-Finished RTL Hierarchical Component Statistics
413
----------------------------------------------------------------------------------
414
----------------------------------------------------------------------------------
415
-Start Part Resource Summary
416
----------------------------------------------------------------------------------
417
-Part Resources:
418
-DSPs: 90 (col length:60)
419
-BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
420
----------------------------------------------------------------------------------
421
-Finished Part Resource Summary
422
----------------------------------------------------------------------------------
423
----------------------------------------------------------------------------------
424
-Start Cross Boundary and Area Optimization
425
----------------------------------------------------------------------------------
426
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
427
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
428
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
429
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
430
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
431
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
432
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
433
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
434
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[8]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
435
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[9]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
436
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[10]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
437
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[11]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
438
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
439
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
440
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
441
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
442
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
443
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
444
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
445
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
446
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[8]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]'
447
-INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[10]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]'
448
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_vga_ctrl/Inst_MouseCtl/\y_max_reg[11] )
449
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[0]' (FDSE) to 'strEnd_reg[1]'
450
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[2]' (FDRE) to 'strEnd_reg[5]'
451
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[3]' (FDSE) to 'strEnd_reg[4]'
452
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\strEnd_reg[4] )
453
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[5]' (FDRE) to 'strEnd_reg[6]'
454
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[6]' (FDRE) to 'strEnd_reg[7]'
455
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[7]' (FDRE) to 'strEnd_reg[8]'
456
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[8]' (FDRE) to 'strEnd_reg[9]'
457
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[9]' (FDRE) to 'strEnd_reg[10]'
458
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[10]' (FDRE) to 'strEnd_reg[11]'
459
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[11]' (FDRE) to 'strEnd_reg[12]'
460
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[12]' (FDRE) to 'strEnd_reg[13]'
461
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[13]' (FDRE) to 'strEnd_reg[14]'
462
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[14]' (FDRE) to 'strEnd_reg[15]'
463
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[15]' (FDRE) to 'strEnd_reg[16]'
464
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[16]' (FDRE) to 'strEnd_reg[17]'
465
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[17]' (FDRE) to 'strEnd_reg[18]'
466
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[18]' (FDRE) to 'strEnd_reg[19]'
467
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[19]' (FDRE) to 'strEnd_reg[20]'
468
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[20]' (FDRE) to 'strEnd_reg[21]'
469
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[21]' (FDRE) to 'strEnd_reg[22]'
470
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[22]' (FDRE) to 'strEnd_reg[23]'
471
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[23]' (FDRE) to 'strEnd_reg[24]'
472
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[24]' (FDRE) to 'strEnd_reg[25]'
473
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[25]' (FDRE) to 'strEnd_reg[26]'
474
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[26]' (FDRE) to 'strEnd_reg[27]'
475
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[27]' (FDRE) to 'strEnd_reg[28]'
476
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[28]' (FDRE) to 'strEnd_reg[29]'
477
-INFO: [Synth 8-3886] merging instance 'strEnd_reg[29]' (FDRE) to 'strEnd_reg[30]'
478
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\strEnd_reg[30] )
479
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][7]' (FDRE) to 'sendStr_reg[26][1]'
480
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][7]' (FDRE) to 'sendStr_reg[26][1]'
481
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][7]' (FDRE) to 'sendStr_reg[23][6]'
482
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][7]' (FDRE) to 'sendStr_reg[22][5]'
483
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][7]' (FDRE) to 'sendStr_reg[21][4]'
484
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][7]' (FDRE) to 'sendStr_reg[19][7]'
485
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][7]' (FDRE) to 'sendStr_reg[19][4]'
486
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][7]' (FDRE) to 'sendStr_reg[18][3]'
487
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][7]' (FDRE) to 'sendStr_reg[5][7]'
488
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][7]' (FDRE) to 'sendStr_reg[5][7]'
489
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][7]' (FDRE) to 'sendStr_reg[14][3]'
490
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[13][7]' (FDRE) to 'sendStr_reg[13][4]'
491
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][7]' (FDRE) to 'sendStr_reg[12][4]'
492
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][7]' (FDRE) to 'sendStr_reg[11][2]'
493
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][7]' (FDRE) to 'sendStr_reg[10][3]'
494
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][7]' (FDRE) to 'sendStr_reg[9][4]'
495
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][7]' (FDRE) to 'sendStr_reg[8][3]'
496
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[7][7]' (FDRE) to 'sendStr_reg[7][3]'
497
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][7]' (FDRE) to 'sendStr_reg[6][3]'
498
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][7]' (FDRE) to 'sendStr_reg[17][3]'
499
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[4][7] )
500
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[3][7]' (FDRE) to 'sendStr_reg[3][3]'
501
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[2][7]' (FDRE) to 'sendStr_reg[2][3]'
502
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][7]' (FDRE) to 'sendStr_reg[1][1]'
503
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[0][7]' (FDRE) to 'sendStr_reg[0][5]'
504
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][6]' (FDRE) to 'sendStr_reg[26][1]'
505
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][6]' (FDRE) to 'sendStr_reg[26][1]'
506
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][6]' (FDRE) to 'sendStr_reg[23][4]'
507
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][6]' (FDSE) to 'sendStr_reg[22][2]'
508
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][6]' (FDSE) to 'sendStr_reg[21][3]'
509
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][6]' (FDSE) to 'sendStr_reg[19][6]'
510
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][6]' (FDSE) to 'sendStr_reg[19][2]'
511
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][6]' (FDRE) to 'sendStr_reg[18][4]'
512
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][6]' (FDSE) to 'sendStr_reg[5][6]'
513
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][6]' (FDSE) to 'sendStr_reg[5][6]'
514
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][6]' (FDSE) to 'sendStr_reg[14][2]'
515
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][6]' (FDSE) to 'sendStr_reg[12][3]'
516
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][6]' (FDSE) to 'sendStr_reg[11][0]'
517
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][6]' (FDSE) to 'sendStr_reg[10][4]'
518
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][6]' (FDSE) to 'sendStr_reg[9][2]'
519
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][6]' (FDRE) to 'sendStr_reg[8][4]'
520
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][6]' (FDSE) to 'sendStr_reg[6][4]'
521
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][6]' (FDSE) to 'sendStr_reg[5][3]'
522
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[4][6]' (FDSE) to 'sendStr_reg[4][1]'
523
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[3][6] )
524
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[2][6] )
525
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][6]' (FDRE) to 'sendStr_reg[1][5]'
526
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][5]' (FDRE) to 'sendStr_reg[26][1]'
527
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][5]' (FDRE) to 'sendStr_reg[26][1]'
528
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][5]' (FDRE) to 'sendStr_reg[22][4]'
529
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][5]' (FDRE) to 'sendStr_reg[19][5]'
530
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][5]' (FDRE) to 'sendStr_reg[19][0]'
531
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[18][5] )
532
-INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][5]' (FDRE) to 'sendStr_reg[5][5]'
533
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
534
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[8][5] )
535
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[22][4] )
536
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[13][4] )
537
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[12][4] )
538
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[10][4] )
539
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[7][4] )
540
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[16][3] )
541
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[9][3] )
542
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[5][3] )
543
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[19][2] )
544
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[13][2] )
545
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[11][2] )
546
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[10][2] )
547
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[7][2] )
548
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[6][2] )
549
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[23][1] )
550
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[22][1] )
551
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[21][1] )
552
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[19][1] )
553
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[14][1] )
554
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[3][1] )
555
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[1][1] )
556
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[0][1] )
557
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[26][0] )
558
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[24][0] )
559
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[23][0] )
560
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[21][0] )
561
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[18][0] )
562
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[14][0] )
563
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[11][0] )
564
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[9][0] )
565
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[8][0] )
566
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[4][0] )
567
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[2][0] )
568
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[1][0] )
569
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[0][0] )
570
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (Inst_UART_TX_CTRL/\txData_reg[9] )
571
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[0] )
572
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uartData_reg[7] )
573
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[8] )
574
-WARNING: [Synth 8-3332] Sequential element (txData_reg[9]) is unused and will be removed from module UART_TX_CTRL.
575
-WARNING: [Synth 8-3332] Sequential element (txData_reg[8]) is unused and will be removed from module UART_TX_CTRL.
576
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[3]) is unused and will be removed from module MouseCtl.
577
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[2]) is unused and will be removed from module MouseCtl.
578
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[1]) is unused and will be removed from module MouseCtl.
579
-WARNING: [Synth 8-3332] Sequential element (zpos_reg[0]) is unused and will be removed from module MouseCtl.
580
-WARNING: [Synth 8-3332] Sequential element (left_down_reg) is unused and will be removed from module MouseCtl.
581
-WARNING: [Synth 8-3332] Sequential element (left_reg) is unused and will be removed from module MouseCtl.
582
-WARNING: [Synth 8-3332] Sequential element (middle_down_reg) is unused and will be removed from module MouseCtl.
583
-WARNING: [Synth 8-3332] Sequential element (middle_reg) is unused and will be removed from module MouseCtl.
584
-WARNING: [Synth 8-3332] Sequential element (right_down_reg) is unused and will be removed from module MouseCtl.
585
-WARNING: [Synth 8-3332] Sequential element (right_reg) is unused and will be removed from module MouseCtl.
586
-WARNING: [Synth 8-3332] Sequential element (new_event_reg) is unused and will be removed from module MouseCtl.
587
-WARNING: [Synth 8-3332] Sequential element (y_max_reg[11]) is unused and will be removed from module MouseCtl.
588
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[9]) is unused and will be removed from module vga_ctrl.
589
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[8]) is unused and will be removed from module vga_ctrl.
590
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
591
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
592
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
593
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
594
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
595
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
596
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
597
-WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
598
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl.
599
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl.
600
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl.
601
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl.
602
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl.
603
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl.
604
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl.
605
-WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl.
606
-WARNING: [Synth 8-3332] Sequential element (strEnd_reg[30]) is unused and will be removed from module GPIO_demo.
607
-WARNING: [Synth 8-3332] Sequential element (strEnd_reg[4]) is unused and will be removed from module GPIO_demo.
608
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][1]) is unused and will be removed from module GPIO_demo.
609
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][0]) is unused and will be removed from module GPIO_demo.
610
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][1]) is unused and will be removed from module GPIO_demo.
611
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][0]) is unused and will be removed from module GPIO_demo.
612
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][6]) is unused and will be removed from module GPIO_demo.
613
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][0]) is unused and will be removed from module GPIO_demo.
614
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][6]) is unused and will be removed from module GPIO_demo.
615
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][1]) is unused and will be removed from module GPIO_demo.
616
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][7]) is unused and will be removed from module GPIO_demo.
617
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][0]) is unused and will be removed from module GPIO_demo.
618
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[6][2]) is unused and will be removed from module GPIO_demo.
619
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][4]) is unused and will be removed from module GPIO_demo.
620
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][2]) is unused and will be removed from module GPIO_demo.
621
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][5]) is unused and will be removed from module GPIO_demo.
622
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][0]) is unused and will be removed from module GPIO_demo.
623
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][3]) is unused and will be removed from module GPIO_demo.
624
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][0]) is unused and will be removed from module GPIO_demo.
625
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][4]) is unused and will be removed from module GPIO_demo.
626
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][2]) is unused and will be removed from module GPIO_demo.
627
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][2]) is unused and will be removed from module GPIO_demo.
628
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][0]) is unused and will be removed from module GPIO_demo.
629
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[12][4]) is unused and will be removed from module GPIO_demo.
630
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][4]) is unused and will be removed from module GPIO_demo.
631
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][2]) is unused and will be removed from module GPIO_demo.
632
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][1]) is unused and will be removed from module GPIO_demo.
633
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][0]) is unused and will be removed from module GPIO_demo.
634
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][5]) is unused and will be removed from module GPIO_demo.
635
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][0]) is unused and will be removed from module GPIO_demo.
636
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][1]) is unused and will be removed from module GPIO_demo.
637
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][0]) is unused and will be removed from module GPIO_demo.
638
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][4]) is unused and will be removed from module GPIO_demo.
639
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][1]) is unused and will be removed from module GPIO_demo.
640
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][1]) is unused and will be removed from module GPIO_demo.
641
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][0]) is unused and will be removed from module GPIO_demo.
642
-WARNING: [Synth 8-3332] Sequential element (uartData_reg[7]) is unused and will be removed from module GPIO_demo.
643
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][2]) is unused and will be removed from module GPIO_demo.
644
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[5][3]) is unused and will be removed from module GPIO_demo.
645
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[26][0]) is unused and will be removed from module GPIO_demo.
646
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[16][3]) is unused and will be removed from module GPIO_demo.
647
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[24][0]) is unused and will be removed from module GPIO_demo.
648
-WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][1]) is unused and will be removed from module GPIO_demo.
649
-WARNING: [Synth 8-3332] Sequential element (y_max_reg[9]) is unused and will be removed from module MouseCtl.
650
----------------------------------------------------------------------------------
651
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 692.656 ; gain = 482.824
652
----------------------------------------------------------------------------------
653
----------------------------------------------------------------------------------
654
-Start ROM, RAM, DSP and Shift Register Reporting
655
----------------------------------------------------------------------------------
656
-
657
-ROM:
658
-+-------------+-------------+---------------+----------------+
659
-|Module Name  | RTL Object  | Depth x Width | Implemented As | 
660
-+-------------+-------------+---------------+----------------+
661
-|MouseCtl     | write_data  | 64x1          | LUT            | 
662
-|MouseDisplay | mouserom[0] | 256x2         | LUT            | 
663
-+-------------+-------------+---------------+----------------+
664
-
665
----------------------------------------------------------------------------------
666
-Finished ROM, RAM, DSP and Shift Register Reporting
667
----------------------------------------------------------------------------------
668
-
669
-Report RTL Partitions: 
670
-+-+--------------+------------+----------+
671
-| |RTL Partition |Replication |Instances |
672
-+-+--------------+------------+----------+
673
-+-+--------------+------------+----------+
674
----------------------------------------------------------------------------------
675
-Start Applying XDC Timing Constraints
676
----------------------------------------------------------------------------------
677
----------------------------------------------------------------------------------
678
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 692.656 ; gain = 482.824
679
----------------------------------------------------------------------------------
680
-
681
-Report RTL Partitions: 
682
-+-+--------------+------------+----------+
683
-| |RTL Partition |Replication |Instances |
684
-+-+--------------+------------+----------+
685
-+-+--------------+------------+----------+
686
----------------------------------------------------------------------------------
687
-Start Technology Mapping
688
----------------------------------------------------------------------------------
689
----------------------------------------------------------------------------------
690
-Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
691
----------------------------------------------------------------------------------
692
-
693
-Report RTL Partitions: 
694
-+-+--------------+------------+----------+
695
-| |RTL Partition |Replication |Instances |
696
-+-+--------------+------------+----------+
697
-+-+--------------+------------+----------+
698
----------------------------------------------------------------------------------
699
-Start IO Insertion
700
----------------------------------------------------------------------------------
701
----------------------------------------------------------------------------------
702
-Start Final Netlist Cleanup
703
----------------------------------------------------------------------------------
704
-INFO: [Synth 8-5365] Flop ps2_data_h_reg is being inverted and renamed to ps2_data_h_reg_inv.
705
----------------------------------------------------------------------------------
706
-Finished Final Netlist Cleanup
707
----------------------------------------------------------------------------------
708
----------------------------------------------------------------------------------
709
-Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
710
----------------------------------------------------------------------------------
711
-
712
-Report Check Netlist: 
713
-+------+------------------+-------+---------+-------+------------------+
714
-|      |Item              |Errors |Warnings |Status |Description       |
715
-+------+------------------+-------+---------+-------+------------------+
716
-|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
717
-+------+------------------+-------+---------+-------+------------------+
718
----------------------------------------------------------------------------------
719
-Start Renaming Generated Instances
720
----------------------------------------------------------------------------------
721
----------------------------------------------------------------------------------
722
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
723
----------------------------------------------------------------------------------
724
-
725
-Report RTL Partitions: 
726
-+-+--------------+------------+----------+
727
-| |RTL Partition |Replication |Instances |
728
-+-+--------------+------------+----------+
729
-+-+--------------+------------+----------+
730
----------------------------------------------------------------------------------
731
-Start Handling Custom Attributes
732
----------------------------------------------------------------------------------
733
----------------------------------------------------------------------------------
734
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
735
----------------------------------------------------------------------------------
736
----------------------------------------------------------------------------------
737
-Start Writing Synthesis Report
738
----------------------------------------------------------------------------------
739
-
740
-Report BlackBoxes: 
741
-+-+--------------+----------+
742
-| |BlackBox name |Instances |
743
-+-+--------------+----------+
744
-+-+--------------+----------+
745
-
746
-Report Cell Usage: 
747
-+------+-----------+------+
748
-|      |Cell       |Count |
749
-+------+-----------+------+
750
-|1     |BUFG       |     3|
751
-|2     |CARRY4     |   132|
752
-|3     |LUT1       |   368|
753
-|4     |LUT2       |   207|
754
-|5     |LUT3       |    91|
755
-|6     |LUT4       |   138|
756
-|7     |LUT5       |    73|
757
-|8     |LUT6       |   157|
758
-|9     |MMCME2_ADV |     1|
759
-|10    |MUXF7      |     3|
760
-|11    |FDRE       |   579|
761
-|12    |FDSE       |     2|
762
-|13    |IBUF       |    22|
763
-|14    |IOBUF      |     2|
764
-|15    |OBUF       |    43|
765
-+------+-----------+------+
766
-
767
-Report Instance Areas: 
768
-+------+------------------------+------------------+------+
769
-|      |Instance                |Module            |Cells |
770
-+------+------------------------+------------------+------+
771
-|1     |top                     |                  |  1821|
772
-|2     |  Inst_btn_debounce     |debouncer         |   215|
773
-|3     |  Inst_UART_TX_CTRL     |UART_TX_CTRL      |   133|
774
-|4     |  Inst_vga_ctrl         |vga_ctrl          |  1100|
775
-|5     |    clk_wiz_0_inst      |clk_wiz_0         |     3|
776
-|6     |      U0                |clk_wiz_0_clk_wiz |     3|
777
-|7     |    Inst_MouseCtl       |MouseCtl          |   680|
778
-|8     |      Inst_Ps2Interface |Ps2Interface      |   211|
779
-|9     |    Inst_MouseDisplay   |MouseDisplay      |   124|
780
-+------+------------------------+------------------+------+
781
----------------------------------------------------------------------------------
782
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824
783
----------------------------------------------------------------------------------
784
-Synthesis finished with 0 errors, 0 critical warnings and 76 warnings.
785
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 692.656 ; gain = 116.863
786
-Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 692.656 ; gain = 482.824
787
-INFO: [Project 1-571] Translating synthesized netlist
788
-INFO: [Netlist 29-17] Analyzing 157 Unisim elements for replacement
789
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
790
-INFO: [Project 1-570] Preparing netlist for logic optimization
791
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
792
-INFO: [Project 1-111] Unisim Transformation Summary:
793
-  A total of 2 instances were transformed.
794
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
795
-
796
-INFO: [Common 17-83] Releasing license: Synthesis
797
-245 Infos, 77 Warnings, 0 Critical Warnings and 0 Errors encountered.
798
-synth_design completed successfully
799
-synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 692.656 ; gain = 424.176
800
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.dcp' has been generated.
801
-report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 692.656 ; gain = 0.000
802
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:11:26 2021...

+ 0
- 43
proj/GPIO.runs/synth_1/runme.sh View File

1
-#!/bin/sh
2
-
3
-# 
4
-# Vivado(TM)
5
-# runme.sh: a Vivado-generated Runs Script for UNIX
6
-# Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
7
-# 
8
-
9
-echo "This script was generated under a different operating system."
10
-echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
11
-exit
12
-
13
-if [ -z "$PATH" ]; then
14
-  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin
15
-else
16
-  PATH=C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2016.4/bin:$PATH
17
-fi
18
-export PATH
19
-
20
-if [ -z "$LD_LIBRARY_PATH" ]; then
21
-  LD_LIBRARY_PATH=
22
-else
23
-  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
24
-fi
25
-export LD_LIBRARY_PATH
26
-
27
-HD_PWD='C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1'
28
-cd "$HD_PWD"
29
-
30
-HD_LOG=runme.log
31
-/bin/touch $HD_LOG
32
-
33
-ISEStep="./ISEWrap.sh"
34
-EAStep()
35
-{
36
-     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
37
-     if [ $? -ne 0 ]
38
-     then
39
-         exit
40
-     fi
41
-}
42
-
43
-EAStep vivado -log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl

+ 0
- 12
proj/GPIO.runs/synth_1/vivado.jou View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:10:44 2021
6
-# Process ID: 9840
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1
8
-# Command line: vivado.exe -log GPIO_demo.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.vds
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace

BIN
proj/GPIO.runs/synth_1/vivado.pb View File


+ 0
- 199
proj/GPIO.xpr View File

1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)              -->
3
-<!--                                                         -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
5
-
6
-<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.xpr">
7
-  <DefaultLaunch Dir="$PRUNDIR"/>
8
-  <Configuration>
9
-    <Option Name="Id" Val="0138f6f78b4b4ef3a03837b84ae3d333"/>
10
-    <Option Name="Part" Val="xc7a35tcpg236-1"/>
11
-    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
12
-    <Option Name="CompiledLibDirXSim" Val=""/>
13
-    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
14
-    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
15
-    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
16
-    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
17
-    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
18
-    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
19
-    <Option Name="TargetLanguage" Val="VHDL"/>
20
-    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
21
-    <Option Name="ActiveSimSet" Val="sim_1"/>
22
-    <Option Name="DefaultLib" Val="xil_defaultlib"/>
23
-    <Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
24
-    <Option Name="IPOutputRepo" Val="$PPRDIR/../repo/cache"/>
25
-    <Option Name="IPCachePermission" Val="read"/>
26
-    <Option Name="IPCachePermission" Val="write"/>
27
-    <Option Name="EnableCoreContainer" Val="FALSE"/>
28
-    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
29
-    <Option Name="IPUserFilesDir" Val="$PPRDIR/GPIO.ip_user_files"/>
30
-    <Option Name="IPStaticSourceDir" Val="$PPRDIR/GPIO.ip_user_files/ipstatic"/>
31
-    <Option Name="EnableBDX" Val="FALSE"/>
32
-    <Option Name="DSABoardId" Val="basys3"/>
33
-    <Option Name="DSANumComputeUnits" Val="16"/>
34
-    <Option Name="WTXSimLaunchSim" Val="0"/>
35
-    <Option Name="WTModelSimLaunchSim" Val="0"/>
36
-    <Option Name="WTQuestaLaunchSim" Val="0"/>
37
-    <Option Name="WTIesLaunchSim" Val="0"/>
38
-    <Option Name="WTVcsLaunchSim" Val="0"/>
39
-    <Option Name="WTRivieraLaunchSim" Val="0"/>
40
-    <Option Name="WTActivehdlLaunchSim" Val="0"/>
41
-    <Option Name="WTXSimExportSim" Val="0"/>
42
-    <Option Name="WTModelSimExportSim" Val="0"/>
43
-    <Option Name="WTQuestaExportSim" Val="0"/>
44
-    <Option Name="WTIesExportSim" Val="0"/>
45
-    <Option Name="WTVcsExportSim" Val="0"/>
46
-    <Option Name="WTRivieraExportSim" Val="0"/>
47
-    <Option Name="WTActivehdlExportSim" Val="0"/>
48
-    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
49
-    <Option Name="XSimRadix" Val="hex"/>
50
-    <Option Name="XSimTimeUnit" Val="ns"/>
51
-    <Option Name="XSimArrayDisplayLimit" Val="64"/>
52
-    <Option Name="XSimTraceLimit" Val="65536"/>
53
-  </Configuration>
54
-  <FileSets Version="1" Minor="31">
55
-    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
56
-      <Filter Type="Srcs"/>
57
-      <File Path="$PPRDIR/../src/hdl/Ps2Interface.vhd">
58
-        <FileInfo>
59
-          <Attr Name="UsedIn" Val="synthesis"/>
60
-          <Attr Name="UsedIn" Val="simulation"/>
61
-        </FileInfo>
62
-      </File>
63
-      <File Path="$PPRDIR/../src/hdl/clk_wiz_0_clk_wiz.vhd">
64
-        <FileInfo>
65
-          <Attr Name="UsedIn" Val="synthesis"/>
66
-          <Attr Name="UsedIn" Val="simulation"/>
67
-        </FileInfo>
68
-      </File>
69
-      <File Path="$PPRDIR/../src/hdl/MouseDisplay.vhd">
70
-        <FileInfo>
71
-          <Attr Name="UsedIn" Val="synthesis"/>
72
-          <Attr Name="UsedIn" Val="simulation"/>
73
-        </FileInfo>
74
-      </File>
75
-      <File Path="$PPRDIR/../src/hdl/MouseCtl.vhd">
76
-        <FileInfo>
77
-          <Attr Name="UsedIn" Val="synthesis"/>
78
-          <Attr Name="UsedIn" Val="simulation"/>
79
-        </FileInfo>
80
-      </File>
81
-      <File Path="$PPRDIR/../src/hdl/clk_wiz_0.vhd">
82
-        <FileInfo>
83
-          <Attr Name="UsedIn" Val="synthesis"/>
84
-          <Attr Name="UsedIn" Val="simulation"/>
85
-        </FileInfo>
86
-      </File>
87
-      <File Path="$PPRDIR/../src/hdl/vga_ctrl.vhd">
88
-        <FileInfo>
89
-          <Attr Name="UsedIn" Val="synthesis"/>
90
-          <Attr Name="UsedIn" Val="simulation"/>
91
-        </FileInfo>
92
-      </File>
93
-      <File Path="$PPRDIR/../src/hdl/UART_TX_CTRL.vhd">
94
-        <FileInfo>
95
-          <Attr Name="UsedIn" Val="synthesis"/>
96
-          <Attr Name="UsedIn" Val="simulation"/>
97
-        </FileInfo>
98
-      </File>
99
-      <File Path="$PPRDIR/../src/hdl/debouncer.vhd">
100
-        <FileInfo>
101
-          <Attr Name="UsedIn" Val="synthesis"/>
102
-          <Attr Name="UsedIn" Val="simulation"/>
103
-        </FileInfo>
104
-      </File>
105
-      <File Path="$PPRDIR/../src/hdl/GPIO_Demo.vhd">
106
-        <FileInfo>
107
-          <Attr Name="UsedIn" Val="synthesis"/>
108
-          <Attr Name="UsedIn" Val="simulation"/>
109
-        </FileInfo>
110
-      </File>
111
-      <Config>
112
-        <Option Name="DesignMode" Val="RTL"/>
113
-        <Option Name="TopModule" Val="GPIO_demo"/>
114
-        <Option Name="TopAutoSet" Val="TRUE"/>
115
-      </Config>
116
-    </FileSet>
117
-    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
118
-      <Filter Type="Constrs"/>
119
-      <File Path="$PPRDIR/../src/constraints/Basys3_Master.xdc">
120
-        <FileInfo>
121
-          <Attr Name="UsedIn" Val="synthesis"/>
122
-          <Attr Name="UsedIn" Val="implementation"/>
123
-        </FileInfo>
124
-      </File>
125
-      <Config>
126
-        <Option Name="ConstrsType" Val="XDC"/>
127
-      </Config>
128
-    </FileSet>
129
-    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
130
-      <Config>
131
-        <Option Name="DesignMode" Val="RTL"/>
132
-        <Option Name="TopModule" Val="GPIO_demo"/>
133
-        <Option Name="TopLib" Val="xil_defaultlib"/>
134
-        <Option Name="TopAutoSet" Val="TRUE"/>
135
-        <Option Name="TransportPathDelay" Val="0"/>
136
-        <Option Name="TransportIntDelay" Val="0"/>
137
-        <Option Name="SrcSet" Val="sources_1"/>
138
-      </Config>
139
-    </FileSet>
140
-  </FileSets>
141
-  <Simulators>
142
-    <Simulator Name="XSim">
143
-      <Option Name="Description" Val="Vivado Simulator"/>
144
-      <Option Name="CompiledLib" Val="0"/>
145
-    </Simulator>
146
-    <Simulator Name="ModelSim">
147
-      <Option Name="Description" Val="ModelSim Simulator"/>
148
-    </Simulator>
149
-    <Simulator Name="Questa">
150
-      <Option Name="Description" Val="Questa Advanced Simulator"/>
151
-    </Simulator>
152
-    <Simulator Name="Riviera">
153
-      <Option Name="Description" Val="Riviera-PRO Simulator"/>
154
-    </Simulator>
155
-    <Simulator Name="ActiveHDL">
156
-      <Option Name="Description" Val="Active-HDL Simulator"/>
157
-    </Simulator>
158
-  </Simulators>
159
-  <Runs Version="1" Minor="10">
160
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
161
-      <Strategy Version="1" Minor="2">
162
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015">
163
-          <Desc>Vivado Synthesis Defaults</Desc>
164
-        </StratHandle>
165
-        <Step Id="synth_design">
166
-          <Option Id="Directive">0</Option>
167
-          <Option Id="FlattenHierarchy">1</Option>
168
-          <Option Id="FsmExtraction">0</Option>
169
-        </Step>
170
-      </Strategy>
171
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
172
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
173
-    </Run>
174
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
175
-      <Strategy Version="1" Minor="2">
176
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015">
177
-          <Desc>Vivado Implementation Defaults</Desc>
178
-        </StratHandle>
179
-        <Step Id="init_design"/>
180
-        <Step Id="opt_design">
181
-          <Option Id="Directive">4</Option>
182
-        </Step>
183
-        <Step Id="power_opt_design"/>
184
-        <Step Id="place_design">
185
-          <Option Id="Directive">14</Option>
186
-        </Step>
187
-        <Step Id="post_place_power_opt_design"/>
188
-        <Step Id="phys_opt_design"/>
189
-        <Step Id="route_design">
190
-          <Option Id="Directive">5</Option>
191
-        </Step>
192
-        <Step Id="post_route_phys_opt_design"/>
193
-        <Step Id="write_bitstream"/>
194
-      </Strategy>
195
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
196
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
197
-    </Run>
198
-  </Runs>
199
-</Project>

+ 0
- 74
vivado.jou View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Wed Apr 14 08:09:08 2021
6
-# Process ID: 4032
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
8
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6828 C:\Users\Hp\Documents\Compteur8BitsBasys3\Compteur8BitsBasys3.xpr
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
11
-#-----------------------------------------------------------
12
-start_gui
13
-open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr
14
-launch_runs synth_1 -jobs 2
15
-wait_on_run synth_1
16
-launch_runs impl_1 -jobs 2
17
-wait_on_run impl_1
18
-remove_files  -fileset sim_1 C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
19
-file delete -force C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
20
-reset_run impl_1
21
-launch_runs impl_1 -jobs 2
22
-wait_on_run impl_1
23
-launch_runs impl_1 -to_step write_bitstream -jobs 2
24
-wait_on_run impl_1
25
-open_hw
26
-connect_hw_server
27
-open_hw_target
28
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
29
-current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
30
-refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
31
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
32
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
33
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
34
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
35
-reset_run synth_1
36
-launch_runs synth_1 -jobs 2
37
-wait_on_run synth_1
38
-reset_run synth_1
39
-launch_runs synth_1 -jobs 2
40
-wait_on_run synth_1
41
-launch_runs impl_1 -jobs 2
42
-wait_on_run impl_1
43
-reset_run synth_1
44
-launch_runs synth_1 -jobs 2
45
-wait_on_run synth_1
46
-launch_runs impl_1 -jobs 2
47
-wait_on_run impl_1
48
-reset_run synth_1
49
-launch_runs synth_1 -jobs 2
50
-wait_on_run synth_1
51
-launch_runs impl_1 -jobs 2
52
-wait_on_run impl_1
53
-reset_run synth_1
54
-launch_runs synth_1 -jobs 2
55
-wait_on_run synth_1
56
-launch_runs impl_1 -jobs 2
57
-wait_on_run impl_1
58
-launch_runs impl_1 -to_step write_bitstream -jobs 2
59
-wait_on_run impl_1
60
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
61
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
62
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
63
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
64
-reset_run synth_1
65
-launch_runs synth_1 -jobs 2
66
-wait_on_run synth_1
67
-launch_runs impl_1 -jobs 2
68
-wait_on_run impl_1
69
-launch_runs impl_1 -to_step write_bitstream -jobs 2
70
-wait_on_run impl_1
71
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
72
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
73
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
74
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]

+ 0
- 159
vivado.log View File

1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Wed Apr 14 08:09:08 2021
6
-# Process ID: 4032
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
8
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6828 C:\Users\Hp\Documents\Compteur8BitsBasys3\Compteur8BitsBasys3.xpr
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
11
-#-----------------------------------------------------------
12
-start_gui
13
-open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr
14
-Scanning sources...
15
-Finished scanning sources
16
-WARNING: [Project 1-509] GeneratedRun file for 'synth_1' not found
17
-WARNING: [Project 1-509] GeneratedRun file for 'impl_1' not found
18
-WARNING: [filemgmt 56-3] IPUserFilesDir: Could not find the directory 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.ip_user_files'.
19
-INFO: [IP_Flow 19-234] Refreshing IP repositories
20
-INFO: [IP_Flow 19-1704] No user IP repositories specified
21
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
22
-open_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 794.082 ; gain = 131.480
23
-launch_runs synth_1 -jobs 2
24
-INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
25
-[Wed Apr 14 08:24:05 2021] Launched synth_1...
26
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
27
-launch_runs impl_1 -jobs 2
28
-[Wed Apr 14 08:25:26 2021] Launched impl_1...
29
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
30
-remove_files  -fileset sim_1 C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
31
-file delete -force C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
32
-reset_run impl_1
33
-launch_runs impl_1 -jobs 2
34
-[Wed Apr 14 08:27:27 2021] Launched impl_1...
35
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
36
-launch_runs impl_1 -to_step write_bitstream -jobs 2
37
-[Wed Apr 14 08:29:13 2021] Launched impl_1...
38
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
39
-open_hw
40
-connect_hw_server
41
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
42
-INFO: [Labtools 27-2222] Launching hw_server...
43
-INFO: [Labtools 27-2221] Launch Output:
44
-
45
-****** Xilinx hw_server v2016.4
46
-  **** Build date : Jan 23 2017-19:37:29
47
-    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
48
-
49
-
50
-connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 881.043 ; gain = 0.000
51
-open_hw_target
52
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
53
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
54
-current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
55
-refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
56
-INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
57
-WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
58
-Resolution: 
59
-1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
60
-2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
61
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
62
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
63
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
64
-INFO: [Labtools 27-3164] End of startup status: HIGH
65
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
66
-INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
67
-WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
68
-Resolution: 
69
-1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
70
-2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
71
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
72
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
73
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
74
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
75
-reset_run synth_1
76
-launch_runs synth_1 -jobs 2
77
-INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd:1]
78
-[Wed Apr 14 08:32:22 2021] Launched synth_1...
79
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
80
-reset_run synth_1
81
-launch_runs synth_1 -jobs 2
82
-INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
83
-[Wed Apr 14 08:33:40 2021] Launched synth_1...
84
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
85
-launch_runs impl_1 -jobs 2
86
-[Wed Apr 14 08:34:54 2021] Launched impl_1...
87
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
88
-reset_run synth_1
89
-launch_runs synth_1 -jobs 2
90
-INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
91
-[Wed Apr 14 08:40:08 2021] Launched synth_1...
92
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
93
-launch_runs impl_1 -jobs 2
94
-[Wed Apr 14 08:41:23 2021] Launched impl_1...
95
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
96
-reset_run synth_1
97
-launch_runs synth_1 -jobs 2
98
-INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
99
-[Wed Apr 14 08:45:24 2021] Launched synth_1...
100
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
101
-launch_runs impl_1 -jobs 2
102
-[Wed Apr 14 08:46:41 2021] Launched impl_1...
103
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
104
-reset_run synth_1
105
-launch_runs synth_1 -jobs 2
106
-INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
107
-[Wed Apr 14 08:49:30 2021] Launched synth_1...
108
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
109
-launch_runs impl_1 -jobs 2
110
-[Wed Apr 14 08:50:57 2021] Launched impl_1...
111
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
112
-launch_runs impl_1 -to_step write_bitstream -jobs 2
113
-[Wed Apr 14 08:54:17 2021] Launched impl_1...
114
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
115
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
116
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
117
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
118
-INFO: [Labtools 27-3164] End of startup status: HIGH
119
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
120
-INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
121
-WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
122
-Resolution: 
123
-1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
124
-2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
125
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
126
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
127
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
128
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
129
-reset_run synth_1
130
-launch_runs synth_1 -jobs 2
131
-INFO: [HDL 9-1061] Parsing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd" into library xil_defaultlib [C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd:1]
132
-[Wed Apr 14 09:00:05 2021] Launched synth_1...
133
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/synth_1/runme.log
134
-launch_runs impl_1 -jobs 2
135
-[Wed Apr 14 09:00:59 2021] Launched impl_1...
136
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
137
-launch_runs impl_1 -to_step write_bitstream -jobs 2
138
-[Wed Apr 14 09:02:14 2021] Launched impl_1...
139
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/runme.log
140
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
141
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
142
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
143
-INFO: [Labtools 27-3164] End of startup status: HIGH
144
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
145
-INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
146
-WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
147
-Resolution: 
148
-1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
149
-2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
150
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
151
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
152
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
153
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
154
-ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA.
155
-Check cable connectivity and that the target board is powered up then
156
-use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
157
-ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
158
-exit
159
-INFO: [Common 17-206] Exiting Vivado at Wed Apr 14 18:31:17 2021...

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