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Test étage 4

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This commit is contained in:
Paul Faure 2021-06-18 09:26:32 +02:00
parent 402e684461
commit 5663419784
4 changed files with 173 additions and 28 deletions
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66
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
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@ -37,34 +37,44 @@ end Test_Etage4_Memoire;
architecture Behavioral of Test_Etage4_Memoire is
component Etage4_Memoire is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
Port ( CLK : in STD_LOGIC; -- Clock
RST : in STD_LOGIC; -- Reset
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
end component;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_IN_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111";
constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111110101111111111";
constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111011001111111111";
constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant CLK_period : time := 10 ns;
@ -72,11 +82,17 @@ begin
instance : Etage4_Memoire
generic map( Nb_bits => 8,
Mem_size => 256,
Instruction_bus_size => 3,
Mem_size => 16,
Adresse_mem_size => 4,
Instruction_bus_size => 5,
Mem_EBP_size => 8,
Adresse_size_mem_EBP => 3,
Bits_Controle_LC => Bits_Controle_LC,
Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET)
port map( CLK => my_CLK,
RST => my_RST,
IN_A => my_IN_A,
@ -96,9 +112,9 @@ begin
process
begin
my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
my_IN_A <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
my_IN_B <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
my_IN_Instruction <= "00000" after 0 ns, "01011" after 4 ns, "01011" after 14 ns;
my_RST <= '0' after 125 ns;
wait;
end process;

2
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
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File diff suppressed because one or more lines are too long

10
Processeur.xpr
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@ -32,7 +32,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="235"/>
<Option Name="WTXSimLaunchSim" Val="247"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -233,9 +233,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Test_Pipeline"/>
<Option Name="TopModule" Val="Test_Etage4_Memoire"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@ -243,6 +248,7 @@
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/>
</Config>
</FileSet>
</FileSets>

123
SimulationsConfig/Test_Etage4_Memoire_behav.wcfg Normal file
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@ -0,0 +1,123 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="Test_Etage4_Memoire_behav.wdb" id="1">
<top_modules>
<top_module name="Test_Etage4_Memoire" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="19120001fs"></ZoomEndTime>
<Cursor1Time time="8460000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="146"></NameColumnWidth>
<ValueColumnWidth column_width="193"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="25" />
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_CLK">
<obj_property name="ElementShortName">my_CLK</obj_property>
<obj_property name="ObjectShortName">my_CLK</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_RST">
<obj_property name="ElementShortName">my_RST</obj_property>
<obj_property name="ObjectShortName">my_RST</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_A">
<obj_property name="ElementShortName">my_IN_A[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B">
<obj_property name="ElementShortName">my_IN_B[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_Instruction">
<obj_property name="ElementShortName">my_IN_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_Instruction[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_A">
<obj_property name="ElementShortName">my_OUT_A[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_A[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_B">
<obj_property name="ElementShortName">my_OUT_B[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_B[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_Instruction">
<obj_property name="ElementShortName">my_OUT_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_Instruction[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
<obj_property name="ElementShortName">Addr[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
<obj_property name="ElementShortName">D_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
<obj_property name="ElementShortName">RW</obj_property>
<obj_property name="ObjectShortName">RW</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
<obj_property name="ElementShortName">MEMORY[127:0]</obj_property>
<obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Addr_MemoireDonnees">
<obj_property name="ElementShortName">Addr_MemoireDonnees[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/IN_Addr_MemoireDonnees">
<obj_property name="ElementShortName">IN_Addr_MemoireDonnees[3:0]</obj_property>
<obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Addr_MemoireDonnees_EBP">
<obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
<obj_property name="ElementShortName">Addr[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
<obj_property name="ElementShortName">RW</obj_property>
<obj_property name="ObjectShortName">RW</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
<obj_property name="ElementShortName">D_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RST">
<obj_property name="ElementShortName">RST</obj_property>
<obj_property name="ObjectShortName">RST</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_OUT">
<obj_property name="ElementShortName">D_OUT[7:0]</obj_property>
<obj_property name="ObjectShortName">D_OUT[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
<obj_property name="ElementShortName">MEMORY[127:0]</obj_property>
<obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Nb_bits">
<obj_property name="ElementShortName">Nb_bits</obj_property>
<obj_property name="ObjectShortName">Nb_bits</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr_size">
<obj_property name="ElementShortName">Addr_size</obj_property>
<obj_property name="ObjectShortName">Addr_size</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Mem_size">
<obj_property name="ElementShortName">Mem_size</obj_property>
<obj_property name="ObjectShortName">Mem_size</obj_property>
</wvobject>
</wave_config>