Browse Source

Test étage 4

Paul Faure 3 months ago
parent
commit
5663419784

+ 41
- 25
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd View File

@@ -37,34 +37,44 @@ end Test_Etage4_Memoire;
37 37
 
38 38
 architecture Behavioral of Test_Etage4_Memoire is
39 39
     component Etage4_Memoire is
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-    Generic ( Nb_bits : Natural;
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-              Mem_size : Natural;
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-              Instruction_bus_size : Natural;
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-              Bits_Controle_LC : STD_LOGIC_VECTOR;
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-              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
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-              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
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-        Port ( CLK : in STD_LOGIC;
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-               RST : in STD_LOGIC;
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-               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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-               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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-               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
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-               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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-               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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-               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
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+    Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
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+              Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
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+              Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
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+              Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
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+              Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
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+              Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
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+              Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
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+              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
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+              Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
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+              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
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+              Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
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+              Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
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+    Port ( CLK : in STD_LOGIC; -- Clock
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+           RST : in STD_LOGIC; -- Reset
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+           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
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+           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
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+           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
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+           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
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+           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
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+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
54 60
     end component;
55 61
     
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     signal my_CLK : STD_LOGIC := '0';
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     signal my_RST : STD_LOGIC := '1';
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     signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
59 65
     signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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-    signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
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+    signal my_IN_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
61 67
     signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
62 68
     signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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-    signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
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+    signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
64 70
     
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-    constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
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-    constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
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-    constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
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+    constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111";
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+    constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111110101111111111";
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+    constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111011001111111111";
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+    constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000";
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+    
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+    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
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+    constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
68 78
     
69 79
     constant CLK_period : time := 10 ns;
70 80
     
@@ -72,11 +82,17 @@ begin
72 82
 
73 83
     instance : Etage4_Memoire
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     generic map( Nb_bits => 8,
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-                 Mem_size => 256,
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-                 Instruction_bus_size => 3,
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+                 Mem_size => 16,
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+                 Adresse_mem_size => 4,
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+                 Instruction_bus_size => 5,
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+                 Mem_EBP_size => 8,
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+                 Adresse_size_mem_EBP => 3,
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                  Bits_Controle_LC => Bits_Controle_LC,
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                  Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
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-                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
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+                 Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP,
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+                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT,
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+                 Code_Instruction_CALL => Code_Instruction_CALL,
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+                 Code_Instruction_RET => Code_Instruction_RET)
80 96
     port map(    CLK => my_CLK,
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                  RST => my_RST,
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                  IN_A => my_IN_A,
@@ -96,9 +112,9 @@ begin
96 112
     
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     process 
98 114
     begin     
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-        my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
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-        my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
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-        my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
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+        my_IN_A <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
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+        my_IN_B <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
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+        my_IN_Instruction <= "00000" after 0 ns, "01011" after 4 ns, "01011" after 14 ns;
102 118
         my_RST <= '0' after 125 ns;
103 119
         wait;
104 120
     end process;    

+ 1
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
File diff suppressed because it is too large
View File


+ 8
- 2
Processeur.xpr View File

@@ -32,7 +32,7 @@
32 32
     <Option Name="EnableBDX" Val="FALSE"/>
33 33
     <Option Name="DSABoardId" Val="basys3"/>
34 34
     <Option Name="DSANumComputeUnits" Val="16"/>
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-    <Option Name="WTXSimLaunchSim" Val="235"/>
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+    <Option Name="WTXSimLaunchSim" Val="247"/>
36 36
     <Option Name="WTModelSimLaunchSim" Val="0"/>
37 37
     <Option Name="WTQuestaLaunchSim" Val="0"/>
38 38
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -233,9 +233,14 @@
233 233
           <Attr Name="UsedIn" Val="simulation"/>
234 234
         </FileInfo>
235 235
       </File>
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+      <File Path="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg">
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+        <FileInfo>
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+          <Attr Name="UsedIn" Val="simulation"/>
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+        </FileInfo>
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+      </File>
236 241
       <Config>
237 242
         <Option Name="DesignMode" Val="RTL"/>
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-        <Option Name="TopModule" Val="Test_Pipeline"/>
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+        <Option Name="TopModule" Val="Test_Etage4_Memoire"/>
239 244
         <Option Name="TopLib" Val="xil_defaultlib"/>
240 245
         <Option Name="TransportPathDelay" Val="0"/>
241 246
         <Option Name="TransportIntDelay" Val="0"/>
@@ -243,6 +248,7 @@
243 248
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
244 249
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
245 250
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
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+        <Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/>
246 252
       </Config>
247 253
     </FileSet>
248 254
   </FileSets>

+ 123
- 0
SimulationsConfig/Test_Etage4_Memoire_behav.wcfg View File

@@ -0,0 +1,123 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
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+<wave_config>
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+   <wave_state>
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+   </wave_state>
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+   <db_ref_list>
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+      <db_ref path="Test_Etage4_Memoire_behav.wdb" id="1">
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+         <top_modules>
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+            <top_module name="Test_Etage4_Memoire" />
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+         </top_modules>
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+      </db_ref>
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+   </db_ref_list>
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+   <zoom_setting>
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+      <ZoomStartTime time="0fs"></ZoomStartTime>
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+      <ZoomEndTime time="19120001fs"></ZoomEndTime>
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+      <Cursor1Time time="8460000fs"></Cursor1Time>
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+   </zoom_setting>
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+   <column_width_setting>
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+      <NameColumnWidth column_width="146"></NameColumnWidth>
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+      <ValueColumnWidth column_width="193"></ValueColumnWidth>
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+   </column_width_setting>
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+   <WVObjectSize size="25" />
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+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_CLK">
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+      <obj_property name="ElementShortName">my_CLK</obj_property>
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+      <obj_property name="ObjectShortName">my_CLK</obj_property>
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+   </wvobject>
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+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_RST">
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+      <obj_property name="ElementShortName">my_RST</obj_property>
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+      <obj_property name="ObjectShortName">my_RST</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_A">
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+      <obj_property name="ElementShortName">my_IN_A[7:0]</obj_property>
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+      <obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B">
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+      <obj_property name="ElementShortName">my_IN_B[7:0]</obj_property>
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+      <obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_Instruction">
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+      <obj_property name="ElementShortName">my_IN_Instruction[4:0]</obj_property>
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+      <obj_property name="ObjectShortName">my_IN_Instruction[4:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_A">
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+      <obj_property name="ElementShortName">my_OUT_A[7:0]</obj_property>
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+      <obj_property name="ObjectShortName">my_OUT_A[7:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_B">
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+      <obj_property name="ElementShortName">my_OUT_B[7:0]</obj_property>
48
+      <obj_property name="ObjectShortName">my_OUT_B[7:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_Instruction">
51
+      <obj_property name="ElementShortName">my_OUT_Instruction[4:0]</obj_property>
52
+      <obj_property name="ObjectShortName">my_OUT_Instruction[4:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
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+      <obj_property name="ElementShortName">Addr[3:0]</obj_property>
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+      <obj_property name="ObjectShortName">Addr[3:0]</obj_property>
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+   </wvobject>
58
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
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+      <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
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+      <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
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+      <obj_property name="ElementShortName">RW</obj_property>
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+      <obj_property name="ObjectShortName">RW</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
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+      <obj_property name="ElementShortName">MEMORY[127:0]</obj_property>
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+      <obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
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+      <obj_property name="Radix">HEXRADIX</obj_property>
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+   </wvobject>
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+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Addr_MemoireDonnees">
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+      <obj_property name="ElementShortName">Addr_MemoireDonnees[3:0]</obj_property>
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+      <obj_property name="ObjectShortName">Addr_MemoireDonnees[3:0]</obj_property>
74
+   </wvobject>
75
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/IN_Addr_MemoireDonnees">
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+      <obj_property name="ElementShortName">IN_Addr_MemoireDonnees[3:0]</obj_property>
77
+      <obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[3:0]</obj_property>
78
+   </wvobject>
79
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Addr_MemoireDonnees_EBP">
80
+      <obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[3:0]</obj_property>
81
+      <obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[3:0]</obj_property>
82
+   </wvobject>
83
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
84
+      <obj_property name="ElementShortName">Addr[3:0]</obj_property>
85
+      <obj_property name="ObjectShortName">Addr[3:0]</obj_property>
86
+   </wvobject>
87
+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
88
+      <obj_property name="ElementShortName">RW</obj_property>
89
+      <obj_property name="ObjectShortName">RW</obj_property>
90
+   </wvobject>
91
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
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+      <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
93
+      <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
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+   </wvobject>
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+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RST">
96
+      <obj_property name="ElementShortName">RST</obj_property>
97
+      <obj_property name="ObjectShortName">RST</obj_property>
98
+   </wvobject>
99
+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/CLK">
100
+      <obj_property name="ElementShortName">CLK</obj_property>
101
+      <obj_property name="ObjectShortName">CLK</obj_property>
102
+   </wvobject>
103
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_OUT">
104
+      <obj_property name="ElementShortName">D_OUT[7:0]</obj_property>
105
+      <obj_property name="ObjectShortName">D_OUT[7:0]</obj_property>
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+   </wvobject>
107
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
108
+      <obj_property name="ElementShortName">MEMORY[127:0]</obj_property>
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+      <obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
110
+   </wvobject>
111
+   <wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Nb_bits">
112
+      <obj_property name="ElementShortName">Nb_bits</obj_property>
113
+      <obj_property name="ObjectShortName">Nb_bits</obj_property>
114
+   </wvobject>
115
+   <wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr_size">
116
+      <obj_property name="ElementShortName">Addr_size</obj_property>
117
+      <obj_property name="ObjectShortName">Addr_size</obj_property>
118
+   </wvobject>
119
+   <wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Mem_size">
120
+      <obj_property name="ElementShortName">Mem_size</obj_property>
121
+      <obj_property name="ObjectShortName">Mem_size</obj_property>
122
+   </wvobject>
123
+</wave_config>

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