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@@ -37,34 +37,44 @@ end Test_Etage4_Memoire;
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architecture Behavioral of Test_Etage4_Memoire is
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component Etage4_Memoire is
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- Generic ( Nb_bits : Natural;
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- Mem_size : Natural;
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- Instruction_bus_size : Natural;
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- Bits_Controle_LC : STD_LOGIC_VECTOR;
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- Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
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- Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
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- Port ( CLK : in STD_LOGIC;
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- RST : in STD_LOGIC;
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- IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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- IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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- IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
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- OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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- OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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- OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
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+ Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
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+ Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
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+ Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
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+ Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
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+ Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
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+ Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
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+ Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
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+ Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
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+ Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
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+ Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
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+ Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
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+ Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
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+ Port ( CLK : in STD_LOGIC; -- Clock
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+ RST : in STD_LOGIC; -- Reset
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+ IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
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+ IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
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+ IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
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+ OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
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+ OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
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+ OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
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end component;
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signal my_CLK : STD_LOGIC := '0';
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signal my_RST : STD_LOGIC := '1';
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signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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- signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
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+ signal my_IN_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
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signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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- signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
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+ signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
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- constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
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- constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
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- constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
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+ constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111";
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+ constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111110101111111111";
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+ constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111011001111111111";
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+ constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000";
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+
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+ constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
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+ constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
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constant CLK_period : time := 10 ns;
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@@ -72,11 +82,17 @@ begin
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instance : Etage4_Memoire
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generic map( Nb_bits => 8,
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- Mem_size => 256,
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- Instruction_bus_size => 3,
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+ Mem_size => 16,
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+ Adresse_mem_size => 4,
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+ Instruction_bus_size => 5,
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+ Mem_EBP_size => 8,
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+ Adresse_size_mem_EBP => 3,
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Bits_Controle_LC => Bits_Controle_LC,
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Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
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- Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
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+ Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP,
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+ Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT,
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+ Code_Instruction_CALL => Code_Instruction_CALL,
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+ Code_Instruction_RET => Code_Instruction_RET)
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port map( CLK => my_CLK,
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RST => my_RST,
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IN_A => my_IN_A,
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@@ -96,9 +112,9 @@ begin
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process
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begin
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- my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
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- my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
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- my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
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+ my_IN_A <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
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+ my_IN_B <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
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+ my_IN_Instruction <= "00000" after 0 ns, "01011" after 4 ns, "01011" after 14 ns;
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my_RST <= '0' after 125 ns;
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wait;
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end process;
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