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-#-----------------------------------------------------------
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-# Vivado v2016.4 (64-bit)
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-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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-# Start of session at: Mon May 10 16:43:40 2021
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-# Process ID: 13872
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-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
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-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1028 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
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-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
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-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
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-#-----------------------------------------------------------
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-start_gui
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-open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr
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-CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg'.
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-CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg'.
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-Scanning sources...
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-Finished scanning sources
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-INFO: [IP_Flow 19-234] Refreshing IP repositories
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-INFO: [IP_Flow 19-1704] No user IP repositories specified
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-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
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-open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 839.340 ; gain = 198.637
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-launch_simulation
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-INFO: [SIM-utils-51] Simulation object is 'sim_1'
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-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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-INFO: [USF-XSim-97] Finding global include files...
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-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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-INFO: [USF-XSim-2] XSim::Compile design
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-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity ALU
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity System
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity BancRegistres
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MUX
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity LC
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Pipeline
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Clock_Divider
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity TestALU
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Test_LC
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Test_MUX
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
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-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
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-INFO: [USF-XSim-3] XSim::Elaborate design
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-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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-Vivado Simulator 2016.4
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-Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
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-Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
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-Using 2 slave threads.
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-Starting static elaboration
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-Completed static elaboration
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-Starting simulation data flow analysis
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-Completed simulation data flow analysis
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-Time Resolution for simulation is 1ps
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-Compiling package std.standard
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-Compiling package std.textio
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-Compiling package ieee.std_logic_1164
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-Compiling package ieee.std_logic_arith
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-Compiling package ieee.std_logic_unsigned
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-Compiling package ieee.numeric_std
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-Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
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-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
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-Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
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-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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-Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
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-Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
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-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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-Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
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-Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
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-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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-Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
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-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
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-Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
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-Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
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-Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
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-Built simulation snapshot Test_Pipeline_behav
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-
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-****** Webtalk v2016.4 (64-bit)
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- **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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- **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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- ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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-
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-source C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
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-INFO: [Common 17-206] Exiting Webtalk at Mon May 10 17:15:25 2021...
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-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
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-INFO: [USF-XSim-4] XSim::Simulate design
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-WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
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-WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
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-WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
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-WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
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-INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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-INFO: [USF-XSim-98] *** Running xsim
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- with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
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-INFO: [USF-XSim-8] Loading simulator feature
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-Vivado Simulator 2016.4
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-Time resolution is 1 ps
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-source Test_Pipeline.tcl
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-# set curr_wave [current_wave_config]
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-# if { [string length $curr_wave] == 0 } {
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-# if { [llength [get_objects]] > 0} {
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-# add_wave /
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-# set_property needs_save false [current_wave_config]
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-# } else {
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-# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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-# }
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-# }
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-# run 1000ns
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-ERROR: Index 191 out of bound 127 downto 0
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-Time: 10 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/line__68
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- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd
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-
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-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd:68
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-INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
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-INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 872.664 ; gain = 3.988
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-relaunch_sim
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-INFO: [SIM-utils-51] Simulation object is 'sim_1'
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-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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-INFO: [USF-XSim-97] Finding global include files...
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-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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-INFO: [USF-XSim-2] XSim::Compile design
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-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity ALU
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity System
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity BancRegistres
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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-INFO: [VRFC 10-307] analyzing entity MUX
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185
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
186
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-INFO: [VRFC 10-307] analyzing entity LC
|
187
|
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
188
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-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
189
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
190
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-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
191
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
192
|
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-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
193
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
194
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-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
195
|
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
196
|
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-INFO: [VRFC 10-307] analyzing entity Pipeline
|
197
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
198
|
|
-INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
199
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|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
200
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-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
201
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
202
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-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
203
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
204
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-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
205
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
206
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-INFO: [VRFC 10-307] analyzing entity TestALU
|
207
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
208
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-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
209
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
210
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-INFO: [VRFC 10-307] analyzing entity Test_LC
|
211
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
212
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-INFO: [VRFC 10-307] analyzing entity Test_MUX
|
213
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
214
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-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
215
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
216
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-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
217
|
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
218
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-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
219
|
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
220
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-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
221
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-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
222
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-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
223
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-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
224
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-INFO: [USF-XSim-3] XSim::Elaborate design
|
225
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-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
226
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-Vivado Simulator 2016.4
|
227
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-Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
228
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-Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
229
|
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-Using 2 slave threads.
|
230
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-Starting static elaboration
|
231
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-Completed static elaboration
|
232
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-Starting simulation data flow analysis
|
233
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-Completed simulation data flow analysis
|
234
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-Time Resolution for simulation is 1ps
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235
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-Compiling package std.standard
|
236
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-Compiling package std.textio
|
237
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-Compiling package ieee.std_logic_1164
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-Compiling package ieee.std_logic_arith
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-Compiling package ieee.std_logic_unsigned
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240
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-Compiling package ieee.numeric_std
|
241
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-Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
242
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-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
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243
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-Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
244
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-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
245
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
246
|
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
247
|
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-Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
248
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
249
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
250
|
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
251
|
|
-Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
252
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
253
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
254
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-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
255
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
256
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
257
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
258
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
|
259
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
260
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
261
|
|
-Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
262
|
|
-Built simulation snapshot Test_Pipeline_behav
|
263
|
|
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
|
264
|
|
-Vivado Simulator 2016.4
|
265
|
|
-Time resolution is 1 ps
|
266
|
|
-ERROR: Array sizes do not match, left array has 5 elements, right array has 8 elements
|
267
|
|
-Time: 0 ps Iteration: 0 Process: /Test_Pipeline/instance/instance_Etage4/line__190
|
268
|
|
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
|
269
|
|
-
|
270
|
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-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd:190
|
271
|
|
-relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 884.223 ; gain = 0.000
|
272
|
|
-relaunch_sim
|
273
|
|
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
274
|
|
-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
275
|
|
-INFO: [USF-XSim-97] Finding global include files...
|
276
|
|
-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
277
|
|
-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
278
|
|
-INFO: [USF-XSim-2] XSim::Compile design
|
279
|
|
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
280
|
|
-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
281
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
282
|
|
-INFO: [VRFC 10-307] analyzing entity ALU
|
283
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
284
|
|
-INFO: [VRFC 10-307] analyzing entity System
|
285
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
286
|
|
-INFO: [VRFC 10-307] analyzing entity BancRegistres
|
287
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
288
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
289
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
290
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
291
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
292
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
293
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
294
|
|
-INFO: [VRFC 10-307] analyzing entity MUX
|
295
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
296
|
|
-INFO: [VRFC 10-307] analyzing entity LC
|
297
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
298
|
|
-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
299
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
300
|
|
-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
301
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
302
|
|
-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
303
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
304
|
|
-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
305
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
306
|
|
-INFO: [VRFC 10-307] analyzing entity Pipeline
|
307
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
308
|
|
-INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
309
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
310
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
311
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
312
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
313
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
314
|
|
-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
315
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
316
|
|
-INFO: [VRFC 10-307] analyzing entity TestALU
|
317
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
318
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
319
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
320
|
|
-INFO: [VRFC 10-307] analyzing entity Test_LC
|
321
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
322
|
|
-INFO: [VRFC 10-307] analyzing entity Test_MUX
|
323
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
324
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
325
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
326
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
327
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
328
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
329
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
330
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
331
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
332
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
333
|
|
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
334
|
|
-INFO: [USF-XSim-3] XSim::Elaborate design
|
335
|
|
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
336
|
|
-Vivado Simulator 2016.4
|
337
|
|
-Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
338
|
|
-Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
339
|
|
-Using 2 slave threads.
|
340
|
|
-Starting static elaboration
|
341
|
|
-Completed static elaboration
|
342
|
|
-Starting simulation data flow analysis
|
343
|
|
-Completed simulation data flow analysis
|
344
|
|
-Time Resolution for simulation is 1ps
|
345
|
|
-Compiling package std.standard
|
346
|
|
-Compiling package std.textio
|
347
|
|
-Compiling package ieee.std_logic_1164
|
348
|
|
-Compiling package ieee.std_logic_arith
|
349
|
|
-Compiling package ieee.std_logic_unsigned
|
350
|
|
-Compiling package ieee.numeric_std
|
351
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
352
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
|
353
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
354
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
355
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
356
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
357
|
|
-Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
358
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
359
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
360
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
361
|
|
-Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
362
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
363
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
364
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
365
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
366
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
367
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
368
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
|
369
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
370
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
371
|
|
-Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
372
|
|
-Built simulation snapshot Test_Pipeline_behav
|
373
|
|
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
374
|
|
-Vivado Simulator 2016.4
|
375
|
|
-Time resolution is 1 ps
|
376
|
|
-ERROR: Index 185 out of bound 95 downto 0
|
377
|
|
-Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
378
|
|
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
379
|
|
-
|
380
|
|
-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
381
|
|
-relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 886.633 ; gain = 0.000
|
382
|
|
-restart
|
383
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
384
|
|
-run 10 us
|
385
|
|
-ERROR: Index 185 out of bound 95 downto 0
|
386
|
|
-Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
387
|
|
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
388
|
|
-
|
389
|
|
-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
390
|
|
-restart
|
391
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
392
|
|
-run 10 us
|
393
|
|
-ERROR: Index 185 out of bound 95 downto 0
|
394
|
|
-Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
395
|
|
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
396
|
|
-
|
397
|
|
-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
398
|
|
-restart
|
399
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
400
|
|
-run 10 us
|
401
|
|
-ERROR: Index 185 out of bound 95 downto 0
|
402
|
|
-Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
403
|
|
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
404
|
|
-
|
405
|
|
-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
406
|
|
-restart
|
407
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
408
|
|
-run 10 us
|
409
|
|
-ERROR: Index 185 out of bound 95 downto 0
|
410
|
|
-Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
411
|
|
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
412
|
|
-
|
413
|
|
-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
414
|
|
-relaunch_sim
|
415
|
|
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
416
|
|
-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
417
|
|
-INFO: [USF-XSim-97] Finding global include files...
|
418
|
|
-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
419
|
|
-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
420
|
|
-INFO: [USF-XSim-2] XSim::Compile design
|
421
|
|
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
422
|
|
-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
423
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
424
|
|
-INFO: [VRFC 10-307] analyzing entity ALU
|
425
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
426
|
|
-INFO: [VRFC 10-307] analyzing entity System
|
427
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
428
|
|
-INFO: [VRFC 10-307] analyzing entity BancRegistres
|
429
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
430
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
431
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
432
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
433
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
434
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
435
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
436
|
|
-INFO: [VRFC 10-307] analyzing entity MUX
|
437
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
438
|
|
-INFO: [VRFC 10-307] analyzing entity LC
|
439
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
440
|
|
-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
441
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
442
|
|
-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
443
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
444
|
|
-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
445
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
446
|
|
-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
447
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
448
|
|
-INFO: [VRFC 10-307] analyzing entity Pipeline
|
449
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
450
|
|
-INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
451
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
452
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
453
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
454
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
455
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
456
|
|
-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
457
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
458
|
|
-INFO: [VRFC 10-307] analyzing entity TestALU
|
459
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
460
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
461
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
462
|
|
-INFO: [VRFC 10-307] analyzing entity Test_LC
|
463
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
464
|
|
-INFO: [VRFC 10-307] analyzing entity Test_MUX
|
465
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
466
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
467
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
468
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
469
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
470
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
471
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
472
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
473
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
474
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
475
|
|
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
476
|
|
-INFO: [USF-XSim-3] XSim::Elaborate design
|
477
|
|
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
478
|
|
-Vivado Simulator 2016.4
|
479
|
|
-Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
480
|
|
-Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
481
|
|
-Using 2 slave threads.
|
482
|
|
-Starting static elaboration
|
483
|
|
-Completed static elaboration
|
484
|
|
-Starting simulation data flow analysis
|
485
|
|
-Completed simulation data flow analysis
|
486
|
|
-Time Resolution for simulation is 1ps
|
487
|
|
-Compiling package std.standard
|
488
|
|
-Compiling package std.textio
|
489
|
|
-Compiling package ieee.std_logic_1164
|
490
|
|
-Compiling package ieee.std_logic_arith
|
491
|
|
-Compiling package ieee.std_logic_unsigned
|
492
|
|
-Compiling package ieee.numeric_std
|
493
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
494
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
|
495
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
496
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
497
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
498
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
499
|
|
-Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
500
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
501
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
502
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
503
|
|
-Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
504
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
505
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
506
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
507
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
508
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
509
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
510
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
|
511
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
512
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
513
|
|
-Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
514
|
|
-Built simulation snapshot Test_Pipeline_behav
|
515
|
|
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
516
|
|
-Vivado Simulator 2016.4
|
517
|
|
-Time resolution is 1 ps
|
518
|
|
-ERROR: Index 185 out of bound 95 downto 0
|
519
|
|
-Time: 520 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
520
|
|
- File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
521
|
|
-
|
522
|
|
-HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
523
|
|
-relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
|
524
|
|
-relaunch_sim
|
525
|
|
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
526
|
|
-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
527
|
|
-INFO: [USF-XSim-97] Finding global include files...
|
528
|
|
-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
529
|
|
-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
530
|
|
-INFO: [USF-XSim-2] XSim::Compile design
|
531
|
|
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
532
|
|
-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
533
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
534
|
|
-INFO: [VRFC 10-307] analyzing entity ALU
|
535
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
536
|
|
-INFO: [VRFC 10-307] analyzing entity System
|
537
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
538
|
|
-INFO: [VRFC 10-307] analyzing entity BancRegistres
|
539
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
540
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
541
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
542
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
543
|
|
-ERROR: [VRFC 10-1412] syntax error near begin [C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd:44]
|
544
|
|
-INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd ignored due to errors
|
545
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
546
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
547
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
548
|
|
-INFO: [VRFC 10-307] analyzing entity MUX
|
549
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
550
|
|
-INFO: [VRFC 10-307] analyzing entity LC
|
551
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
552
|
|
-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
553
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
554
|
|
-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
555
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
556
|
|
-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
557
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
558
|
|
-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
559
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
560
|
|
-INFO: [VRFC 10-307] analyzing entity Pipeline
|
561
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
562
|
|
-INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
563
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
564
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
565
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
566
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
567
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
568
|
|
-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
569
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
570
|
|
-INFO: [VRFC 10-307] analyzing entity TestALU
|
571
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
572
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
573
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
574
|
|
-INFO: [VRFC 10-307] analyzing entity Test_LC
|
575
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
576
|
|
-INFO: [VRFC 10-307] analyzing entity Test_MUX
|
577
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
578
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
579
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
580
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
581
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
582
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
583
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
584
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
585
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
586
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
587
|
|
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
588
|
|
-INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log'
|
589
|
|
-ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
|
590
|
|
-ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
591
|
|
-ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
592
|
|
-ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
593
|
|
-
|
594
|
|
-relaunch_sim
|
595
|
|
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
596
|
|
-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
597
|
|
-INFO: [USF-XSim-97] Finding global include files...
|
598
|
|
-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
599
|
|
-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
600
|
|
-INFO: [USF-XSim-2] XSim::Compile design
|
601
|
|
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
602
|
|
-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
603
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
604
|
|
-INFO: [VRFC 10-307] analyzing entity ALU
|
605
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
606
|
|
-INFO: [VRFC 10-307] analyzing entity System
|
607
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
608
|
|
-INFO: [VRFC 10-307] analyzing entity BancRegistres
|
609
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
610
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
611
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
612
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
613
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
614
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
615
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
616
|
|
-INFO: [VRFC 10-307] analyzing entity MUX
|
617
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
618
|
|
-INFO: [VRFC 10-307] analyzing entity LC
|
619
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
620
|
|
-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
621
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
622
|
|
-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
623
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
624
|
|
-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
625
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
626
|
|
-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
627
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
628
|
|
-INFO: [VRFC 10-307] analyzing entity Pipeline
|
629
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
630
|
|
-INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
631
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
632
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
633
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
634
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
635
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
636
|
|
-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
637
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
638
|
|
-INFO: [VRFC 10-307] analyzing entity TestALU
|
639
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
640
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
641
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
642
|
|
-INFO: [VRFC 10-307] analyzing entity Test_LC
|
643
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
644
|
|
-INFO: [VRFC 10-307] analyzing entity Test_MUX
|
645
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
646
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
647
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
648
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
649
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
650
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
651
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
652
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
653
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
654
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
655
|
|
-INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
656
|
|
-INFO: [USF-XSim-3] XSim::Elaborate design
|
657
|
|
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
658
|
|
-Vivado Simulator 2016.4
|
659
|
|
-Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
660
|
|
-Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
661
|
|
-Using 2 slave threads.
|
662
|
|
-Starting static elaboration
|
663
|
|
-Completed static elaboration
|
664
|
|
-Starting simulation data flow analysis
|
665
|
|
-Completed simulation data flow analysis
|
666
|
|
-Time Resolution for simulation is 1ps
|
667
|
|
-Compiling package std.standard
|
668
|
|
-Compiling package std.textio
|
669
|
|
-Compiling package ieee.std_logic_1164
|
670
|
|
-Compiling package ieee.std_logic_arith
|
671
|
|
-Compiling package ieee.std_logic_unsigned
|
672
|
|
-Compiling package ieee.numeric_std
|
673
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
674
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
|
675
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
676
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
677
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
678
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
679
|
|
-Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
680
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
681
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
682
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
683
|
|
-Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
684
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
685
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
686
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
687
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
688
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
689
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
690
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
|
691
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
692
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
693
|
|
-Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
694
|
|
-Built simulation snapshot Test_Pipeline_behav
|
695
|
|
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
696
|
|
-Vivado Simulator 2016.4
|
697
|
|
-Time resolution is 1 ps
|
698
|
|
-relaunch_sim
|
699
|
|
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
700
|
|
-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
701
|
|
-INFO: [USF-XSim-97] Finding global include files...
|
702
|
|
-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
703
|
|
-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
704
|
|
-INFO: [USF-XSim-2] XSim::Compile design
|
705
|
|
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
706
|
|
-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
707
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
708
|
|
-INFO: [VRFC 10-307] analyzing entity ALU
|
709
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
710
|
|
-INFO: [VRFC 10-307] analyzing entity System
|
711
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
712
|
|
-INFO: [VRFC 10-307] analyzing entity BancRegistres
|
713
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
714
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
715
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
716
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
717
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
718
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
719
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
720
|
|
-INFO: [VRFC 10-307] analyzing entity MUX
|
721
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
722
|
|
-INFO: [VRFC 10-307] analyzing entity LC
|
723
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
724
|
|
-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
725
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
726
|
|
-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
727
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
728
|
|
-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
729
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
730
|
|
-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
731
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
732
|
|
-INFO: [VRFC 10-307] analyzing entity Pipeline
|
733
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
734
|
|
-INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
735
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
736
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
737
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
738
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
739
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
740
|
|
-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
741
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
742
|
|
-INFO: [VRFC 10-307] analyzing entity TestALU
|
743
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
744
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
745
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
746
|
|
-INFO: [VRFC 10-307] analyzing entity Test_LC
|
747
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
748
|
|
-INFO: [VRFC 10-307] analyzing entity Test_MUX
|
749
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
750
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
751
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
752
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
753
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
754
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
755
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
756
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
757
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
758
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
759
|
|
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
760
|
|
-INFO: [USF-XSim-3] XSim::Elaborate design
|
761
|
|
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
762
|
|
-Vivado Simulator 2016.4
|
763
|
|
-Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
764
|
|
-Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
765
|
|
-Using 2 slave threads.
|
766
|
|
-Starting static elaboration
|
767
|
|
-Completed static elaboration
|
768
|
|
-Starting simulation data flow analysis
|
769
|
|
-Completed simulation data flow analysis
|
770
|
|
-Time Resolution for simulation is 1ps
|
771
|
|
-Compiling package std.standard
|
772
|
|
-Compiling package std.textio
|
773
|
|
-Compiling package ieee.std_logic_1164
|
774
|
|
-Compiling package ieee.std_logic_arith
|
775
|
|
-Compiling package ieee.std_logic_unsigned
|
776
|
|
-Compiling package ieee.numeric_std
|
777
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
778
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
|
779
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
780
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
781
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
782
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
783
|
|
-Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
784
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
785
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
786
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
787
|
|
-Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
788
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
789
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
790
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
791
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
792
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
793
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
794
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
|
795
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
796
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
797
|
|
-Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
798
|
|
-Built simulation snapshot Test_Pipeline_behav
|
799
|
|
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
800
|
|
-Vivado Simulator 2016.4
|
801
|
|
-Time resolution is 1 ps
|
802
|
|
-relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
|
803
|
|
-restart
|
804
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
805
|
|
-run 100 us
|
806
|
|
-reset_run synth_1
|
807
|
|
-WARNING: [Vivado 12-1017] Problems encountered:
|
808
|
|
-1. Failed to delete one or more files in run directory C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1
|
809
|
|
-
|
810
|
|
-launch_runs synth_1 -jobs 2
|
811
|
|
-[Mon May 10 18:17:42 2021] Launched synth_1...
|
812
|
|
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1/runme.log
|
813
|
|
-launch_runs impl_1 -jobs 2
|
814
|
|
-[Mon May 10 18:20:21 2021] Launched impl_1...
|
815
|
|
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
|
816
|
|
-launch_runs impl_1 -to_step write_bitstream -jobs 2
|
817
|
|
-[Mon May 10 18:21:46 2021] Launched impl_1...
|
818
|
|
-Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
|
819
|
|
-open_hw
|
820
|
|
-connect_hw_server
|
821
|
|
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
822
|
|
-INFO: [Labtools 27-2222] Launching hw_server...
|
823
|
|
-INFO: [Labtools 27-2221] Launch Output:
|
824
|
|
-
|
825
|
|
-****** Xilinx hw_server v2016.4
|
826
|
|
- **** Build date : Jan 23 2017-19:37:29
|
827
|
|
- ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
828
|
|
-
|
829
|
|
-
|
830
|
|
-open_hw_target
|
831
|
|
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
|
832
|
|
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
|
833
|
|
-current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
834
|
|
-refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
|
835
|
|
-INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
836
|
|
-WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
|
837
|
|
-Resolution:
|
838
|
|
-1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
|
839
|
|
-2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
|
840
|
|
-set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
|
841
|
|
-set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
|
842
|
|
-program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
|
843
|
|
-INFO: [Labtools 27-3164] End of startup status: HIGH
|
844
|
|
-refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
845
|
|
-INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
846
|
|
-WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
|
847
|
|
-Resolution:
|
848
|
|
-1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
|
849
|
|
-2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
|
850
|
|
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
|
851
|
|
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
|
852
|
|
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
|
853
|
|
-WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
|
854
|
|
-restart
|
855
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
856
|
|
-run 100 us
|
857
|
|
-restart
|
858
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
859
|
|
-run 100 us
|
860
|
|
-save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
|
861
|
|
-ERROR: [Wavedata 42-440] There is no current wave configuration open to save
|
862
|
|
-save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
|
863
|
|
-ERROR: [Wavedata 42-440] There is no current wave configuration open to save
|
864
|
|
-save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
|
865
|
|
-ERROR: [Wavedata 42-440] There is no current wave configuration open to save
|
866
|
|
-restart
|
867
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
868
|
|
-run 100 us
|
869
|
|
-save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
|
870
|
|
-ERROR: [Wavedata 42-440] There is no current wave configuration open to save
|
871
|
|
-restart
|
872
|
|
-INFO: [Simtcl 6-17] Simulation restarted
|
873
|
|
-run 100 us
|
874
|
|
-save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
|
875
|
|
-ERROR: [Wavedata 42-440] There is no current wave configuration open to save
|
876
|
|
-save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
|
877
|
|
-ERROR: [Wavedata 42-440] There is no current wave configuration open to save
|
878
|
|
-save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
|
879
|
|
-ERROR: [Wavedata 42-440] There is no current wave configuration open to save
|
880
|
|
-ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA.
|
881
|
|
-Check cable connectivity and that the target board is powered up then
|
882
|
|
-use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
|
883
|
|
-ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
|
884
|
|
-close_hw
|
885
|
|
-relaunch_sim
|
886
|
|
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
887
|
|
-INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
888
|
|
-INFO: [USF-XSim-97] Finding global include files...
|
889
|
|
-INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
890
|
|
-INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
891
|
|
-INFO: [USF-XSim-2] XSim::Compile design
|
892
|
|
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
893
|
|
-"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
894
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
895
|
|
-INFO: [VRFC 10-307] analyzing entity ALU
|
896
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
|
897
|
|
-INFO: [VRFC 10-307] analyzing entity System
|
898
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
899
|
|
-INFO: [VRFC 10-307] analyzing entity BancRegistres
|
900
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
901
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
902
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
903
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
904
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
905
|
|
-INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
906
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
907
|
|
-INFO: [VRFC 10-307] analyzing entity MUX
|
908
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
909
|
|
-INFO: [VRFC 10-307] analyzing entity LC
|
910
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
911
|
|
-INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
912
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
913
|
|
-INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
914
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
915
|
|
-INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
916
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
917
|
|
-INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
918
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
919
|
|
-INFO: [VRFC 10-307] analyzing entity Pipeline
|
920
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
921
|
|
-INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
922
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
923
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
924
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
925
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
926
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
927
|
|
-INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
928
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
929
|
|
-INFO: [VRFC 10-307] analyzing entity TestALU
|
930
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
931
|
|
-INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
932
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
933
|
|
-INFO: [VRFC 10-307] analyzing entity Test_LC
|
934
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
935
|
|
-INFO: [VRFC 10-307] analyzing entity Test_MUX
|
936
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
937
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
938
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
939
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
940
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
941
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
942
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
943
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
944
|
|
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
945
|
|
-INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
946
|
|
-INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
|
947
|
|
-INFO: [USF-XSim-3] XSim::Elaborate design
|
948
|
|
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
949
|
|
-Vivado Simulator 2016.4
|
950
|
|
-Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
951
|
|
-Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
952
|
|
-Using 2 slave threads.
|
953
|
|
-Starting static elaboration
|
954
|
|
-Completed static elaboration
|
955
|
|
-Starting simulation data flow analysis
|
956
|
|
-Completed simulation data flow analysis
|
957
|
|
-Time Resolution for simulation is 1ps
|
958
|
|
-Compiling package std.standard
|
959
|
|
-Compiling package std.textio
|
960
|
|
-Compiling package ieee.std_logic_1164
|
961
|
|
-Compiling package ieee.std_logic_arith
|
962
|
|
-Compiling package ieee.std_logic_unsigned
|
963
|
|
-Compiling package ieee.numeric_std
|
964
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
965
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
|
966
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
967
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
968
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
969
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
970
|
|
-Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
971
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
972
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
973
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
974
|
|
-Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
975
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
976
|
|
-Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
977
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
978
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
979
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
980
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
981
|
|
-Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
|
982
|
|
-Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
983
|
|
-Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
984
|
|
-Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
985
|
|
-Built simulation snapshot Test_Pipeline_behav
|
986
|
|
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
987
|
|
-Vivado Simulator 2016.4
|
988
|
|
-Time resolution is 1 ps
|