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+----------------------------------------------------------------------------------
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+-- Company:
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+-- Engineer:
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+--
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+-- Create Date: 19.04.2021 16:57:41
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+-- Design Name:
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+-- Module Name: Pipeline - Behavioral
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+-- Project Name:
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+-- Target Devices:
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+-- Tool Versions:
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+-- Description:
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+--
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+-- Dependencies:
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+--
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+-- Revision:
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+-- Revision 0.01 - File Created
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+-- Additional Comments:
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+--
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+----------------------------------------------------------------------------------
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+
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+
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+library IEEE;
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+use IEEE.STD_LOGIC_1164.ALL;
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+
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+-- Uncomment the following library declaration if using
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+-- arithmetic functions with Signed or Unsigned values
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+--use IEEE.NUMERIC_STD.ALL;
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+
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+-- Uncomment the following library declaration if instantiating
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+-- any Xilinx leaf cells in this code.
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+--library UNISIM;
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+--use UNISIM.VComponents.all;
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+
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+entity Pipeline is
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+ Generic (Nb_bits : Natural := 8;
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+ Instruction_En_Memoire_Size : Natural := 29;
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+ Addr_Memoire_Instruction_Size : Natural := 3;
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+ Memoire_Instruction_Size : Natural := 8;
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+ Instruction_Bus_Size : Natural := 5;
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+ Nb_Instructions : Natural := 32;
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+ Nb_Registres : Natural := 16;
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+ Addr_registres_size : Natural := 4;
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+ Memoire_Size : Natural := 32;
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+ Adresse_mem_size : Natural := 5;
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+ Memoire_Adresses_Retour_Size : Natural := 16;
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+ Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
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+ Port (CLK : STD_LOGIC;
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+ RST : STD_LOGIC;
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+ STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
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+end Pipeline;
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+
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+architecture Behavioral of Pipeline is
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+
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+ component Etage1_LectureInstruction is
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+ Generic (Instruction_size_in_memory : Natural;
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+ Addr_size_mem_instruction : Natural;
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+ Mem_instruction_size : Natural;
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+ Nb_bits : Natural;
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+ Instruction_bus_size : Natural;
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+ Nb_registres : Natural;
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+ Mem_adresse_retour_size : Natural;
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+ Adresse_size_mem_adresse_retour : Natural;
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+ Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
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+ Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
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+ Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
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+ Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
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+ Code_Instruction_JMP : STD_LOGIC_VECTOR;
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+ Code_Instruction_JMZ : STD_LOGIC_VECTOR;
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+ Code_Instruction_CALL : STD_LOGIC_VECTOR;
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+ Code_Instruction_RET : STD_LOGIC_VECTOR;
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+ Code_Instruction_STOP : STD_LOGIC_VECTOR);
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+ Port ( CLK : in STD_LOGIC;
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+ RST : in STD_LOGIC;
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+ Z : in STD_LOGIC;
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+ A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
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+ end component;
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+
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+ component Etage2_5_Registres is
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+ Generic ( Nb_bits : Natural;
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+ Nb_registres : Natural;
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+ Addr_registres_size : Natural;
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+ Instruction_bus_size : Natural;
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+ Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
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+ Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
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+ Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
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+ Code_Instruction_PRI : STD_LOGIC_VECTOR;
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+ Code_Instruction_GET : STD_LOGIC_VECTOR);
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+ Port ( CLK : in STD_LOGIC;
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+ RST : in STD_LOGIC;
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+ STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
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+ OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
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+ IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
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+ end component;
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+
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+ component Etage3_Calcul is
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+ Generic ( Nb_bits : Natural;
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+ Instruction_bus_size : Natural;
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+ Bits_Controle_LC : STD_LOGIC_VECTOR;
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+ Bits_Controle_MUX : STD_LOGIC_VECTOR);
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+ Port ( RST : in STD_LOGIC;
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+ IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
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+ OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
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+ N : out STD_LOGIC;
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+ O : out STD_LOGIC;
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+ Z : out STD_LOGIC;
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+ C : out STD_LOGIC);
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+ end component;
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+
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+ component Etage4_Memoire is
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+ Generic ( Nb_bits : Natural;
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+ Mem_size : Natural;
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+ Adresse_mem_size : Natural;
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+ Instruction_bus_size : Natural;
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+ Mem_EBP_size : Natural;
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+ Adresse_size_mem_EBP : Natural;
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+ Bits_Controle_LC : STD_LOGIC_VECTOR;
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+ Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
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+ Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
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+ Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
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+ Code_Instruction_CALL : STD_LOGIC_VECTOR;
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+ Code_Instruction_RET : STD_LOGIC_VECTOR);
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+ Port ( CLK : in STD_LOGIC;
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+ RST : in STD_LOGIC;
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+ IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
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+ OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
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+ OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
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+ end component;
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+
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+ signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+ signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
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+ signal N : STD_LOGIC := '0';
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+ signal Z : STD_LOGIC := '0';
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+ signal O : STD_LOGIC := '0';
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+ signal C : STD_LOGIC := '0';
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+
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+ constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
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+ constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
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+ constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
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+ constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
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+ constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
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+ constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
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+ constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
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+ constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
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+ constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
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+ constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
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+ constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
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+ constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
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+ constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
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+ constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
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+ constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
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+ constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
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+
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+ constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
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+ constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
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+ constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
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+ constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
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+begin
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+ instance_Etage1 : Etage1_LectureInstruction
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+ generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
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+ Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
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+ Mem_instruction_size => Memoire_Instruction_Size,
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+ Nb_bits => Nb_bits,
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+ Instruction_bus_size => Instruction_Bus_Size,
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+ Nb_registres => Nb_Registres,
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+ Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
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+ Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
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+ Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
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+ Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
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+ Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
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+ Instructions_critiques_ecriture => Instructions_critiques_ecriture,
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+ Code_Instruction_JMP => Code_Instruction_JMP,
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+ Code_Instruction_JMZ => Code_Instruction_JMZ,
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+ Code_Instruction_CALL => Code_Instruction_CALL,
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+ Code_Instruction_RET => Code_Instruction_RET,
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+ Code_Instruction_STOP => Code_Instruction_STOP
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+ )
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+ port map (
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+ CLK => CLK,
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+ RST => RST,
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+ Z => Z,
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+ A => A_from_1,
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+ B => B_from_1,
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+ C => C_from_1,
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+ Instruction => Instruction_from_1
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+ );
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+
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+ instance_Etage2_5 : Etage2_5_Registres
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+ generic map( Nb_bits => Nb_bits,
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+ Nb_Registres => Nb_Registres,
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+ Addr_registres_size => Addr_registres_size,
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+ Instruction_bus_size => Instruction_Bus_Size,
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+ Bits_Controle_LC_5 => Bits_Controle_LC_5,
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+ Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
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+ Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
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+ Code_Instruction_PRI => Code_Instruction_PRI,
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+ Code_Instruction_GET => Code_Instruction_GET
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245
|
+ )
|
|
246
|
+ port map( CLK => CLK,
|
|
247
|
+ RST => RST,
|
|
248
|
+ STD_IN => STD_IN,
|
|
249
|
+ STD_OUT => STD_OUT,
|
|
250
|
+ IN_2_A => A_to_2,
|
|
251
|
+ IN_2_B => B_to_2,
|
|
252
|
+ IN_2_C => C_to_2,
|
|
253
|
+ IN_2_Instruction => Instruction_to_2,
|
|
254
|
+ OUT_2_A => A_from_2,
|
|
255
|
+ OUT_2_B => B_from_2,
|
|
256
|
+ OUT_2_C => C_from_2,
|
|
257
|
+ OUT_2_Instruction => Instruction_from_2,
|
|
258
|
+ IN_5_A => A_to_5,
|
|
259
|
+ IN_5_B => B_to_5,
|
|
260
|
+ IN_5_Instruction => Instruction_to_5
|
|
261
|
+ );
|
|
262
|
+
|
|
263
|
+ instance_Etage3 : Etage3_Calcul
|
|
264
|
+ generic map( Nb_bits => Nb_bits,
|
|
265
|
+ Instruction_bus_size => Instruction_Bus_Size,
|
|
266
|
+ Bits_Controle_LC => Bits_Controle_LC_3,
|
|
267
|
+ Bits_Controle_MUX => Bits_Controle_MUX_3
|
|
268
|
+ )
|
|
269
|
+ port map( RST => RST,
|
|
270
|
+ IN_A => A_to_3,
|
|
271
|
+ IN_B => B_to_3,
|
|
272
|
+ IN_C => C_to_3,
|
|
273
|
+ IN_Instruction => Instruction_to_3,
|
|
274
|
+ OUT_A => A_from_3,
|
|
275
|
+ OUT_B => B_from_3,
|
|
276
|
+ OUT_Instruction => Instruction_from_3,
|
|
277
|
+ N => N,
|
|
278
|
+ O => O,
|
|
279
|
+ Z => Z,
|
|
280
|
+ C => C
|
|
281
|
+ );
|
|
282
|
+
|
|
283
|
+ instance_Etage4 : Etage4_Memoire
|
|
284
|
+ generic map( Nb_bits => Nb_bits,
|
|
285
|
+ Mem_size => Memoire_Size,
|
|
286
|
+ Adresse_mem_size => Adresse_mem_size,
|
|
287
|
+ Instruction_bus_size => Instruction_Bus_Size,
|
|
288
|
+ Mem_EBP_size => Memoire_Adresses_Retour_Size,
|
|
289
|
+ Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
|
|
290
|
+ Bits_Controle_LC => Bits_Controle_LC_4,
|
|
291
|
+ Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
|
|
292
|
+ Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
|
|
293
|
+ Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT,
|
|
294
|
+ Code_Instruction_CALL => Code_Instruction_CALL,
|
|
295
|
+ Code_Instruction_RET => Code_Instruction_RET
|
|
296
|
+ )
|
|
297
|
+ port map( CLK => CLK,
|
|
298
|
+ RST => RST,
|
|
299
|
+ IN_A => A_to_4,
|
|
300
|
+ IN_B => B_to_4,
|
|
301
|
+ IN_Instruction => Instruction_to_4,
|
|
302
|
+ OUT_A => A_from_4,
|
|
303
|
+ OUT_B => B_from_4,
|
|
304
|
+ OUT_Instruction => Instruction_from_4
|
|
305
|
+ );
|
|
306
|
+
|
|
307
|
+ process
|
|
308
|
+ begin
|
|
309
|
+ wait until CLK'event and CLK = '1';
|
|
310
|
+ A_to_2 <= A_from_1;
|
|
311
|
+ B_to_2 <= B_from_1;
|
|
312
|
+ C_to_2 <= C_from_1;
|
|
313
|
+ Instruction_to_2 <= Instruction_from_1;
|
|
314
|
+
|
|
315
|
+ A_to_3 <= A_from_2;
|
|
316
|
+ B_to_3 <= B_from_2;
|
|
317
|
+ C_to_3 <= C_from_2;
|
|
318
|
+ Instruction_to_3 <= Instruction_from_2;
|
|
319
|
+
|
|
320
|
+ A_to_4 <= A_from_3;
|
|
321
|
+ B_to_4 <= B_from_3;
|
|
322
|
+ Instruction_to_4 <= Instruction_from_3;
|
|
323
|
+
|
|
324
|
+ A_to_5 <= A_from_4;
|
|
325
|
+ B_to_5 <= B_from_4;
|
|
326
|
+ Instruction_to_5 <= Instruction_from_4;
|
|
327
|
+ end process;
|
|
328
|
+end Behavioral;
|