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Travail en cours, bug adresse tick d'avant

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Paul Faure 2021-06-16 13:24:57 +02:00
parent 402e684461
commit 1442985687
5 changed files with 222 additions and 82 deletions
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82
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
View file

@ -37,34 +37,59 @@ end Test_Etage4_Memoire;
architecture Behavioral of Test_Etage4_Memoire is architecture Behavioral of Test_Etage4_Memoire is
component Etage4_Memoire is component Etage4_Memoire is
Generic ( Nb_bits : Natural; Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
Mem_size : Natural; Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
Instruction_bus_size : Natural; Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
Bits_Controle_LC : STD_LOGIC_VECTOR; Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR); Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
Port ( CLK : in STD_LOGIC; Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
RST : in STD_LOGIC; Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); Port ( CLK : in STD_LOGIC; -- Clock
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); RST : in STD_LOGIC; -- Reset
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
end component; end component;
signal my_CLK : STD_LOGIC := '0'; signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1'; signal my_RST : STD_LOGIC := '1';
signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0'); signal my_IN_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0'); signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
signal my_OUT_AddrRetour : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111"; constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111";
constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111"; constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1101111110101111111111";
constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000"; constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1001111011001111111111";
constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant CNULL : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant CWR : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant CCALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant CRET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant C0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant C1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant C2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant C3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant C5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant C7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant C12 : STD_LOGIC_VECTOR (7 downto 0) := "00001100";
constant C36 : STD_LOGIC_VECTOR (7 downto 0) := "00100100";
constant C54 : STD_LOGIC_VECTOR (7 downto 0) := "00110110";
constant C77 : STD_LOGIC_VECTOR (7 downto 0) := "01001101";
constant C100 : STD_LOGIC_VECTOR (7 downto 0) := "01100100";
constant CLK_period : time := 10 ns; constant CLK_period : time := 10 ns;
@ -72,11 +97,15 @@ begin
instance : Etage4_Memoire instance : Etage4_Memoire
generic map( Nb_bits => 8, generic map( Nb_bits => 8,
Mem_size => 256, Mem_size => 16,
Instruction_bus_size => 3, Adresse_mem_size => 4,
Instruction_bus_size => 5,
Bits_Controle_LC => Bits_Controle_LC, Bits_Controle_LC => Bits_Controle_LC,
Bits_Controle_MUX_IN => Bits_Controle_MUX_IN, Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT) Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET)
port map( CLK => my_CLK, port map( CLK => my_CLK,
RST => my_RST, RST => my_RST,
IN_A => my_IN_A, IN_A => my_IN_A,
@ -84,7 +113,8 @@ begin
IN_Instruction => my_IN_Instruction, IN_Instruction => my_IN_Instruction,
OUT_A => my_OUT_A, OUT_A => my_OUT_A,
OUT_B => my_OUT_B, OUT_B => my_OUT_B,
OUT_Instruction => my_OUT_Instruction); OUT_Instruction => my_OUT_Instruction,
OUT_AddrRetour => my_OUT_AddrRetour);
CLK_process :process CLK_process :process
begin begin
@ -96,9 +126,9 @@ begin
process process
begin begin
my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns; my_IN_A <= C0 after 0 ns, C0 after 5 ns, C1 after 15 ns, C2 after 25 ns, C77 after 35 ns, C0 after 45 ns, C54 after 55 ns, C0 after 65 ns, C0 after 75 ns;
my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns; my_IN_B <= C0 after 0 ns, C36 after 5 ns, C5 after 15 ns, C7 after 25 ns, C3 after 35 ns, C12 after 45 ns, C1 after 55 ns, C100 after 65 ns, C0 after 75 ns;
my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns; my_IN_Instruction <= CNULL after 0 ns, CWR after 5 ns, CWR after 15 ns, CWR after 25 ns, CCALL after 35 ns, CWR after 45 ns, CCALL after 55 ns, CWR after 65 ns, CRET after 75 ns, CRET after 85 ns, CNULL after 95 ns;
my_RST <= '0' after 125 ns; my_RST <= '0' after 125 ns;
wait; wait;
end process; end process;

95
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
View file

@ -29,8 +29,6 @@ entity Etage4_Memoire is
Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables) Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd) Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd) Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd) Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
@ -44,7 +42,8 @@ entity Etage4_Memoire is
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
end Etage4_Memoire; end Etage4_Memoire;
architecture Structural of Etage4_Memoire is architecture Structural of Etage4_Memoire is
@ -52,26 +51,18 @@ architecture Structural of Etage4_Memoire is
Generic (Nb_bits : Natural; Generic (Nb_bits : Natural;
Addr_size : Natural; Addr_size : Natural;
Mem_size : Natural); Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
RW : in STD_LOGIC; RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
RST : in STD_LOGIC; CALL : in STD_LOGIC; -- '1' -> CALL en cours
CLK : in STD_LOGIC; IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
end component; RET : in STD_LOGIC; -- '1' -> RET en cours
OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
component MemoireAdressesRetour is OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
Generic (Nb_bits : Natural; RST : in STD_LOGIC; -- Reset
Addr_size : Natural; CLK : in STD_LOGIC; -- Clock
Mem_size : Natural); D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end component; end component;
component LC is component LC is
@ -94,7 +85,9 @@ architecture Structural of Etage4_Memoire is
signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- EBP (offset à ajouter à l'adresse) signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- EBP (offset à ajouter à l'adresse)
signal Last_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Ancien EBP, valeur récupérée en mémoire lors d'un RET
signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Nouvelle valeur d'EBP, a stocker lors d'un CALL (Cf fonctionnement MemoireAdressesRetour.vhd) signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Nouvelle valeur d'EBP, a stocker lors d'un CALL (Cf fonctionnement MemoireAdressesRetour.vhd)
signal IN_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- EBP à stocker ne mémoire (ajout de 0)
signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse entrante dans le composant de mémoire de donnees signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse entrante dans le composant de mémoire de donnees
signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Sortie du mux de choix d'adresse entre A et B signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Sortie du mux de choix d'adresse entre A et B
@ -106,11 +99,9 @@ architecture Structural of Etage4_Memoire is
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Signal interne signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Signal interne
-- Signaux de la memoire de contexte -- Signaux de contrôle de la mémoire
signal R_Aux : STD_LOGIC := '0'; signal CALL_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0'; signal RET_Aux : STD_LOGIC := '0';
signal E : STD_LOGIC;
signal F : STD_LOGIC;
begin begin
@ -152,27 +143,18 @@ begin
generic map (Nb_bits => Nb_bits, generic map (Nb_bits => Nb_bits,
Addr_size => Adresse_mem_size, Addr_size => Adresse_mem_size,
Mem_size => Mem_size) Mem_size => Mem_size)
port map ( Addr => Addr_MemoireDonnees, port map (Addr => Addr_MemoireDonnees,
RW => Commande_MemoireDonnees(0), RW => Commande_MemoireDonnees(0),
D_IN => IN_B, D_IN => IN_B,
RST => RST, CALL => CALL_Aux,
CLK => CLK, IN_EBP => IN_EBP,
D_OUT => Sortie_MemoireDonnees); IN_AddrRet => IN_A,
RET => RET_Aux,
instance_MemoireEBP : MemoireAdressesRetour OUT_EBP => Last_EBP,
generic map (Nb_bits => Adresse_mem_size, OUT_AddrRet => OUT_AddrRetour,
Addr_size => Adresse_size_mem_EBP, RST => RST,
Mem_size => Mem_EBP_size CLK => CLK,
) D_OUT => Sortie_MemoireDonnees);
port map ( R => R_Aux,
W => W_Aux,
D_IN => New_EBP,
RST => RST,
CLK => CLK,
D_OUT => EBP,
E => E,
F => F
);
OUT_A <= (others => '0') when RST = '0' else OUT_A <= (others => '0') when RST = '0' else
IN_A; IN_A;
@ -181,12 +163,19 @@ begin
OUT_Instruction <= (others => '0') when RST = '0' else OUT_Instruction <= (others => '0') when RST = '0' else
IN_Instruction; IN_Instruction;
-- Controle de la mémoire de contexte (ici aussi un LC aurait été disproportionné) -- Controle de la gestion des appels de fonctions (ici aussi un LC aurait été disproportionné)
R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else RET_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
'0'; '0';
W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
'0'; '0';
New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
EBP <= New_EBP when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_CALL else
Last_EBP (Adresse_mem_size - 1 downto 0) when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_RET else
(others => '0') when RST = '0' else
EBP;
IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP;
Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP; Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0);
end Structural; end Structural;

14
Processeur.srcs/sources_1/new/MemoireDonnees.vhd
View file

@ -23,6 +23,12 @@ entity MemoireDonnees is
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write) RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0) D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
CALL : in STD_LOGIC; -- '1' -> CALL en cours
IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
RET : in STD_LOGIC; -- '1' -> RET en cours
OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
RST : in STD_LOGIC; -- Reset RST : in STD_LOGIC; -- Reset
CLK : in STD_LOGIC; -- Clock CLK : in STD_LOGIC; -- Clock
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
@ -37,7 +43,13 @@ begin
if (RST = '0') then if (RST = '0') then
MEMORY <= (others => '0'); MEMORY <= (others => '0');
else else
if (RW = '0') then if (CALL = '1') then
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP;
MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet;
elsif (RET = '1') then
OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2));
OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
elsif (RW = '0') then
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN; MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
end if; end if;
end if; end if;

10
Processeur.xpr
View file

@ -32,7 +32,7 @@
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/> <Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="235"/> <Option Name="WTXSimLaunchSim" Val="287"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@ -233,9 +233,14 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Test_Pipeline"/> <Option Name="TopModule" Val="Test_Etage4_Memoire"/>
<Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>
@ -243,6 +248,7 @@
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/>
</Config> </Config>
</FileSet> </FileSet>
</FileSets> </FileSets>

103
SimulationsConfig/Test_Etage4_Memoire_behav.wcfg Normal file
View file

@ -0,0 +1,103 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="Test_Etage4_Memoire_behav.wdb" id="1">
<top_modules>
<top_module name="Test_Etage4_Memoire" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="79200001fs"></ZoomEndTime>
<Cursor1Time time="50600000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="146"></NameColumnWidth>
<ValueColumnWidth column_width="327"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="18" />
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_CLK">
<obj_property name="ElementShortName">my_CLK</obj_property>
<obj_property name="ObjectShortName">my_CLK</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_RST">
<obj_property name="ElementShortName">my_RST</obj_property>
<obj_property name="ObjectShortName">my_RST</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_A">
<obj_property name="ElementShortName">my_IN_A[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B">
<obj_property name="ElementShortName">my_IN_B[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_Instruction">
<obj_property name="ElementShortName">my_IN_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_Instruction[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_A">
<obj_property name="ElementShortName">my_OUT_A[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_A[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_B">
<obj_property name="ElementShortName">my_OUT_B[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_B[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_Instruction">
<obj_property name="ElementShortName">my_OUT_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_Instruction[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_AddrRetour">
<obj_property name="ElementShortName">my_OUT_AddrRetour[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_AddrRetour[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/EBP">
<obj_property name="ElementShortName">EBP[3:0]</obj_property>
<obj_property name="ObjectShortName">EBP[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Last_EBP">
<obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
<obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/OUT_EBP">
<obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
<obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
<obj_property name="ElementShortName">MEMORY[127:0]</obj_property>
<obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
<obj_property name="ElementShortName">RW</obj_property>
<obj_property name="ObjectShortName">RW</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
<obj_property name="ElementShortName">Addr[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
<obj_property name="ElementShortName">D_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/CALL">
<obj_property name="ElementShortName">CALL</obj_property>
<obj_property name="ObjectShortName">CALL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RET">
<obj_property name="ElementShortName">RET</obj_property>
<obj_property name="ObjectShortName">RET</obj_property>
</wvobject>
</wave_config>