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@@ -1,9 +1,9 @@
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<?xml version="1.0" encoding="UTF-8"?>
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-<!-- Product Version: Vivado v2016.4 (64-bit) -->
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+<!-- Product Version: Vivado v2018.2 (64-bit) -->
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<!-- -->
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-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
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+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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-<Project Version="7" Minor="17" Path="/home/paulfaure/Documents/4A/PSI/Processeur/Processeur.xpr">
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+<Project Version="7" Minor="38" Path="/home/pfaure/Documents/PSI/Processeur/Processeur.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
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@@ -13,6 +13,7 @@
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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+ <Option Name="ProjectType" Val="Default"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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- <Option Name="IPUserFilesDir" Val="$PPRDIR/Processeur.ip_user_files"/>
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- <Option Name="IPStaticSourceDir" Val="$PPRDIR/Processeur.ip_user_files/ipstatic"/>
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+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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+ <Option Name="DSAVendor" Val="xilinx"/>
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<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="DSANumComputeUnits" Val="16"/>
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<Option Name="WTXSimLaunchSim" Val="420"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="64"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Simulator Name="IES">
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<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
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</Simulator>
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+ <Simulator Name="Xcelium">
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+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
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+ </Simulator>
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<Simulator Name="VCS">
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<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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</Simulator>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="10">
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- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
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+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
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<Step Id="synth_design"/>
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</Strategy>
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+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
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+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="false">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
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<Step Id="init_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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</Runs>
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+ <Board/>
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</Project>
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