diff --git a/Interpreteur/src/.idea/.gitignore b/Interpreteur/src/.idea/.gitignore new file mode 100644 index 0000000..73f69e0 --- /dev/null +++ b/Interpreteur/src/.idea/.gitignore @@ -0,0 +1,8 @@ +# Default ignored files +/shelf/ +/workspace.xml +# Datasource local storage ignored files +/dataSources/ +/dataSources.local.xml +# Editor-based HTTP Client requests +/httpRequests/ diff --git a/Interpreteur/src/.idea/modules.xml b/Interpreteur/src/.idea/modules.xml new file mode 100644 index 0000000..f669a0e --- /dev/null +++ b/Interpreteur/src/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/Interpreteur/src/.idea/src.iml b/Interpreteur/src/.idea/src.iml new file mode 100644 index 0000000..bc2cd87 --- /dev/null +++ b/Interpreteur/src/.idea/src.iml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/Interpreteur/src/.idea/vcs.xml b/Interpreteur/src/.idea/vcs.xml new file mode 100644 index 0000000..b2bdec2 --- /dev/null +++ b/Interpreteur/src/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/Interpreteur/src/instructions.c b/Interpreteur/src/instructions.c index 48b64f0..27be068 100755 --- a/Interpreteur/src/instructions.c +++ b/Interpreteur/src/instructions.c @@ -66,6 +66,9 @@ void asm_add_2(char ins, int arg1, int arg2) { void asm_add_1(char ins, int arg1) { asm_add_3(ins, arg1, 0, 0); } +void asm_add_0(char ins) { + asm_add_3(ins, 0, 0, 0); +} void asm_run() { int ip = 0; diff --git a/Interpreteur/src/interpreter.y b/Interpreteur/src/interpreter.y index 7fefe8b..2def9a5 100755 --- a/Interpreteur/src/interpreter.y +++ b/Interpreteur/src/interpreter.y @@ -12,7 +12,7 @@ int nb; } -%token tADD tMUL tSOU tDIV tCOP tAFC tJMP tJMF tINF tSUP tEQU tPRI tAFCA tWR tREAD +%token tADD tMUL tSOU tDIV tCOP tAFC tJMP tJMF tINF tSUP tEQU tPRI tAFCA tWR tREAD tCOPR tCALL tRET %token tNB @@ -53,12 +53,19 @@ Instruction: {asm_add_3(EQU, $2, $3, $4);} | tPRI tNB {asm_add_1(PRI, $2);} - | tAFCA tNB tNB + | tAFCA tNB tNB {asm_add_2(AFCA, $2, $3);} | tWR tNB tNB {asm_add_2(WR, $2, $3);} | tREAD tNB tNB {asm_add_2(READ, $2, $3);} + | tCOPR tNB tNB + {asm_add_2(COPR, $2, $3);} + | tCALL tNB tNB tNB + {asm_add_3(READ, $2, $3, $4);} + | tRET + {asm_add_0(RET);} + ;