From 93c6be6a07a9230d4bf7575e6bf182211a942de0 Mon Sep 17 00:00:00 2001 From: pfaure Date: Sat, 19 Sep 2020 17:32:25 +0200 Subject: [PATCH] =?UTF-8?q?Version=20Fonctionnelle=20:=20Activit=C3=A9=201?= =?UTF-8?q?=20termin=C3=A9e.=20MAJ=20:=20.gitignore=20ajout=20*.lst?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 3 +- MDK-ARM/Project.uvoptx | 142 ++++++++++++++++++++++++++++++++++++++-- MDK-ARM/Project.uvprojx | 14 ++-- MyDrivers/MyTimer.c | 99 ++++++++++++++++++++++++++++ Services/Chrono.c | 13 ++-- Src/main.c | 24 ++++++- 6 files changed, 278 insertions(+), 17 deletions(-) diff --git a/.gitignore b/.gitignore index 7d3774e..b6b0afe 100644 --- a/.gitignore +++ b/.gitignore @@ -2,4 +2,5 @@ MDK-ARM/DebugConfig/ MDK-ARM/*.scvd MDK-ARM/NUCLEO-F103RB/ MDK-ARM/*.uvguix.* -MDK-ARM/RTE/ \ No newline at end of file +MDK-ARM/RTE/ +*.lst \ No newline at end of file diff --git a/MDK-ARM/Project.uvoptx b/MDK-ARM/Project.uvoptx index b9bc961..1b8a968 100644 --- a/MDK-ARM/Project.uvoptx +++ b/MDK-ARM/Project.uvoptx @@ -101,6 +101,8 @@ 0 0 1 + 0 + 0 5 @@ -190,8 +192,13 @@ + + + + 1 + 0 0 2 10000000 @@ -279,6 +286,8 @@ 0 0 1 + 0 + 0 5 @@ -296,7 +305,7 @@ 0 DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + (1010=75,104,451,661,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=859,49,1453,800,0)(131=828,47,1422,798,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) 0 @@ -329,7 +338,120 @@ -U-O142 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) - + + + 0 + 0 + 32 + 1 +
134218060
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Services\Chrono.c + + \\NUCLEO_F103RB\../Services/Chrono.c\32 + + + 1 + 0 + 64 + 1 +
134219162
+ 0 + 0 + 0 + 0 + 0 + 1 + ../Src/main.c + + \\NUCLEO_F103RB\../Src/main.c\64 + + + 2 + 0 + 117 + 1 +
134218136
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Services\Chrono.c + + \\NUCLEO_F103RB\../Services/Chrono.c\117 + + + 3 + 0 + 20 + 1 +
134218220
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\MyDrivers\MyTimer.c + + \\NUCLEO_F103RB\../MyDrivers/MyTimer.c\20 + + + 4 + 0 + 40 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + startup_stm32f103xb.s + + + + + + + 0 + 1 + TIM1 + + + 1 + 1 + GPIOB + + + 2 + 1 + SPI1 + + + 3 + 1 + USART1 + + + 4 + 1 + TIM2 + + + 5 + 1 + Chrono_Time + + 0 @@ -368,8 +490,20 @@ + + + + + + + 0 + `TIM2_CNT + FF00000000000000000000000000E0FFFFFFEF410000000000000000000000000000000054494D325F434E540000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F1800000000000000000000000000000000000000CE020008 + + 1 + 0 0 2 10000000 @@ -407,7 +541,7 @@ 2 2 1 - 0 + 1 0 0 ..\Services\Chrono.c @@ -427,7 +561,7 @@ 3 3 1 - 0 + 1 0 0 ..\MyDrivers\MyTimer.c diff --git a/MDK-ARM/Project.uvprojx b/MDK-ARM/Project.uvprojx index c7613f3..4dcfee4 100644 --- a/MDK-ARM/Project.uvprojx +++ b/MDK-ARM/Project.uvprojx @@ -11,11 +11,12 @@ 0x4 ARM-ADS 5060422::V5.06 update 4 (build 422)::ARMCC + 0 STM32F103RB STMicroelectronics - Keil.STM32F1xx_DFP.2.2.0 + Keil.STM32F1xx_DFP.2.3.0 http://www.keil.com/pack/ IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") @@ -183,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -323,6 +325,7 @@ 0 0 0 + 0 0 1 1 @@ -460,12 +463,13 @@ Simulateur 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32F103RB STMicroelectronics - Keil.STM32F1xx_DFP.2.2.0 + Keil.STM32F1xx_DFP.2.3.0 http://www.keil.com/pack/ IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") @@ -633,6 +637,7 @@ 0 0 0 + 0 0 0 8 @@ -760,7 +765,7 @@ 1 - 4 + 1 0 0 1 @@ -773,6 +778,7 @@ 0 0 0 + 0 0 1 1 diff --git a/MyDrivers/MyTimer.c b/MyDrivers/MyTimer.c index bdfc3fd..d27dc73 100644 --- a/MyDrivers/MyTimer.c +++ b/MyDrivers/MyTimer.c @@ -11,3 +11,102 @@ */ #include "stm32f103xb.h" + +void (* ptrfonc1)(void); +void (* ptrfonc2)(void); +void (* ptrfonc3)(void); +void (* ptrfonc4)(void); + +void MyTimer_Conf(TIM_TypeDef * Timer,int Arr, int Psc) { + int valid = 1; + if (Timer == TIM1) { + RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; + } else if (Timer == TIM2) { + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; + } else if (Timer == TIM3) { + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; + } else if (Timer == TIM4) { + RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; + } else { + valid = 0; + } + + if (valid) { + Timer->ARR = Arr; + Timer->PSC = Psc; + } +} + +void MyTimer_Start(TIM_TypeDef * Timer) { + Timer->CR1 |= TIM_CR1_CEN; +} + +void MyTimer_Stop(TIM_TypeDef * Timer) { + Timer->CR1 &= ~TIM_CR1_CEN; +} + +void MyTimer_IT_Conf(TIM_TypeDef * Timer, void (*IT_function) (void),int Prio) { + if (Timer == TIM1) { + NVIC->ISER[0] = NVIC->ISER[0] | (1 << 25); + NVIC->IP[25] = NVIC->IP[25] | (Prio << 4); + ptrfonc1 = IT_function; + } else if (Timer == TIM2) { + NVIC->ISER[0] = NVIC->ISER[0] | (1 << 28); + NVIC->IP[28] = NVIC->IP[28] | (Prio << 4); + ptrfonc2 = IT_function; + } else if (Timer == TIM3) { + NVIC->ISER[0] = NVIC->ISER[0] | (1 << 29); + NVIC->IP[29] = NVIC->IP[29] | (Prio << 4); + ptrfonc3 = IT_function; + } else if (Timer == TIM4) { + NVIC->ISER[0] = NVIC->ISER[0] | (1 << 30); + NVIC->IP[30] = NVIC->IP[30] | (Prio << 4); + ptrfonc4 = IT_function; + } +} + + +void MyTimer_IT_Enable(TIM_TypeDef * Timer) { + if (Timer == TIM1) { + TIM1->DIER |= TIM_DIER_UIE; + } else if (Timer == TIM2) { + TIM2->DIER |= TIM_DIER_UIE; + } else if (Timer == TIM3) { + TIM3->DIER |= TIM_DIER_UIE; + } else if (Timer == TIM4) { + TIM4->DIER |= TIM_DIER_UIE; + } +} + + +void MyTimer_IT_Disable(TIM_TypeDef * Timer) { + if (Timer == TIM1) { + TIM1->DIER &= ~TIM_DIER_UIE; + } else if (Timer == TIM2) { + TIM2->DIER &= ~TIM_DIER_UIE; + } else if (Timer == TIM3) { + TIM3->DIER &= ~TIM_DIER_UIE; + } else if (Timer == TIM4) { + TIM4->DIER &= ~TIM_DIER_UIE; + } +} + + +void TIM1_UP_IRQHandler(void) { + TIM1->SR &= ~TIM_SR_UIF; + (*ptrfonc1)(); +} + +void TIM2_IRQHandler(void) { + TIM2->SR &= ~TIM_SR_UIF; + (*ptrfonc2)(); +} + +void TIM3_IRQHandler(void) { + TIM3->SR &= ~TIM_SR_UIF; + (*ptrfonc3)(); +} +void TIM4_IRQHandler(void) { + TIM4->SR &= ~TIM_SR_UIF; + (*ptrfonc4)(); +} \ No newline at end of file diff --git a/Services/Chrono.c b/Services/Chrono.c index 975d170..19b9c53 100644 --- a/Services/Chrono.c +++ b/Services/Chrono.c @@ -37,13 +37,13 @@ void Chrono_Conf(TIM_TypeDef * Timer) Chrono_Timer=Timer; // Réglage Timer pour un débordement à 10ms - //MyTimer_Conf(Chrono_Timer... + MyTimer_Conf(Chrono_Timer, 99, 7199); // Réglage interruption du Timer avec callback : Chrono_Task_10ms() - //MyTimer_IT_Conf(.. + MyTimer_IT_Conf(Chrono_Timer, Chrono_Task_10ms, 7); // Validation IT - //MyTimer_IT_Enable(.. + MyTimer_IT_Enable(Chrono_Timer); } @@ -57,7 +57,8 @@ void Chrono_Conf(TIM_TypeDef * Timer) */ void Chrono_Start(void) { - //MyTimer_Start(..); + // Lancement du Timer + MyTimer_Start(Chrono_Timer); } @@ -69,7 +70,7 @@ void Chrono_Start(void) */ void Chrono_Stop(void) { - //MyTimer_Stop(.. + MyTimer_Stop(Chrono_Timer); } @@ -82,7 +83,7 @@ void Chrono_Stop(void) void Chrono_Reset(void) { // Arrêt Chrono - //MyTimer_Stop(.. + MyTimer_Stop(Chrono_Timer); // Reset Time Chrono_Time.Hund=0; diff --git a/Src/main.c b/Src/main.c index 8566001..03fefd6 100644 --- a/Src/main.c +++ b/Src/main.c @@ -32,13 +32,33 @@ void SystemClock_Config(void); * @retval None */ int main(void) -{ +{ /* Configure the system clock to 72 MHz */ SystemClock_Config(); + + /* DU BLABLA POUR JOUER AU DéBUT + TIM1->CR2|=0x1 ; + TIM1->CR2=0xFFFF ; + TIM1->CR2 &= ~0x0040 ; + TIM1->CR2=0xFFFF ; + TIM1->CR2&=~(1<<6) ; + GPIOB->CRL=(0xFFFF ) ; + GPIOB->CRL&=~(0xF<<8) ; + GPIOB->CRL|= (0x5<<8) ; + GPIOB->ODR|=GPIO_ODR_ODR1 ; + SPI1->CR1 |= 0x2; + + SPI1->CR1 = 0xFFFF; + SPI1->CR1 &= ~SPI_CR1_DFF; + USART1->CR2 = 0xFFFFFFFF; + USART1->CR2 &= ~USART_CR2_STOP; + USART1->CR2 |= (0x2 << USART_CR2_STOP_Pos);*/ + + /* Add your application code here */ // Configuration chronomètre - Chrono_Conf(TIM2); + Chrono_Conf(TIM1); // Lancement chronomètre Chrono_Start();