53 lines
1.3 KiB
VHDL
53 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.04.2021 22:51:31
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-- Design Name:
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-- Module Name: test_Compteur - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity test_Compteur is
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-- Port ( );
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end test_Compteur;
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architecture Behavioral of test_Compteur is
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component Compteur is
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Port ( CK : in STD_LOGIC;
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RST : in STD_LOGIC;
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SENS : in STD_LOGIC;
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LOAD : in STD_LOGIC;
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EN : in STD_LOGIC;
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Din : in STD_LOGIC_VECTOR (7 downto 0);
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Dout : out STD_LOGIC_VECTOR (7 downto 0));
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end component;
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signal CK
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begin
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end Behavioral;
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