123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104 |
- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
- --------------------------------------------------------------------------------------
- | Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
- | Date : Fri Apr 09 23:16:08 2021
- | Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
- | Command : report_control_sets -verbose -file GPIO_demo_control_sets_placed.rpt
- | Design : GPIO_demo
- | Device : xc7a35t
- --------------------------------------------------------------------------------------
-
- Control Set Information
-
- Table of Contents
- -----------------
- 1. Summary
- 2. Flip-Flop Distribution
- 3. Detailed Control Set Information
-
- 1. Summary
- ----------
-
- +----------------------------------------------------------+-------+
- | Status | Count |
- +----------------------------------------------------------+-------+
- | Number of unique control sets | 36 |
- | Unused register locations in slices containing registers | 94 |
- +----------------------------------------------------------+-------+
-
-
- 2. Flip-Flop Distribution
- -------------------------
-
- +--------------+-----------------------+------------------------+-----------------+--------------+
- | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
- +--------------+-----------------------+------------------------+-----------------+--------------+
- | No | No | No | 132 | 57 |
- | No | No | Yes | 0 | 0 |
- | No | Yes | No | 226 | 57 |
- | Yes | No | No | 105 | 40 |
- | Yes | No | Yes | 0 | 0 |
- | Yes | Yes | No | 115 | 32 |
- +--------------+-----------------------+------------------------+-----------------+--------------+
-
-
- 3. Detailed Control Set Information
- -----------------------------------
-
- +-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
- | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
- +-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk_inter0 | 1 | 4 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/data_inter0 | 1 | 4 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_overflow_i_1_n_0 | | 2 | 4 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/shift_frame | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/reset_bit_count | 1 | 4 |
- | CLK_IBUF_BUFG | eqOp2_in | tmrVal[3]_i_1_n_0 | 2 | 4 |
- | CLK_IBUF_BUFG | | sendStr[3][0] | 1 | 5 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_1_n_0 | 2 | 7 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/g0_b0_n_0 | | 2 | 7 |
- | CLK_IBUF_BUFG | uartSend | | 2 | 7 |
- | CLK_IBUF_BUFG | uartData | | 6 | 7 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/load_rx_data_reg_n_0 | | 2 | 8 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_inc[7]_i_1_n_0 | | 3 | 8 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_inc[7]_i_1_n_0 | | 4 | 8 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_1_n_0 | | 2 | 10 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_new_reg_n_0 | | 3 | 11 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_1_n_0 | 3 | 11 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/eqOp4_in | Inst_vga_ctrl/v_cntr_reg0 | 3 | 12 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/vga_red_reg[3]_i_1_n_0 | 2 | 12 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/eqOp4_in | 3 | 12 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_new_reg_n_0 | | 4 | 12 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_1_n_0 | 4 | 14 |
- | CLK_IBUF_BUFG | | Inst_UART_TX_CTRL/bitTmr[0]_i_1_n_0 | 4 | 14 |
- | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[4][0]_i_1_n_0 | 4 | 16 |
- | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[1][0]_i_1_n_0 | 4 | 16 |
- | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[2][0]_i_1_n_0 | 4 | 16 |
- | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[3][0]_i_1_n_0 | 4 | 16 |
- | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[0][0]_i_1_n_0 | 4 | 16 |
- | CLK_IBUF_BUFG | | | 10 | 17 |
- | CLK_IBUF_BUFG | | reset_cntr0 | 5 | 18 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/v_sync_reg | | 10 | 23 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/reset_timeout_cnt_reg_n_0 | 7 | 24 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/reset_periodic_check_cnt | 6 | 26 |
- | CLK_IBUF_BUFG | | tmrCntr0 | 7 | 27 |
- | CLK_IBUF_BUFG | uartData | strIndex0 | 8 | 31 |
- | CLK_IBUF_BUFG | Inst_UART_TX_CTRL/txBit_i_1_n_0 | Inst_UART_TX_CTRL/READY | 9 | 32 |
- | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | | 47 | 115 |
- +-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
-
-
- +--------+-----------------------+
- | Fanout | Number of ControlSets |
- +--------+-----------------------+
- | 4 | 5 |
- | 5 | 1 |
- | 7 | 4 |
- | 8 | 3 |
- | 10 | 1 |
- | 11 | 2 |
- | 12 | 4 |
- | 14 | 2 |
- | 16+ | 14 |
- +--------+-----------------------+
-
|