*** Running vivado with args -log GPIO_demo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GPIO_demo.tcl ****** Vivado v2016.4 (64-bit) **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017 **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source GPIO_demo.tcl -notrace Command: synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy none -directive RuntimeOptimized -fsm_extraction off Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3172 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 350.121 ; gain = 140.289 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'GPIO_demo' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70] Parameter DEBNC_CLOCKS bound to: 65536 - type: integer Parameter PORT_WIDTH bound to: 5 - type: integer INFO: [Synth 8-3491] module 'debouncer' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:42' bound to instance 'Inst_btn_debounce' of component 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:320] INFO: [Synth 8-638] synthesizing module 'debouncer' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50] Parameter DEBNC_CLOCKS bound to: 65536 - type: integer Parameter PORT_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'debouncer' (1#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/debouncer.vhd:50] INFO: [Synth 8-3491] module 'UART_TX_CTRL' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:42' bound to instance 'Inst_UART_TX_CTRL' of component 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:450] INFO: [Synth 8-638] synthesizing module 'UART_TX_CTRL' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50] INFO: [Synth 8-256] done synthesizing module 'UART_TX_CTRL' (2#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/UART_TX_CTRL.vhd:50] INFO: [Synth 8-3491] module 'vga_ctrl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:38' bound to instance 'Inst_vga_ctrl' of component 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:465] INFO: [Synth 8-638] synthesizing module 'vga_ctrl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50] INFO: [Synth 8-3491] module 'clk_wiz_0' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:74' bound to instance 'clk_wiz_0_inst' of component 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:197] INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83] INFO: [Synth 8-3491] module 'clk_wiz_0_clk_wiz' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:74' bound to instance 'U0' of component 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:98] INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 10.125000 - type: float Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float Parameter CLKOUT0_DIVIDE_F bound to: 9.375000 - type: float Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: float Parameter REF_JITTER2 bound to: 0.000000 - type: float Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:125] INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:187] INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:194] INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (3#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0_clk_wiz.vhd:83] INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (4#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/clk_wiz_0.vhd:83] Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer Parameter CHECK_PERIOD_MS bound to: 500 - type: integer Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer INFO: [Synth 8-3491] module 'MouseCtl' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:179' bound to instance 'Inst_MouseCtl' of component 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:207] INFO: [Synth 8-638] synthesizing module 'MouseCtl' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208] Parameter SYSCLK_FREQUENCY_HZ bound to: 108000000 - type: integer Parameter CHECK_PERIOD_MS bound to: 500 - type: integer Parameter TIMEOUT_PERIOD_MS bound to: 100 - type: integer INFO: [Synth 8-3491] module 'Ps2Interface' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:152' bound to instance 'Inst_Ps2Interface' of component 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:370] INFO: [Synth 8-638] synthesizing module 'Ps2Interface' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180] INFO: [Synth 8-256] done synthesizing module 'Ps2Interface' (5#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/Ps2Interface.vhd:180] INFO: [Synth 8-256] done synthesizing module 'MouseCtl' (6#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseCtl.vhd:208] INFO: [Synth 8-3491] module 'MouseDisplay' declared at 'C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:99' bound to instance 'Inst_MouseDisplay' of component 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:334] INFO: [Synth 8-638] synthesizing module 'MouseDisplay' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129] WARNING: [Synth 8-614] signal 'ypos' is read in the process but is not in the sensitivity list [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:197] INFO: [Synth 8-256] done synthesizing module 'MouseDisplay' (7#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:129] INFO: [Synth 8-256] done synthesizing module 'vga_ctrl' (8#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/vga_ctrl.vhd:50] INFO: [Synth 8-256] done synthesizing module 'GPIO_demo' (9#1) [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:70] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 391.957 ; gain = 182.125 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 391.957 ; gain = 182.125 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc] Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/GPIO_demo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/GPIO_demo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 692.656 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcpg236-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- INFO: [Synth 8-5544] ROM "READY" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5545] ROM "txState" won't be mapped to RAM because address size (31) is larger than maximum supported(25) INFO: [Synth 8-5544] ROM "bitIndex" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5546] ROM "busy" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "delay_100us_counter_enable" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "delay_20us_counter_enable" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "delay_63clk_counter_enable" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "reset_bit_count" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "periodic_check_tick" won't be mapped to RAM because address size (26) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "timeout" won't be mapped to RAM because it is too sparse INFO: [Synth 8-4471] merging register 'green_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:238] INFO: [Synth 8-4471] merging register 'blue_out_reg[3:0]' into 'red_out_reg[3:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:239] INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213] INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214] INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213] INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214] INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:213] INFO: [Synth 8-41] '_-' operator could not be merged with '+' operator due to loss of accuracy [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/MouseDisplay.vhd:214] INFO: [Synth 8-4471] merging register 'sendStr_reg[15][7:0]' into 'sendStr_reg[3][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414] INFO: [Synth 8-4471] merging register 'sendStr_reg[25][7:0]' into 'sendStr_reg[24][7:0]' [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/hdl/GPIO_Demo.vhd:414] INFO: [Synth 8-5544] ROM "sendStr[0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[1]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[2]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[3]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[4]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[5]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[6]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[7]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[8]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[9]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[10]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[11]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[12]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[13]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[14]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[18]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[19]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[21]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[22]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[23]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "sendStr[24]" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "strEnd" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "strIndex" won't be mapped to Block RAM because address size (3) smaller than threshold (5) --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 2 Input 24 Bit Adders := 1 3 Input 13 Bit Adders := 2 2 Input 12 Bit Adders := 7 2 Input 11 Bit Adders := 1 2 Input 8 Bit Adders := 1 4 Input 8 Bit Adders := 1 3 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 4 Bit Adders := 4 3 Input 4 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 31 Bit Registers := 1 26 Bit Registers := 1 24 Bit Registers := 1 12 Bit Registers := 10 11 Bit Registers := 2 10 Bit Registers := 1 8 Bit Registers := 30 7 Bit Registers := 1 6 Bit Registers := 1 5 Bit Registers := 2 4 Bit Registers := 16 3 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 42 +---Muxes : 3 Input 31 Bit Muxes := 1 2 Input 26 Bit Muxes := 1 2 Input 24 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 12 Bit Muxes := 10 2 Input 11 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 38 Input 8 Bit Muxes := 1 3 Input 8 Bit Muxes := 20 2 Input 7 Bit Muxes := 10 3 Input 6 Bit Muxes := 2 2 Input 6 Bit Muxes := 13 4 Input 6 Bit Muxes := 2 5 Input 6 Bit Muxes := 1 3 Input 5 Bit Muxes := 2 2 Input 5 Bit Muxes := 4 4 Input 5 Bit Muxes := 6 5 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 9 3 Input 4 Bit Muxes := 3 4 Input 4 Bit Muxes := 3 3 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 9 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 4 18 Input 2 Bit Muxes := 1 3 Input 2 Bit Muxes := 2 38 Input 2 Bit Muxes := 6 2 Input 1 Bit Muxes := 24 4 Input 1 Bit Muxes := 2 18 Input 1 Bit Muxes := 5 38 Input 1 Bit Muxes := 5 3 Input 1 Bit Muxes := 6 8 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module GPIO_demo Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 31 Bit Registers := 1 8 Bit Registers := 26 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 3 Input 31 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 3 Input 8 Bit Muxes := 20 2 Input 7 Bit Muxes := 10 2 Input 6 Bit Muxes := 10 2 Input 4 Bit Muxes := 1 9 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 8 Input 1 Bit Muxes := 1 Module debouncer Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 5 Module UART_TX_CTRL Detailed RTL Component Info : +---Registers : 10 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 1 Module Ps2Interface Detailed RTL Component Info : +---Adders : 2 Input 11 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 4 Bit Adders := 3 +---Registers : 11 Bit Registers := 2 8 Bit Registers := 1 7 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 17 +---Muxes : 2 Input 11 Bit Muxes := 1 3 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 3 Input 4 Bit Muxes := 2 3 Input 3 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 18 Input 2 Bit Muxes := 1 18 Input 1 Bit Muxes := 5 2 Input 1 Bit Muxes := 7 4 Input 1 Bit Muxes := 1 Module MouseCtl Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 2 Input 24 Bit Adders := 1 2 Input 12 Bit Adders := 4 2 Input 8 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 24 Bit Registers := 1 12 Bit Registers := 6 8 Bit Registers := 3 6 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 17 +---Muxes : 2 Input 26 Bit Muxes := 1 2 Input 24 Bit Muxes := 1 2 Input 12 Bit Muxes := 10 2 Input 9 Bit Muxes := 2 38 Input 8 Bit Muxes := 1 3 Input 6 Bit Muxes := 2 2 Input 6 Bit Muxes := 3 4 Input 6 Bit Muxes := 2 5 Input 6 Bit Muxes := 1 3 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 6 5 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 3 3 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 3 2 Input 4 Bit Muxes := 1 3 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 2 2 Input 2 Bit Muxes := 1 38 Input 2 Bit Muxes := 6 38 Input 1 Bit Muxes := 5 2 Input 1 Bit Muxes := 5 3 Input 1 Bit Muxes := 6 Module MouseDisplay Detailed RTL Component Info : +---Adders : 3 Input 13 Bit Adders := 2 2 Input 12 Bit Adders := 3 3 Input 4 Bit Adders := 2 +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 1 Module vga_ctrl Detailed RTL Component Info : +---Adders : 4 Input 8 Bit Adders := 1 3 Input 8 Bit Adders := 2 +---Registers : 12 Bit Registers := 4 4 Bit Registers := 9 1 Bit Registers := 5 +---Muxes : 2 Input 4 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[8]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[9]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[10]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/x_max_reg[11]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[0]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[1]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[2]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[3]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[4]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[5]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[6]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[7]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[8]' (FDSE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[9]' INFO: [Synth 8-3886] merging instance 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[10]' (FDRE) to 'Inst_vga_ctrl/Inst_MouseCtl/y_max_reg[11]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_vga_ctrl/Inst_MouseCtl/\y_max_reg[11] ) INFO: [Synth 8-3886] merging instance 'strEnd_reg[0]' (FDSE) to 'strEnd_reg[1]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[2]' (FDRE) to 'strEnd_reg[5]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[3]' (FDSE) to 'strEnd_reg[4]' INFO: [Synth 8-3333] propagating constant 1 across sequential element (\strEnd_reg[4] ) INFO: [Synth 8-3886] merging instance 'strEnd_reg[5]' (FDRE) to 'strEnd_reg[6]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[6]' (FDRE) to 'strEnd_reg[7]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[7]' (FDRE) to 'strEnd_reg[8]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[8]' (FDRE) to 'strEnd_reg[9]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[9]' (FDRE) to 'strEnd_reg[10]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[10]' (FDRE) to 'strEnd_reg[11]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[11]' (FDRE) to 'strEnd_reg[12]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[12]' (FDRE) to 'strEnd_reg[13]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[13]' (FDRE) to 'strEnd_reg[14]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[14]' (FDRE) to 'strEnd_reg[15]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[15]' (FDRE) to 'strEnd_reg[16]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[16]' (FDRE) to 'strEnd_reg[17]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[17]' (FDRE) to 'strEnd_reg[18]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[18]' (FDRE) to 'strEnd_reg[19]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[19]' (FDRE) to 'strEnd_reg[20]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[20]' (FDRE) to 'strEnd_reg[21]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[21]' (FDRE) to 'strEnd_reg[22]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[22]' (FDRE) to 'strEnd_reg[23]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[23]' (FDRE) to 'strEnd_reg[24]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[24]' (FDRE) to 'strEnd_reg[25]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[25]' (FDRE) to 'strEnd_reg[26]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[26]' (FDRE) to 'strEnd_reg[27]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[27]' (FDRE) to 'strEnd_reg[28]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[28]' (FDRE) to 'strEnd_reg[29]' INFO: [Synth 8-3886] merging instance 'strEnd_reg[29]' (FDRE) to 'strEnd_reg[30]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\strEnd_reg[30] ) INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][7]' (FDRE) to 'sendStr_reg[26][1]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][7]' (FDRE) to 'sendStr_reg[26][1]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][7]' (FDRE) to 'sendStr_reg[23][6]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][7]' (FDRE) to 'sendStr_reg[22][5]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][7]' (FDRE) to 'sendStr_reg[21][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][7]' (FDRE) to 'sendStr_reg[19][7]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][7]' (FDRE) to 'sendStr_reg[19][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][7]' (FDRE) to 'sendStr_reg[18][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][7]' (FDRE) to 'sendStr_reg[5][7]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][7]' (FDRE) to 'sendStr_reg[5][7]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][7]' (FDRE) to 'sendStr_reg[14][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[13][7]' (FDRE) to 'sendStr_reg[13][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][7]' (FDRE) to 'sendStr_reg[12][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][7]' (FDRE) to 'sendStr_reg[11][2]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][7]' (FDRE) to 'sendStr_reg[10][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][7]' (FDRE) to 'sendStr_reg[9][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][7]' (FDRE) to 'sendStr_reg[8][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[7][7]' (FDRE) to 'sendStr_reg[7][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][7]' (FDRE) to 'sendStr_reg[6][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][7]' (FDRE) to 'sendStr_reg[17][3]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[4][7] ) INFO: [Synth 8-3886] merging instance 'sendStr_reg[3][7]' (FDRE) to 'sendStr_reg[3][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[2][7]' (FDRE) to 'sendStr_reg[2][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][7]' (FDRE) to 'sendStr_reg[1][1]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[0][7]' (FDRE) to 'sendStr_reg[0][5]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][6]' (FDRE) to 'sendStr_reg[26][1]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][6]' (FDRE) to 'sendStr_reg[26][1]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[23][6]' (FDRE) to 'sendStr_reg[23][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][6]' (FDSE) to 'sendStr_reg[22][2]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[21][6]' (FDSE) to 'sendStr_reg[21][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][6]' (FDSE) to 'sendStr_reg[19][6]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][6]' (FDSE) to 'sendStr_reg[19][2]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[18][6]' (FDRE) to 'sendStr_reg[18][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][6]' (FDSE) to 'sendStr_reg[5][6]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[16][6]' (FDSE) to 'sendStr_reg[5][6]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[14][6]' (FDSE) to 'sendStr_reg[14][2]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[12][6]' (FDSE) to 'sendStr_reg[12][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[11][6]' (FDSE) to 'sendStr_reg[11][0]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[10][6]' (FDSE) to 'sendStr_reg[10][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[9][6]' (FDSE) to 'sendStr_reg[9][2]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[8][6]' (FDRE) to 'sendStr_reg[8][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[6][6]' (FDSE) to 'sendStr_reg[6][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[5][6]' (FDSE) to 'sendStr_reg[5][3]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[4][6]' (FDSE) to 'sendStr_reg[4][1]' INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[3][6] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[2][6] ) INFO: [Synth 8-3886] merging instance 'sendStr_reg[1][6]' (FDRE) to 'sendStr_reg[1][5]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[26][5]' (FDRE) to 'sendStr_reg[26][1]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[24][5]' (FDRE) to 'sendStr_reg[26][1]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[22][5]' (FDRE) to 'sendStr_reg[22][4]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[20][5]' (FDRE) to 'sendStr_reg[19][5]' INFO: [Synth 8-3886] merging instance 'sendStr_reg[19][5]' (FDRE) to 'sendStr_reg[19][0]' INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[18][5] ) INFO: [Synth 8-3886] merging instance 'sendStr_reg[17][5]' (FDRE) to 'sendStr_reg[5][5]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[8][5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[22][4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[13][4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[12][4] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[10][4] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[7][4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[16][3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[9][3] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[5][3] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[19][2] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[13][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[11][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[10][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[7][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[6][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[23][1] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[22][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[21][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[19][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[14][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[3][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[1][1] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[0][1] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[26][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[24][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[23][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[21][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[18][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[14][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[11][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[9][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[8][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[4][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[2][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sendStr_reg[1][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sendStr_reg[0][0] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (Inst_UART_TX_CTRL/\txData_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uartData_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (Inst_UART_TX_CTRL/\txData_reg[8] ) WARNING: [Synth 8-3332] Sequential element (txData_reg[9]) is unused and will be removed from module UART_TX_CTRL. WARNING: [Synth 8-3332] Sequential element (txData_reg[8]) is unused and will be removed from module UART_TX_CTRL. WARNING: [Synth 8-3332] Sequential element (zpos_reg[3]) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (zpos_reg[2]) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (zpos_reg[1]) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (zpos_reg[0]) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (left_down_reg) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (left_reg) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (middle_down_reg) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (middle_reg) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (right_down_reg) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (right_reg) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (new_event_reg) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (y_max_reg[11]) is unused and will be removed from module MouseCtl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[9]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[8]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (v_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[7]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[6]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[5]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[4]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[3]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[2]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[1]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (h_cntr_reg_dly_reg[0]) is unused and will be removed from module vga_ctrl. WARNING: [Synth 8-3332] Sequential element (strEnd_reg[30]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (strEnd_reg[4]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[0][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[1][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][6]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[2][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][6]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[3][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][7]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[4][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[6][2]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][4]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[7][2]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][5]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[8][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][3]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[9][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][4]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[10][2]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][2]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[11][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[12][4]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][4]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[13][2]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[14][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][5]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[18][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[21][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][4]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[22][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[23][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (uartData_reg[7]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][2]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[5][3]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[26][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[16][3]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[24][0]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (sendStr_reg[19][1]) is unused and will be removed from module GPIO_demo. WARNING: [Synth 8-3332] Sequential element (y_max_reg[9]) is unused and will be removed from module MouseCtl. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: +-------------+-------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +-------------+-------------+---------------+----------------+ |MouseCtl | write_data | 64x1 | LUT | |MouseDisplay | mouserom[0] | 256x2 | LUT | +-------------+-------------+---------------+----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-5365] Flop ps2_data_h_reg is being inverted and renamed to ps2_data_h_reg_inv. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |BUFG | 3| |2 |CARRY4 | 132| |3 |LUT1 | 368| |4 |LUT2 | 207| |5 |LUT3 | 91| |6 |LUT4 | 138| |7 |LUT5 | 73| |8 |LUT6 | 157| |9 |MMCME2_ADV | 1| |10 |MUXF7 | 3| |11 |FDRE | 579| |12 |FDSE | 2| |13 |IBUF | 22| |14 |IOBUF | 2| |15 |OBUF | 43| +------+-----------+------+ Report Instance Areas: +------+------------------------+------------------+------+ | |Instance |Module |Cells | +------+------------------------+------------------+------+ |1 |top | | 1821| |2 | Inst_btn_debounce |debouncer | 215| |3 | Inst_UART_TX_CTRL |UART_TX_CTRL | 133| |4 | Inst_vga_ctrl |vga_ctrl | 1100| |5 | clk_wiz_0_inst |clk_wiz_0 | 3| |6 | U0 |clk_wiz_0_clk_wiz | 3| |7 | Inst_MouseCtl |MouseCtl | 680| |8 | Inst_Ps2Interface |Ps2Interface | 211| |9 | Inst_MouseDisplay |MouseDisplay | 124| +------+------------------------+------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 692.656 ; gain = 482.824 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 76 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 692.656 ; gain = 116.863 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 692.656 ; gain = 482.824 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 157 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances INFO: [Common 17-83] Releasing license: Synthesis 245 Infos, 77 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 692.656 ; gain = 424.176 INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1/GPIO_demo.dcp' has been generated. report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 692.656 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:11:26 2021...